diff --git a/CHANGELOG.md b/CHANGELOG.md
index f9584458b..0a605edc7 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -4,6 +4,7 @@
 
 **VERSIONS:**
 
++ **[v2.7.0](#v270)**
 + **[v2.6.0](#v260)**
 + **[v2.5.1](#v251)**
 + **[v2.5.0](#v250)**
@@ -21,6 +22,239 @@
 ---
 ---
 
+## `v2.7.0`
+
++ released: 2022-12-01
+
+### `2.7.0` Changes
+
+1. **[AVR low level hal support](#font-colorredavrfont)**
+2. **[Improvements](#270-improvements)**
+3. **[Fixes](#270-fixes)**
+4. **[NEW HARDWARE](#270-new-hardware)**
+5. **[PLANET DEBUG](#270-planet-debug)**
+6. **[Collaborators](#270-collaborators)**
+
+#### <font color=red>AVR</font>
+
+**AVR MCUs supported!**
+
+|      MCU      |      MCU       |      MCU      |
+| :-----------: | :------------: | :-----------: |
+|  AT90USB1286  |  AT90USB1287   |  AT90USB646   |
+|  AT90USB647   |   ATmega128    |  ATmega1280   |
+|  ATmega1281   |   ATmega1284   |  ATmega1284P  |
+|  ATmega128A   |    ATmega16    |  ATmega164A   |
+|  ATmega164P   |  ATmega164PA   |   ATmega168   |
+|  ATmega168A   |   ATmega168P   |  ATmega168PA  |
+|  ATmega168PB  |   ATmega16A    |  ATmega16U4   |
+|  ATmega2560   |   ATmega2561   |   ATmega32    |
+|  ATmega324A   |   ATmega324P   |  ATmega324PA  |
+|  ATmega324PB  |   ATmega328    |   ATmega32A   |
+|  ATmega32U4   |    ATmega64    |   ATmega640   |
+|   ATmega644   |   ATmega644A   |  ATmega644P   |
+|  ATmega644PA  |   ATmega64A    | ATxmega128A1U |
+| ATxmega128A3  | ATxmega128A3U  | ATxmega128A4U |
+| ATxmega128B1  |  ATxmega128B3  | ATxmega128D3  |
+| ATxmega128D4  |  ATxmega16A4   | ATxmega16A4U  |
+|  ATxmega16D4  |  ATxmega16E5   | ATxmega192A3  |
+| ATxmega192A3U |  ATxmega192D3  | ATxmega256A3  |
+| ATxmega256A3B | ATxmega256A3BU | ATxmega256A3U |
+| ATxmega256D3  |  ATxmega32A4   | ATxmega32A4U  |
+|  ATxmega32D3  |  ATxmega32D4   |  ATxmega32E5  |
+| ATxmega384D3  |  ATxmega64A1U  |  ATxmega64A3  |
+| ATxmega64A3U  |  ATxmega64A4U  |  ATxmega64B1  |
+|  ATxmega64B3  |  ATxmega64D3   |  ATxmega64D4  |
+|  ATmega328PB  |   ATmega169A   |  ATmega169P   |
+|  ATmega169PA  |   ATmega325    |  ATmega3250   |
+|  ATmega3250A  |  ATmega3250P   | ATmega3250PA  |
+|  ATmega325A   |   ATmega325P   |  ATmega325PA  |
+|   ATmega329   |   ATmega3290   |  ATmega3290A  |
+|  ATmega3290P  |   ATmega329A   |  ATmega329P   |
+|  ATmega329PA  |   ATmega645    |  ATmega6450   |
+|  ATmega6450A  |  ATmega6450P   |  ATmega645A   |
+|  ATmega645P   |   ATmega649    |  ATmega6490   |
+|  ATmega6490A  |  ATmega6490P   |  ATmega649A   |
+|  ATmega649P   |
+
+**Supported modules:**
+
++ **NEW** Software I2C implemention for AVR MCUs
++ ADC (Full module support)
++ SPI (Full module support)
++ UART (Full module support)
++ I2C (Full module support)
++ PWM (Full module support)
++ GPIO (Full module support)
+
+**Files added:**
+
++ [assembly.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/common/include/assembly.h)
++ [CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/CMakeLists.txt)
++ [CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/hal_ll/CMakeLists.txt)
++ [CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/adc/CMakeLists.txt)
++ [CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/gpio/CMakeLists.txt)
++ [CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/hal_ll/CMakeLists.txt)
++ [CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/i2c/CMakeLists.txt)
++ [CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/one_wire/CMakeLists.txt)
++ [CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/spi_master/CMakeLists.txt)
++ [CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/tim/CMakeLists.txt)
++ [CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/uart/CMakeLists.txt)
++ [CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/CMakeLists.txt)
++ [CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/common/CMakeLists.txt)
++ [CMakeLists.txt](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/core/CMakeLists.txt)
++ [common_macros.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/common/include/common_macros.h)
++ [hal_ll_adc.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/adc/implementation_1/hal_ll_adc.c)
++ [hal_ll_adc.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/adc/implementation_2/hal_ll_adc.c)
++ [hal_ll_adc.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/adc/hal_ll_adc.h)
++ [hal_ll_analog_in_map.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/adc/hal_ll_analog_in_map.h)
++ [hal_ll_bit_control.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/common/include/hal_ll_bit_control.h)
++ [hal_ll_core.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/core/src/hal_ll_core.c)
++ [hal_ll_core.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/core/include/hal_ll_core.h)
++ [hal_ll_core_defines.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/core/include/hal_ll_core_defines.h)
++ [hal_ll_core_port.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/core/include/hal_ll_core_port.h)
++ [hal_ll_gpio.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/gpio/implementation_1/hal_ll_gpio.c)
++ [hal_ll_gpio.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/gpio/hal_ll_gpio.h)
++ [hal_ll_gpio_constants.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/gpio/hal_ll_gpio_constants.h)
++ [hal_ll_gpio_port.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/gpio/implementation_1/subimplementation_1/hal_ll_gpio_port.c)
++ [hal_ll_gpio_port.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/gpio/hal_ll_gpio_port.h)
++ [hal_ll_i2c_master.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/i2c/implementation_1/hal_ll_i2c_master.c)
++ [hal_ll_i2c_master.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/i2c/implementation_2/hal_ll_i2c_master.c)
++ [hal_ll_i2c_master.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/i2c/implementation_3/hal_ll_i2c_master.c)
++ [hal_ll_i2c_master.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/i2c/hal_ll_i2c_master.h)
++ [hal_ll_i2c_pin_map.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/i2c/hal_ll_i2c_pin_map.h)
++ [hal_ll_one_wire.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/one_wire/hal_ll_one_wire.c)
++ [hal_ll_one_wire.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/one_wire/hal_ll_one_wire.h)
++ [hal_ll_pin_names.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/hal_ll_pin_names.h)
++ [hal_ll_spi_master.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/spi_master/implementation_1/hal_ll_spi_master.c)
++ [hal_ll_spi_master.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/spi_master/implementation_2/hal_ll_spi_master.c)
++ [hal_ll_spi_master.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/spi_master/hal_ll_spi_master.h)
++ [hal_ll_spi_master_pin_map.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/spi_master/hal_ll_spi_master_pin_map.h)
++ [hal_ll_target.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/hal_ll_target.h)
++ [hal_ll_target_names.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/hal_ll_target_names.h)
++ [hal_ll_tim.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/tim/implementation_1/hal_ll_tim.c)
++ [hal_ll_tim.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/tim/implementation_2/hal_ll_tim.c)
++ [hal_ll_tim.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/tim/implementation_3/hal_ll_tim.c)
++ [hal_ll_tim.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/tim/hal_ll_tim.h)
++ [hal_ll_tim_pin_map.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/tim/hal_ll_tim_pin_map.h)
++ [hal_ll_uart.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/uart/implementation_1/hal_ll_uart.c)
++ [hal_ll_uart.c](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/uart/implementation_2/hal_ll_uart.c)
++ [hal_ll_uart.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/uart/hal_ll_uart.h)
++ [hal_ll_uart_pin_map.h](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/include/uart/hal_ll_uart_pin_map.h)
+
+#### `2.7.0` Improvements
+
++ Improved `Graphic Library` implementation
+  + Improvement for issue of bad conversion for special case
+  + Added check if result is `+Inf`, or `-Inf` since cast to integer is undefined
+  + Added `max` and `min` int instead
++ Added option to disable/enable whole module based on availability
+
+#### `2.7.0` Fixes
+
++ Fixed VTFT imlplementation for `PIC18F57Q43`
+  + API now returns adequate active instance for further use
++ Fixed `I2C` implementation 2 for PIC 8bit devices
+  + Restart signal is now generated adequatelly
+  + Fix impacts following devices:
+    + `PIC18F25K42`
+    + `PIC18F26K42`
+    + `PIC18F27K42`
+    + `PIC18F45K42`
+    + `PIC18F46K42`
+    + `PIC18F47K42`
+    + `PIC18F55K42`
+    + `PIC18F56K42`
+    + `PIC18F57K42`
+    + `PIC18LF25K42`
+    + `PIC18LF26K42`
+    + `PIC18LF27K42`
+    + `PIC18LF45K42`
+    + `PIC18LF46K42`
+    + `PIC18LF47K42`
+    + `PIC18LF55K42`
+    + `PIC18LF56K42`
+    + `PIC18LF57K42`
+    + `PIC18F57Q43`
++ Fixed `GPIO` implementation for `RISC-V` devices
+  + Unlock routine fixed for SWJ pins
+  + User is now available to use SWJ pins
+  + Affects all `GIGADEVICE` MCUs
++ Fixed TFT port setting for:
+  + `MCU CARD 11 FOR PIC`
+    + Set to adequate 8bit port
++ Fixed inclusion of adequate `mcu_definitions` header file for following MCUs:
+  + `STM32L100C6_AUx`
+  + `STM32L100R8_ATx`
+  + `STM32L100RB_ATx`
+  + `STM32L151C6_ATx`
+  + `STM32L151C6_AUx`
+  + `STM32L151C8_ATx`
+  + `STM32L151C8_AUx`
+  + `STM32L151CB_ATx`
+  + `STM32L151CB_AUx`
+  + `STM32L151R6_AHx`
+  + `STM32L151R6_ATx`
+  + `STM32L151R8_AHx`
+  + `STM32L151R8_ATx`
+  + `STM32L151RB_AHx`
+  + `STM32L151RB_ATx`
+  + `STM32L151RC_ATx`
+  + `STM32L151V8_AHx`
+  + `STM32L151V8_ATx`
+  + `STM32L151VB_AHx`
+  + `STM32L151VB_ATx`
+  + `STM32L151VC_ATx`
+  + `STM32L152C6_ATx`
+  + `STM32L152C6_AUx`
+  + `STM32L152C8_ATx`
+  + `STM32L152C8_AUx`
+  + `STM32L152CB_ATx`
+  + `STM32L152CB_AUx`
+  + `STM32L152R6_AHx`
+  + `STM32L152R6_ATx`
+  + `STM32L152R8_AHx`
+  + `STM32L152R8_ATx`
+  + `STM32L152RB_AHx`
+  + `STM32L152RB_ATx`
+  + `STM32L152RC_ATx`
+  + `STM32L152V8_AHx`
+  + `STM32L152V8_ATx`
+  + `STM32L152VB_AHx`
+  + `STM32L152VB_ATx`
+  + `STM32L152VC_ATx`
+  + `STM32L162RC_ATx`
+  + `STM32L162VC_ATx`
+
+#### `2.7.0` NEW HARDWARE
+
+Support added for following hardware:
+
++ [EasyAVR PRO v8](https://www.mikroe.com/easyavr-pro-v8)
++ [SIBRAIN FOR ATMEGA3250](https://www.mikroe.com/sibrain-for-atmega3250)
++ [SIBRAIN FOR ATMEGA6450](https://www.mikroe.com/sibrain-for-atmega6450)
++ [EasyAVR v7](https://www.mikroe.com/easyavr)
+
+#### `2.7.0` PLANET DEBUG
+
++ Incoming update with newly released AVR boards
+
+#### `2.7.0` Collaborators
+
+**We would like to thank the following people for contributing:**
+
++ **[@Valentin Hubert](https://github.com/vahu72)**
+  + **Software I2C** full implementation for AVR
+    + **[view files](https://github.com/MikroElektronika/mikrosdk_v2/blob/master/targets/avr_8bit/mikroe/avr/src/i2c/implementation_3/hal_ll_i2c_master.c)**
+
+---
+**[BACK TO TOP OF 2.7.0](#v270)**
+
+---
+**[BACK TO TOP](#changelog)**
+
+---
+
 ## `v2.6.0`
 
 + released: 2022-06-16
@@ -39,7 +273,7 @@
 **RISV-V MCU architecture supported!**
 
 |      MCU      |      MCU      |
-|:-------------:|:-------------:|
+| :-----------: | :-----------: |
 | GD32VF103C4T6 | GD32VF103C6T6 |
 | GD32VF103C8T6 | GD32VF103CBT6 |
 | GD32VF103R4T6 | GD32VF103R6T6 |
@@ -218,31 +452,31 @@ Support added for following hardware:
 
 List of MCU's affected:
 
-|  MCU NAME    |  MCU NAME    |  MCU NAME    |  MCU NAME    |  MCU NAME    |
-|:------------:|:------------:|:------------:|:------------:|:------------:|
+|   MCU NAME   |   MCU NAME   |   MCU NAME   |   MCU NAME   |   MCU NAME   |
+| :----------: | :----------: | :----------: | :----------: | :----------: |
 | PIC18F24J11  | PIC18F24J50  | PIC18F24K50  | PIC18F25J11  | PIC18F25J50  |
 | PIC18F25K50  | PIC18F25K80  | PIC18F26J11  | PIC18F26J13  | PIC18F26J50  |
 | PIC18F26J53  | PIC18F26K22  | PIC18F26K80  | PIC18F27J13  | PIC18F27J53  |
-| PIC18F4455   | PIC18F4458   | PIC18F44J11  | PIC18F44J50  | PIC18F4515   |
-| PIC18F4525   | PIC18F4550   | PIC18F4553   | PIC18F4585   | PIC18F45J11  |
-| PIC18F45J50  | PIC18F45K22  | PIC18F45K50  | PIC18F45K80  | PIC18F4610   |
-| PIC18F4620   | PIC18F4680   | PIC18F4682   | PIC18F4685   | PIC18F46J11  |
+|  PIC18F4455  |  PIC18F4458  | PIC18F44J11  | PIC18F44J50  |  PIC18F4515  |
+|  PIC18F4525  |  PIC18F4550  |  PIC18F4553  |  PIC18F4585  | PIC18F45J11  |
+| PIC18F45J50  | PIC18F45K22  | PIC18F45K50  | PIC18F45K80  |  PIC18F4610  |
+|  PIC18F4620  |  PIC18F4680  |  PIC18F4682  |  PIC18F4685  | PIC18F46J11  |
 | PIC18F46J13  | PIC18F46J50  | PIC18F46J53  | PIC18F46K22  | PIC18F46K80  |
-| PIC18F47J13  | PIC18F47J53  | PIC18F6520   | PIC18F6525   | PIC18F6527   |
-| PIC18F6585   | PIC18F65J10  | PIC18F65J11  | PIC18F65J15  | PIC18F65J50  |
-| PIC18F65J94  | PIC18F65K22  | PIC18F65K80  | PIC18F65K90  | PIC18F6620   |
-| PIC18F6621   | PIC18F6622   | PIC18F6627   | PIC18F6628   | PIC18F6680   |
+| PIC18F47J13  | PIC18F47J53  |  PIC18F6520  |  PIC18F6525  |  PIC18F6527  |
+|  PIC18F6585  | PIC18F65J10  | PIC18F65J11  | PIC18F65J15  | PIC18F65J50  |
+| PIC18F65J94  | PIC18F65K22  | PIC18F65K80  | PIC18F65K90  |  PIC18F6620  |
+|  PIC18F6621  |  PIC18F6622  |  PIC18F6627  |  PIC18F6628  |  PIC18F6680  |
 | PIC18F66J10  | PIC18F66J11  | PIC18F66J15  | PIC18F66J16  | PIC18F66J50  |
 | PIC18F66J55  | PIC18F66J60  | PIC18F66J65  | PIC18F66J94  | PIC18F66K22  |
-| PIC18F66K80  | PIC18F66K90  | PIC18F6720   | PIC18F6722   | PIC18F6723   |
+| PIC18F66K80  | PIC18F66K90  |  PIC18F6720  |  PIC18F6722  |  PIC18F6723  |
 | PIC18F67J10  | PIC18F67J11  | PIC18F67J50  | PIC18F67J60  | PIC18F67J94  |
-| PIC18F67K22  | PIC18F67K90  | PIC18F8520   | PIC18F8525   | PIC18F8527   |
-| PIC18F8585   | PIC18F85J10  | PIC18F85J11  | PIC18F85J15  | PIC18F85J50  |
-| PIC18F85J94  | PIC18F85K22  | PIC18F85K90  | PIC18F8620   | PIC18F8621   |
-| PIC18F8622   | PIC18F8627   | PIC18F8628   | PIC18F8680   | PIC18F86J10  |
+| PIC18F67K22  | PIC18F67K90  |  PIC18F8520  |  PIC18F8525  |  PIC18F8527  |
+|  PIC18F8585  | PIC18F85J10  | PIC18F85J11  | PIC18F85J15  | PIC18F85J50  |
+| PIC18F85J94  | PIC18F85K22  | PIC18F85K90  |  PIC18F8620  |  PIC18F8621  |
+|  PIC18F8622  |  PIC18F8627  |  PIC18F8628  |  PIC18F8680  | PIC18F86J10  |
 | PIC18F86J11  | PIC18F86J15  | PIC18F86J16  | PIC18F86J50  | PIC18F86J55  |
 | PIC18F86J60  | PIC18F86J65  | PIC18F86J94  | PIC18F86K22  | PIC18F86K90  |
-| PIC18F8720   | PIC18F8722   | PIC18F8723   | PIC18F87J10  | PIC18F87J11  |
+|  PIC18F8720  |  PIC18F8722  |  PIC18F8723  | PIC18F87J10  | PIC18F87J11  |
 | PIC18F87J50  | PIC18F87J60  | PIC18F87J94  | PIC18F87K22  | PIC18F87K90  |
 | PIC18F95J94  | PIC18F96J60  | PIC18F96J65  | PIC18F96J94  | PIC18F97J60  |
 | PIC18F97J94  | PIC18LF24J11 | PIC18LF24J50 | PIC18LF24K50 | PIC18LF25J11 |
@@ -571,32 +805,32 @@ For more information, please refer to main script [DESCRIPTION](./scripts/ReadMe
 
 + **Support added for 71 Texas Instruments TIVA MCU's**
 
-| CHIP NAME       | CHIP NAME       | CHIP NAME       |
-|-----------------|-----------------|-----------------|
-| TM4C1230C3PM    | TM4C1230D5PM    | TM4C1230E6PM    |
-| TM4C1230H6PM    | TM4C1231C3PM    | TM4C1231D5PM    |
-| TM4C1231D5PZ    | TM4C1231E6PM    | TM4C1231E6PZ    |
-| TM4C1231H6PGE   | TM4C1231H6PM    | TM4C1231H6PZ    |
-| TM4C1232C3PM    | TM4C1232D5PM    | TM4C1232E6PM    |
-| TM4C1232H6PM    | TM4C1233C3PM    | TM4C1233D5PM    |
-| TM4C1233D5PZ    | TM4C1233E6PM    | TM4C1233E6PZ    |
-| TM4C1233H6PGE   | TM4C1233H6PM    | TM4C1233H6PZ    |
-| TM4C1236D5PM    | TM4C1236E6PM    | TM4C1236H6PM    |
-| TM4C1237D5PM    | TM4C1237D5PZ    | TM4C1237E6PM    |
-| TM4C1237E6PZ    | TM4C1237H6PGE   | TM4C1237H6PM    |
-| TM4C1237H6PZ    | TM4C123AE6PM    | TM4C123AH6PM    |
-| TM4C123BE6PM    | TM4C123BE6PZ    | TM4C123BH6PGE   |
-| TM4C123BH6PM    | TM4C123BH6PZ    | TM4C123BH6ZRB   |
-| TM4C123FE6PM    | TM4C123FH6PM    | TM4C123GE6PM    |
-| TM4C123GE6PZ    | TM4C123GH6PGE   | TM4C123GH6PM    |
-| TM4C123GH6PZ    | TM4C123GH6ZRB   | TM4C123GH6ZXR   |
-| TM4C1290NCPDT   | TM4C1290NCZAD   | TM4C1292NCPDT   |
-| TM4C1292NCZAD   | TM4C1294KCPDT   | TM4C1294NCPDT   |
-| TM4C1294NCZAD   | TM4C1297NCZAD   | TM4C1299KCZAD   |
-| TM4C1299NCZAD   | TM4C129CNCPDT   | TM4C129CNCZAD   |
-| TM4C129DNCPDT   | TM4C129DNCZAD   | TM4C129EKCPDT   |
-| TM4C129ENCPDT   | TM4C129ENCZAD   | TM4C129LNCZAD   |
-| TM4C129XKCZAD   | TM4C129XNCZAD   |
+| CHIP NAME     | CHIP NAME     | CHIP NAME     |
+| ------------- | ------------- | ------------- |
+| TM4C1230C3PM  | TM4C1230D5PM  | TM4C1230E6PM  |
+| TM4C1230H6PM  | TM4C1231C3PM  | TM4C1231D5PM  |
+| TM4C1231D5PZ  | TM4C1231E6PM  | TM4C1231E6PZ  |
+| TM4C1231H6PGE | TM4C1231H6PM  | TM4C1231H6PZ  |
+| TM4C1232C3PM  | TM4C1232D5PM  | TM4C1232E6PM  |
+| TM4C1232H6PM  | TM4C1233C3PM  | TM4C1233D5PM  |
+| TM4C1233D5PZ  | TM4C1233E6PM  | TM4C1233E6PZ  |
+| TM4C1233H6PGE | TM4C1233H6PM  | TM4C1233H6PZ  |
+| TM4C1236D5PM  | TM4C1236E6PM  | TM4C1236H6PM  |
+| TM4C1237D5PM  | TM4C1237D5PZ  | TM4C1237E6PM  |
+| TM4C1237E6PZ  | TM4C1237H6PGE | TM4C1237H6PM  |
+| TM4C1237H6PZ  | TM4C123AE6PM  | TM4C123AH6PM  |
+| TM4C123BE6PM  | TM4C123BE6PZ  | TM4C123BH6PGE |
+| TM4C123BH6PM  | TM4C123BH6PZ  | TM4C123BH6ZRB |
+| TM4C123FE6PM  | TM4C123FH6PM  | TM4C123GE6PM  |
+| TM4C123GE6PZ  | TM4C123GH6PGE | TM4C123GH6PM  |
+| TM4C123GH6PZ  | TM4C123GH6ZRB | TM4C123GH6ZXR |
+| TM4C1290NCPDT | TM4C1290NCZAD | TM4C1292NCPDT |
+| TM4C1292NCZAD | TM4C1294KCPDT | TM4C1294NCPDT |
+| TM4C1294NCZAD | TM4C1297NCZAD | TM4C1299KCZAD |
+| TM4C1299NCZAD | TM4C129CNCPDT | TM4C129CNCZAD |
+| TM4C129DNCPDT | TM4C129DNCZAD | TM4C129EKCPDT |
+| TM4C129ENCPDT | TM4C129ENCZAD | TM4C129LNCZAD |
+| TM4C129XKCZAD | TM4C129XNCZAD |
 
 **Supported modules:**
 
@@ -789,7 +1023,7 @@ Examples are used for testing mikroSDK specific module cases.
 + **Support added for 147 NXP Kinetis MCU's**
 
 | CHIP NAME       | CHIP NAME       | CHIP NAME       | CHIP NAME       | CHIP NAME       |
-|-----------------|-----------------|-----------------|-----------------|-----------------|
+| --------------- | --------------- | --------------- | --------------- | --------------- |
 | MK20DN128VFM5   | MK20DN128VFT5   | MK20DN128VLF5   | MK20DN128VLH5   | MK20DN128VMP5   |
 | MK20DN32VFM5    | MK20DN32VFT5    | MK20DN32VLF5    | MK20DN32VLH5    | MK20DN32VMP5    |
 | MK20DN64VFM5    | MK20DN64VFT5    | MK20DN64VLF5    | MK20DN64VLH5    | MK20DN64VMP5    |
@@ -1398,7 +1632,7 @@ For more information, please refer to main script [DESCRIPTION](./scripts/ReadMe
 **MX CHIPS:**
 
 | CHIP NAME       | CHIP NAME        | CHIP NAME       | CHIP NAME        | CHIP NAME       |
-|-----------------|------------------|-----------------|------------------|-----------------|
+| --------------- | ---------------- | --------------- | ---------------- | --------------- |
 | PIC32MX110F016B | PIC32MX210F016B  | PIC32MX320F032H | PIC32MX440F256H  | PIC32MX570F512L |
 | PIC32MX110F016C | PIC32MX210F016C  | PIC32MX320F064H | PIC32MX440F512H  | PIC32MX575F256H |
 | PIC32MX110F016D | PIC32MX210F016D  | PIC32MX320F128H | PIC32MX450F128H  | PIC32MX575F256L |
@@ -1426,7 +1660,7 @@ For more information, please refer to main script [DESCRIPTION](./scripts/ReadMe
 **MZ CHIPS:**
 
 | CHIP NAME         | CHIP NAME         | CHIP NAME         | CHIP NAME         |
-|-------------------|-------------------|-------------------|-------------------|
+| ----------------- | ----------------- | ----------------- | ----------------- |
 | PIC32MZ0512EFE064 | PIC32MZ1024EFE064 | PIC32MZ1024EFH064 | PIC32MZ2048EFG064 |
 | PIC32MZ0512EFE100 | PIC32MZ1024EFE100 | PIC32MZ1024EFH100 | PIC32MZ2048EFG100 |
 | PIC32MZ0512EFE124 | PIC32MZ1024EFE124 | PIC32MZ1024EFH124 | PIC32MZ2048EFG124 |
diff --git a/CMakeLists.txt b/CMakeLists.txt
index d78c2a5ec..6462cb8e9 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -1,8 +1,8 @@
 cmake_minimum_required(VERSION 3.11)
 if (${TOOLCHAIN_LANGUAGE} MATCHES "MikroC")
-    project(MikroSDK VERSION 2.6.0 LANGUAGES MikroC)
+    project(MikroSDK VERSION 2.7.0 LANGUAGES MikroC)
 else()
-    project(MikroSDK VERSION 2.6.0 LANGUAGES C ASM)
+    project(MikroSDK VERSION 2.7.0 LANGUAGES C ASM)
     find_package(MikroC.Core)
     add_compile_options("-fms-extensions")
 endif()
diff --git a/README.md b/README.md
index 22074f7b2..880a69ae0 100644
--- a/README.md
+++ b/README.md
@@ -1,6 +1,6 @@
 # mikroSDK 2.0
 
-[![SDK Version](https://img.shields.io/badge/mikroSDK%20version-2.6.0-gold)](https://github.com/MikroElektronika/mikrosdk_v2/tree/mikroSDK-2.6.0)
+[![SDK Version](https://img.shields.io/badge/mikroSDK%20version-2.7.0-gold)](https://github.com/MikroElektronika/mikrosdk_v2/tree/mikroSDK-2.7.0)
 
 ---
 ## About
diff --git a/REQUIREMENTS.md b/REQUIREMENTS.md
index 3c0d0e3ce..3dad64d02 100644
--- a/REQUIREMENTS.md
+++ b/REQUIREMENTS.md
@@ -17,6 +17,9 @@
 
 **SDK requirements by version:**
 
+* **v2.7.0**
+  * [`FLASH1`]
+  * [`RAM1`]
 * **v2.6.0**
   * [`FLASH1`]
   * [`RAM1`]
diff --git a/SUPPORTED_CHIP_LIST.md b/SUPPORTED_CHIP_LIST.md
index 2f5c763ca..e7a828938 100644
--- a/SUPPORTED_CHIP_LIST.md
+++ b/SUPPORTED_CHIP_LIST.md
@@ -6,6 +6,7 @@
 
 - [List of supported chips](#list-of-supported-chips)
   - [CONTENT](#content)
+    - [AVR](#avr)
     - [GIGADEVICE](#gigadevice)
     - [TIVA](#tiva)
     - [NXP](#nxp)
@@ -15,426 +16,540 @@
 
 ---
 
+### AVR
+
+|   CHIP NAME    | ARCHITECTURE |  REQUIREMENTS   | SUPPORTED IN VERSION |        GPIO        |        ADC         |                 I2C                 |        PWM         |        SPI         |        UART        |      ONE WIRE      |
+| :------------: | :----------: | :-------------: | :------------------: | :----------------: | :----------------: | :---------------------------------: | :----------------: | :----------------: | :----------------: | :----------------: |
+|  AT90USB1286   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  AT90USB1287   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   AT90USB646   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   AT90USB647   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega128    |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega1280   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega1281   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega1284   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega1284P   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega128A   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|    ATmega16    |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega164A   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega164P   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega164PA   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega168    |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega168A   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega168P   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega168PA   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega168PB   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega16A    |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega16U4   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega2560   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega2561   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|    ATmega32    |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega324A   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega324P   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega324PA   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega324PB   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega328    |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega32A    |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega32U4   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|    ATmega64    |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega640    |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega644    |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega644A   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega644P   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega644PA   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega64A    |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| ATxmega128A1U  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega128A3  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| ATxmega128A3U  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| ATxmega128A4U  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega128B1  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega128B3  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega128D3  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega128D4  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega16A4   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega16A4U  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega16D4   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega16E5   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega192A3  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| ATxmega192A3U  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega192D3  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega256A3  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| ATxmega256A3B  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| ATxmega256A3BU |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| ATxmega256A3U  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega256D3  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega32A4   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega32A4U  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega32D3   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega32D4   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega32E5   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega384D3  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega64A1U  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega64A3   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega64A3U  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega64A4U  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega64B1   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega64B3   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega64D3   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATxmega64D4   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega328PB   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: |         :heavy_check_mark:          | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega169A   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega169P   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega169PA   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega325    |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega3250   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega3250A   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega3250P   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega3250PA  |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega325A   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega325P   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega325PA   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega329    |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega3290   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega3290A   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega3290P   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega329A   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega329P   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega329PA   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega645    |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega6450   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega6450A   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega6450P   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega645A   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega645P   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega649    |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega6490   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega6490A   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  ATmega6490P   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega649A   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   ATmega649P   |   AVR 8bit   | `FLASH1`;`RAM1` |       `2.7.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: [:one:](#note_2) | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+
+> **_NOTE:_**
+>> <a name="note_2">:one:</a> Chip doesn't have specified hardware module.
+>> Software implementation is used.
+
+---
+
 ### GIGADEVICE
 
-|    CHIP NAME      |  ARCHITECTURE  |  REQUIREMENTS   |  SUPPORTED IN VERSION  |        GPIO        |         ADC        |         I2C        |         PWM        |         SPI        |         UART       |       ONE WIRE     |
-|:-----------------:|:--------------:|:---------------:|:----------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|
-|   GD32VF103C4T6   |     RISC-V     | `FLASH1`;`RAM1` |        `2.6.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   GD32VF103C6T6   |     RISC-V     | `FLASH1`;`RAM1` |        `2.6.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   GD32VF103C8T6   |     RISC-V     | `FLASH1`;`RAM1` |        `2.6.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   GD32VF103CBT6   |     RISC-V     | `FLASH1`;`RAM1` |        `2.6.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   GD32VF103R4T6   |     RISC-V     | `FLASH1`;`RAM1` |        `2.6.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   GD32VF103R6T6   |     RISC-V     | `FLASH1`;`RAM1` |        `2.6.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   GD32VF103R8T6   |     RISC-V     | `FLASH1`;`RAM1` |        `2.6.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   GD32VF103RBT6   |     RISC-V     | `FLASH1`;`RAM1` |        `2.6.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   GD32VF103T4U6   |     RISC-V     | `FLASH1`;`RAM1` |        `2.6.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   GD32VF103T6U6   |     RISC-V     | `FLASH1`;`RAM1` |        `2.6.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   GD32VF103T8U6   |     RISC-V     | `FLASH1`;`RAM1` |        `2.6.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   GD32VF103TBU6   |     RISC-V     | `FLASH1`;`RAM1` |        `2.6.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   GD32VF103V8T6   |     RISC-V     | `FLASH1`;`RAM1` |        `2.6.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   GD32VF103VBT6   |     RISC-V     | `FLASH1`;`RAM1` |        `2.6.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   CHIP NAME   | ARCHITECTURE |  REQUIREMENTS   | SUPPORTED IN VERSION |        GPIO        |        ADC         |        I2C         |        PWM         |        SPI         |        UART        |      ONE WIRE      |
+| :-----------: | :----------: | :-------------: | :------------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: |
+| GD32VF103C4T6 |    RISC-V    | `FLASH1`;`RAM1` |       `2.6.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| GD32VF103C6T6 |    RISC-V    | `FLASH1`;`RAM1` |       `2.6.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| GD32VF103C8T6 |    RISC-V    | `FLASH1`;`RAM1` |       `2.6.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| GD32VF103CBT6 |    RISC-V    | `FLASH1`;`RAM1` |       `2.6.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| GD32VF103R4T6 |    RISC-V    | `FLASH1`;`RAM1` |       `2.6.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| GD32VF103R6T6 |    RISC-V    | `FLASH1`;`RAM1` |       `2.6.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| GD32VF103R8T6 |    RISC-V    | `FLASH1`;`RAM1` |       `2.6.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| GD32VF103RBT6 |    RISC-V    | `FLASH1`;`RAM1` |       `2.6.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| GD32VF103T4U6 |    RISC-V    | `FLASH1`;`RAM1` |       `2.6.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| GD32VF103T6U6 |    RISC-V    | `FLASH1`;`RAM1` |       `2.6.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| GD32VF103T8U6 |    RISC-V    | `FLASH1`;`RAM1` |       `2.6.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| GD32VF103TBU6 |    RISC-V    | `FLASH1`;`RAM1` |       `2.6.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| GD32VF103V8T6 |    RISC-V    | `FLASH1`;`RAM1` |       `2.6.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| GD32VF103VBT6 |    RISC-V    | `FLASH1`;`RAM1` |       `2.6.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
 
 ---
 
 ### TIVA
 
-|    CHIP NAME      |  ARCHITECTURE  |  REQUIREMENTS   |  SUPPORTED IN VERSION  |        GPIO        |         ADC        |         I2C        |         PWM        |         SPI        |         UART       |       ONE WIRE     |
-|:-----------------:|:--------------:|:---------------:|:----------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|
-|   TM4C1230C3PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1230D5PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1230E6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1230H6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1231C3PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1231D5PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1231D5PZ    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1231E6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1231E6PZ    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1231H6PGE   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1231H6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1231H6PZ    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1232C3PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1232D5PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1232E6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1232H6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1233C3PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1233D5PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1233D5PZ    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1233E6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1233E6PZ    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1233H6PGE   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1233H6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1233H6PZ    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1236D5PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1236E6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1236H6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1237D5PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1237D5PZ    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1237E6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1237E6PZ    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1237H6PGE   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1237H6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1237H6PZ    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C123AE6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C123AH6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C123BE6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C123BE6PZ    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C123BH6PGE   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C123BH6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C123BH6PZ    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C123BH6ZRB   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C123FE6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C123FH6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C123GE6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C123GE6PZ    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C123GH6PGE   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C123GH6PM    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C123GH6PZ    |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C123GH6ZRB   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C123GH6ZXR   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1290NCPDT   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1290NCZAD   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1292NCPDT   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1292NCZAD   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1294KCPDT   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1294NCPDT   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1294NCZAD   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1297NCZAD   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1299KCZAD   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C1299NCZAD   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C129CNCPDT   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C129CNCZAD   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C129DNCPDT   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C129DNCZAD   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C129EKCPDT   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C129ENCPDT   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C129ENCZAD   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C129LNCZAD   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C129XKCZAD   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|   TM4C129XNCZAD   |      ARM       | `FLASH1`;`RAM1` |        `2.3.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   CHIP NAME   | ARCHITECTURE |  REQUIREMENTS   | SUPPORTED IN VERSION |        GPIO        |        ADC         |        I2C         |        PWM         |        SPI         |        UART        |      ONE WIRE      |
+| :-----------: | :----------: | :-------------: | :------------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: |
+| TM4C1230C3PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1230D5PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1230E6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1230H6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1231C3PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1231D5PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1231D5PZ  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1231E6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1231E6PZ  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1231H6PGE |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1231H6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1231H6PZ  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1232C3PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1232D5PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1232E6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1232H6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1233C3PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1233D5PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1233D5PZ  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1233E6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1233E6PZ  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1233H6PGE |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1233H6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1233H6PZ  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1236D5PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1236E6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1236H6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1237D5PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1237D5PZ  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1237E6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1237E6PZ  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1237H6PGE |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1237H6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1237H6PZ  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C123AE6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C123AH6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C123BE6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C123BE6PZ  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C123BH6PGE |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C123BH6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C123BH6PZ  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C123BH6ZRB |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C123FE6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C123FH6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C123GE6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C123GE6PZ  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C123GH6PGE |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C123GH6PM  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C123GH6PZ  |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C123GH6ZRB |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C123GH6ZXR |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1290NCPDT |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1290NCZAD |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1292NCPDT |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1292NCZAD |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1294KCPDT |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1294NCPDT |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1294NCZAD |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1297NCZAD |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1299KCZAD |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C1299NCZAD |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C129CNCPDT |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C129CNCZAD |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C129DNCPDT |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C129DNCZAD |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C129EKCPDT |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C129ENCPDT |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C129ENCZAD |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C129LNCZAD |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C129XKCZAD |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| TM4C129XNCZAD |     ARM      | `FLASH1`;`RAM1` |       `2.3.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
 
 ---
 
 ### NXP
 
-|    CHIP NAME      |  ARCHITECTURE  |  REQUIREMENTS   |  SUPPORTED IN VERSION  |        GPIO        |         ADC        |         I2C        |         PWM        |         SPI        |         UART       |       ONE WIRE     |
-|:-----------------:|:--------------:|:---------------:|:----------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|
-|  MK20DN128VFM5    |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DN128VFT5    |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DN128VLF5    |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DN128VLH5    |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DN128VMP5    |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DN32VFM5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DN32VFT5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DN32VLF5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DN32VLH5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DN32VMP5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DN64VFM5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DN64VFT5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DN64VLF5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DN64VLH5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DN64VMP5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DX128VFM5    |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DX128VFT5    |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DX128VLF5    |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DX128VLH5    |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DX32VFM5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DX32VFT5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DX32VLF5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DX32VLH5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DX32VMP5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DX64VFM5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DX64VFT5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DX64VLF5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DX64VLH5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK20DX64VMP5     |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN128CAH12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN128VDC10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN128VLH10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN128VLL10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN128VMP10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN1M0AVLH12  |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN1M0AVLK12  |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN1M0AVLL12  |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN1M0AVLQ12  |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN1M0AVMC12  |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN1M0AVMD12  |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN1M0VLH12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN1M0VLK12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN1M0VLL12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN1M0VLQ12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN1M0VMC12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN1M0VMD12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN256CAH12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN256VDC12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN256VLH12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN256VLL12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN256VMP12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN512CAP12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN512VDC12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN512VFX12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN512VLH12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN512VLL12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FN512VMP12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FX512AVLH12  |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FX512AVLK12  |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FX512AVLL12  |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FX512AVLQ12  |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FX512AVMC12  |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FX512AVMD12  |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FX512VLH12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FX512VLK12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FX512VLL12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FX512VLQ12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FX512VMC12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK22FX512VMD12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK51DN256CLQ10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK51DN256CMD10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK51DN512CLL10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK51DN512CLQ10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK51DN512CMC10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK51DN512CMD10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK51DX256CLK10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK51DX256CLL10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK51DX256CMC10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK53DN512CLQ10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK53DN512CMD10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK53DX256CLQ10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK53DX256CMD10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK60DN256VLL10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK60DN256VLQ10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK60DN256VMC10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK60DN256VMD10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK60DN512VLL10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK60DN512VLQ10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK60DN512VMC10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK60DN512VMD10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK60DX256VLL10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK60DX256VLQ10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK60DX256VMC10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK60DX256VMD10   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK64FN1M0CAJ12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK64FN1M0VDC12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK64FN1M0VLL12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK64FN1M0VLQ12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK64FN1M0VMD12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK64FX512VDC12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK64FX512VLL12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK64FX512VLQ12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK64FX512VMD12   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK65FN2M0CAC18   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK65FN2M0VMI18   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK65FX1M0CAC18   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK65FX1M0VMI18   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK66FN2M0VLQ18   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK66FN2M0VMD18   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK66FX1M0VLQ18   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK66FX1M0VMD18   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK80FN256VDC15   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK80FN256VLL15   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK80FN256VLQ15   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK82FN256VDC15   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK82FN256VLL15   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MK82FN256VLQ15   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV42F128VLF16   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV42F128VLH16   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV42F128VLL16   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV42F256VLH16   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV42F256VLL16   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV42F64VLF16    |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV42F64VLH16    |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV44F128VLF16   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV44F128VLH16   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV44F128VLL16   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV44F256VLH16   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV44F256VLL16   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV44F64VLF16    |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV44F64VLH16    |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV46F128VLH16   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV46F128VLL16   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV46F256VLH16   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV46F256VLL16   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV56F1M0VLL24   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV56F1M0VLQ24   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV56F1M0VMD24   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV56F512VLL24   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV56F512VLQ24   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV56F512VMD24   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV58F1M0VLL24   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV58F1M0VLQ24   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV58F1M0VMD24   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV58F512VLL24   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV58F512VLQ24   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-|  MKV58F512VMD24   |      ARM       | `FLASH1`;`RAM1` |        `2.2.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|    CHIP NAME    | ARCHITECTURE |  REQUIREMENTS   | SUPPORTED IN VERSION |        GPIO        |        ADC         |        I2C         |        PWM         |        SPI         |        UART        |      ONE WIRE      |
+| :-------------: | :----------: | :-------------: | :------------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: |
+|  MK20DN128VFM5  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DN128VFT5  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DN128VLF5  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DN128VLH5  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DN128VMP5  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DN32VFM5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DN32VFT5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DN32VLF5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DN32VLH5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DN32VMP5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DN64VFM5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DN64VFT5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DN64VLF5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DN64VLH5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DN64VMP5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DX128VFM5  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DX128VFT5  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DX128VLF5  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DX128VLH5  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DX32VFM5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DX32VFT5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DX32VLF5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DX32VLH5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DX32VMP5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DX64VFM5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DX64VFT5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DX64VLF5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DX64VLH5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MK20DX64VMP5   |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN128CAH12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN128VDC10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN128VLH10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN128VLL10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN128VMP10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN1M0AVLH12 |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN1M0AVLK12 |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN1M0AVLL12 |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN1M0AVLQ12 |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN1M0AVMC12 |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN1M0AVMD12 |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN1M0VLH12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN1M0VLK12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN1M0VLL12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN1M0VLQ12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN1M0VMC12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN1M0VMD12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN256CAH12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN256VDC12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN256VLH12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN256VLL12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN256VMP12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN512CAP12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN512VDC12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN512VFX12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN512VLH12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN512VLL12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FN512VMP12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FX512AVLH12 |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FX512AVLK12 |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FX512AVLL12 |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FX512AVLQ12 |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FX512AVMC12 |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FX512AVMD12 |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FX512VLH12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FX512VLK12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FX512VLL12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FX512VLQ12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FX512VMC12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK22FX512VMD12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK51DN256CLQ10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK51DN256CMD10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK51DN512CLL10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK51DN512CLQ10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK51DN512CMC10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK51DN512CMD10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK51DX256CLK10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK51DX256CLL10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK51DX256CMC10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK53DN512CLQ10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK53DN512CMD10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK53DX256CLQ10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK53DX256CMD10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK60DN256VLL10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK60DN256VLQ10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK60DN256VMC10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK60DN256VMD10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK60DN512VLL10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK60DN512VLQ10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK60DN512VMC10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK60DN512VMD10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK60DX256VLL10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK60DX256VLQ10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK60DX256VMC10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK60DX256VMD10  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK64FN1M0CAJ12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK64FN1M0VDC12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK64FN1M0VLL12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK64FN1M0VLQ12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK64FN1M0VMD12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK64FX512VDC12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK64FX512VLL12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK64FX512VLQ12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK64FX512VMD12  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK65FN2M0CAC18  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK65FN2M0VMI18  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK65FX1M0CAC18  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK65FX1M0VMI18  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK66FN2M0VLQ18  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK66FN2M0VMD18  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK66FX1M0VLQ18  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK66FX1M0VMD18  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK80FN256VDC15  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK80FN256VLL15  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK80FN256VLQ15  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK82FN256VDC15  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK82FN256VLL15  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MK82FN256VLQ15  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV42F128VLF16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV42F128VLH16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV42F128VLL16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV42F256VLH16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV42F256VLL16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MKV42F64VLF16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MKV42F64VLH16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV44F128VLF16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV44F128VLH16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV44F128VLL16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV44F256VLH16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV44F256VLL16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MKV44F64VLF16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  MKV44F64VLH16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV46F128VLH16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV46F128VLL16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV46F256VLH16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV46F256VLL16  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV56F1M0VLL24  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV56F1M0VLQ24  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV56F1M0VMD24  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV56F512VLL24  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV56F512VLQ24  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV56F512VMD24  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV58F1M0VLL24  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV58F1M0VLQ24  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV58F1M0VMD24  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV58F512VLL24  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV58F512VLQ24  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| MKV58F512VMD24  |     ARM      | `FLASH1`;`RAM1` |       `2.2.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
 
 ---
 
 ### PIC32
 
-|    CHIP NAME      |  ARCHITECTURE  |  REQUIREMENTS   |  SUPPORTED IN VERSION  |        GPIO        |         ADC        |         I2C        |         PWM        |         SPI        |         UART       |       ONE WIRE     |
-|:-----------------:|:--------------:|:---------------:|:----------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|
-| PIC32MX110F016B   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX110F016C   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX110F016D   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX120F032B   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX120F032C   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX120F032D   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX120F064H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX130F064B   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX130F064C   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX130F064D   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX130F128H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX130F128L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX130F256B   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX130F256D   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX150F128B   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX150F128C   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX150F128D   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX150F256H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX150F256L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX170F256B   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX170F256D   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX170F512H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX170F512L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX210F016B   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX210F016C   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX210F016D   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX220F032B   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX220F032C   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX220F032D   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX230F064B   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX230F064C   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX230F064D   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX230F128H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX230F128L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX230F256B   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX230F256D   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX250F128B   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX250F128C   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX250F128D   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX250F256H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX250F256L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX270F256B   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX270F256D   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX270F256DB  |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX270F512H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX270F512L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX320F032H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX320F064H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX320F128H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX320F128L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX330F064H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX330F064L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX340F128H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX340F128L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX340F256H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX340F512H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX350F128H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX350F128L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX350F256H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX350F256L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX360F256L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX360F512L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX370F512H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX370F512L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX420F032H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX430F064H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX430F064L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX440F128H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX440F128L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX440F256H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX440F512H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX450F128H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX450F128L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX450F256H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX450F256HB  |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX450F256L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX460F256L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX460F512L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX470F512H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX470F512L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX470F512LB  |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX530F128H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX530F128L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX534F064H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX534F064L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX550F256H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX550F256L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX564F064H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX564F064L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX564F128H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX564F128L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX570F512H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX570F512L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX575F256H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX575F256L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX575F512H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX575F512L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX664F064H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX664F064L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX664F128H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX664F128L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX675F256H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX675F256L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX675F512H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX675F512L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX695F512H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX695F512L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX764F128H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX764F128L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX775F256H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX775F256L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX775F512H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX775F512L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX795F512H   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MX795F512L   |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ0512EFE064 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ0512EFE100 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ0512EFE124 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ0512EFE144 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ0512EFF064 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ0512EFF100 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ0512EFF124 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ0512EFF144 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ0512EFK064 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ0512EFK100 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ0512EFK124 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ0512EFK144 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFE064 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFE100 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFE124 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFE144 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFF064 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFF100 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFF124 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFF144 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFG064 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFG100 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFG124 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFG144 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFH064 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFH100 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFH124 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFH144 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFK064 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFK100 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFK124 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFK144 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFM064 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFM100 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFM124 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ1024EFM144 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ2048EFG064 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ2048EFG100 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ2048EFG124 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ2048EFG144 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ2048EFH064 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ2048EFH100 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ2048EFH124 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ2048EFH144 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ2048EFM064 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ2048EFM100 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ2048EFM124 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC32MZ2048EFM144 |   PIC 32bit    | `FLASH1`;`RAM1` |        `2.1.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|     CHIP NAME     | ARCHITECTURE |  REQUIREMENTS   | SUPPORTED IN VERSION |        GPIO        |        ADC         |        I2C         |        PWM         |        SPI         |        UART        |      ONE WIRE      |
+| :---------------: | :----------: | :-------------: | :------------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: |
+|  PIC32MX110F016B  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX110F016C  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX110F016D  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX120F032B  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX120F032C  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX120F032D  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX120F064H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX130F064B  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX130F064C  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX130F064D  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX130F128H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX130F128L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX130F256B  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX130F256D  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX150F128B  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX150F128C  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX150F128D  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX150F256H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX150F256L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX170F256B  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX170F256D  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX170F512H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX170F512L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX210F016B  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX210F016C  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX210F016D  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX220F032B  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX220F032C  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX220F032D  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX230F064B  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX230F064C  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX230F064D  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX230F128H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX230F128L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX230F256B  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX230F256D  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX250F128B  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX250F128C  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX250F128D  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX250F256H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX250F256L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX270F256B  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX270F256D  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MX270F256DB  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX270F512H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX270F512L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX320F032H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX320F064H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX320F128H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX320F128L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX330F064H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX330F064L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX340F128H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX340F128L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX340F256H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX340F512H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX350F128H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX350F128L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX350F256H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX350F256L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX360F256L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX360F512L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX370F512H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX370F512L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX420F032H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX430F064H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX430F064L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX440F128H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX440F128L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX440F256H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX440F512H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX450F128H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX450F128L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX450F256H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MX450F256HB  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX450F256L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX460F256L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX460F512L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX470F512H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX470F512L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MX470F512LB  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX530F128H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX530F128L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX534F064H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX534F064L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX550F256H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX550F256L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX564F064H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX564F064L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX564F128H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX564F128L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX570F512H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX570F512L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX575F256H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX575F256L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX575F512H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX575F512L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX664F064H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX664F064L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX664F128H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX664F128L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX675F256H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX675F256L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX675F512H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX675F512L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX695F512H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX695F512L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX764F128H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX764F128L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX775F256H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX775F256L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX775F512H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX775F512L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX795F512H  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|  PIC32MX795F512L  |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ0512EFE064 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ0512EFE100 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ0512EFE124 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ0512EFE144 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ0512EFF064 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ0512EFF100 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ0512EFF124 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ0512EFF144 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ0512EFK064 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ0512EFK100 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ0512EFK124 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ0512EFK144 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFE064 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFE100 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFE124 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFE144 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFF064 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFF100 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFF124 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFF144 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFG064 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFG100 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFG124 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFG144 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFH064 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFH100 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFH124 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFH144 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFK064 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFK100 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFK124 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFK144 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFM064 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFM100 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFM124 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ1024EFM144 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ2048EFG064 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ2048EFG100 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ2048EFG124 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ2048EFG144 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ2048EFH064 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ2048EFH100 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ2048EFH124 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ2048EFH144 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ2048EFM064 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ2048EFM100 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ2048EFM124 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC32MZ2048EFM144 |  PIC 32bit   | `FLASH1`;`RAM1` |       `2.1.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
 
 [BACK TO TOP](#list-of-supported-chips)
 
@@ -442,269 +557,269 @@
 
 ### PIC18
 
-|    CHIP NAME      |  ARCHITECTURE  |  REQUIREMENTS   |  SUPPORTED IN VERSION  |        GPIO        |         ADC        |         I2C        |         PWM        |         SPI        |         UART       |       ONE WIRE     |
-|:-----------------:|:--------------:|:---------------:|:----------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|
-| PIC18F2455        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F2458        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F24J11       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F24J50       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F24K50       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F2515        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F2525        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F2550        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F2553        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F2585        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F25J11       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F25J50       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F25K40       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F25K42       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F25K50       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F25K80       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F2610        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F2620        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F2680        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F2682        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F2685        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F26J11       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F26J13       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F26J50       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F26J53       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F26K20       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F26K22       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F26K40       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F26K42       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F26K80       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F27J13       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F27J53       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F27K40       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F27K42       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F4455        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F4458        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F44J11       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F44J50       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F4515        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F4525        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F4550        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F4553        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F4585        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F45J11       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F45J50       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F45K22 [:one:](#note_1) |    PIC 8bit    | `FLASH1`        |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F45K40       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F45K42       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F45K50       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F45K80       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F4610        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F4620        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F4680        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F4682        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F4685        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F46J11       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F46J13       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F46J50       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F46J53       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F46K20       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F46K22       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F46K40       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F46K42       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F46K80       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F47J13       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F47J53       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F47K40       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F47K42       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F47Q10       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F55K42       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F56K42       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F57K42       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F57Q43       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F6520        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F6525        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F6527        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F6585        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F65J10       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F65J11       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F65J15       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F65J50       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F65J90       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F65J94       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F65K22       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F65K40       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F65K80       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F65K90       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F6620        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F6621        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F6622        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F6627        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F6628        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F6680        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F66J10       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F66J11       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F66J15       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F66J16       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F66J50       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F66J55       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F66J60       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F66J65       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F66J90       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F66J93       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F66J94       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F66K22       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F66K40       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F66K80       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F66K90       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F6720        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F6722        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F6723        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F67J10       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F67J11       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F67J50       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F67J60       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F67J90       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F67J93       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F67J94       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F67K22       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F67K40       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F67K90       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F8520        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F8525        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F8527        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F8585        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F85J10       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F85J11       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F85J15       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F85J50       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F85J90       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F85J94       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F85K22       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F85K90       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F8620        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F8621        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F8622        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F8627        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F8628        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F8680        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F86J10       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F86J11       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F86J15       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F86J16       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F86J50       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F86J55       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F86J60       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F86J65       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F86J72       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F86J90       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F86J93       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F86J94       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F86K22       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F86K90       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F8720        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F8722        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F8723        |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F87J10       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F87J11       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F87J50       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F87J60       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F87J72       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F87J90       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F87J93       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F87J94       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F87K22       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F87K90       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F95J94       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F96J60       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F96J65       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F96J94       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F97J60       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18F97J94       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF2455       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF2458       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF24J11      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF24J50      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF24K50      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF2515       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF2525       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF2550       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF2553       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF2585       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF25J11      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF25J50      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF25K40      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF25K42      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF25K50      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF25K80      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF2610       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF2620       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF2680       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF2682       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF2685       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF26J11      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF26J13      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF26J50      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF26J53      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF26K22      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF26K40      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF26K42      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF26K80      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF27J13      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF27J53      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF27K40      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF27K42      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF4455       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF4458       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF44J11      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF44J50      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF4515       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF4525       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF4550       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF4553       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF4585       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF45J11      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF45J50      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF45K22 [:one:](#note_1)|    PIC 8bit    | `FLASH1`        |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF45K40      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF45K42      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF45K50      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF45K80      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF4610       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF4620       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF4680       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF4682       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF4685       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF46J11      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF46J13      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF46J50      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF46J53      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF46K22      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF46K40      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF46K42      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF46K80      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF47J13      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF47J53      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF47K40      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF47K42      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF55K42      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF56K42      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF57K42      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF6520       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF6527       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF65K40      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF65K80      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF6622       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF6627       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF6628       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF66K40      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF66K80      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF6722       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF6723       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF67K40      |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF8520       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF8527       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF8622       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF8627       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF8628       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF8720       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF8722       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| PIC18LF8723       |    PIC 8bit    | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|           CHIP NAME           | ARCHITECTURE |  REQUIREMENTS   | SUPPORTED IN VERSION |        GPIO        |        ADC         |        I2C         |        PWM         |        SPI         |        UART        |      ONE WIRE      |
+| :---------------------------: | :----------: | :-------------: | :------------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: |
+|          PIC18F2455           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F2458           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F24J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F24J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F24K50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F2515           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F2525           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F2550           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F2553           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F2585           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F25J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F25J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F25K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F25K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F25K50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F25K80          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F2610           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F2620           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F2680           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F2682           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F2685           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F26J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F26J13          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F26J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F26J53          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F26K20          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F26K22          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F26K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F26K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F26K80          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F27J13          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F27J53          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F27K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F27K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F4455           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F4458           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F44J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F44J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F4515           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F4525           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F4550           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F4553           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F4585           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F45J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F45J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC18F45K22 [:one:](#note_1)  |   PIC 8bit   |    `FLASH1`     |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F45K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F45K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F45K50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F45K80          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F4610           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F4620           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F4680           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F4682           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F4685           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F46J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F46J13          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F46J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F46J53          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F46K20          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F46K22          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F46K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F46K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F46K80          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F47J13          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F47J53          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F47K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F47K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F47Q10          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F55K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F56K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F57K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F57Q43          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F6520           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F6525           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F6527           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F6585           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F65J10          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F65J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F65J15          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F65J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F65J90          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F65J94          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F65K22          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F65K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F65K80          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F65K90          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F6620           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F6621           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F6622           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F6627           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F6628           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F6680           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F66J10          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F66J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F66J15          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F66J16          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F66J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F66J55          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F66J60          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F66J65          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F66J90          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F66J93          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F66J94          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F66K22          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F66K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F66K80          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F66K90          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F6720           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F6722           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F6723           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F67J10          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F67J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F67J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F67J60          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F67J90          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F67J93          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F67J94          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F67K22          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F67K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F67K90          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F8520           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F8525           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F8527           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F8585           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F85J10          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F85J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F85J15          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F85J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F85J90          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F85J94          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F85K22          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F85K90          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F8620           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F8621           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F8622           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F8627           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F8628           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F8680           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F86J10          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F86J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F86J15          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F86J16          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F86J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F86J55          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F86J60          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F86J65          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F86J72          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F86J90          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F86J93          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F86J94          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F86K22          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F86K90          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F8720           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F8722           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F8723           |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F87J10          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F87J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F87J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F87J60          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F87J72          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F87J90          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F87J93          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F87J94          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F87K22          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F87K90          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F95J94          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F96J60          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F96J65          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F96J94          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F97J60          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18F97J94          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF2455          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF2458          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF24J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF24J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF24K50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF2515          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF2525          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF2550          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF2553          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF2585          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF25J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF25J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF25K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF25K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF25K50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF25K80          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF2610          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF2620          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF2680          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF2682          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF2685          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF26J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF26J13          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF26J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF26J53          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF26K22          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF26K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF26K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF26K80          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF27J13          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF27J53          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF27K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF27K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF4455          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF4458          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF44J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF44J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF4515          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF4525          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF4550          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF4553          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF4585          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF45J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF45J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| PIC18LF45K22 [:one:](#note_1) |   PIC 8bit   |    `FLASH1`     |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF45K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF45K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF45K50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF45K80          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF4610          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF4620          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF4680          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF4682          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF4685          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF46J11          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF46J13          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF46J50          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF46J53          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF46K22          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF46K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF46K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF46K80          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF47J13          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF47J53          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF47K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF47K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF55K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF56K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF57K42          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF6520          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF6527          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF65K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF65K80          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF6622          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF6627          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF6628          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF66K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF66K80          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF6722          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF6723          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|         PIC18LF67K40          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF8520          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF8527          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF8622          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF8627          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF8628          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF8720          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF8722          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|          PIC18LF8723          |   PIC 8bit   | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
 
 > **_NOTE:_**
 >> <a name="note_1">:one:</a> Chip doesn't have the minimum required amount of SRAM,
@@ -717,1265 +832,1265 @@
 
 ### STM32
 
-|    CHIP NAME      |  ARCHITECTURE  |  REQUIREMENTS   |  SUPPORTED IN VERSION  |        GPIO        |         ADC        |         I2C        |         PWM        |         SPI        |         UART       |       ONE WIRE     |
-|:-----------------:|:--------------:|:---------------:|:----------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|:------------------:|
-| STM32F030C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F030C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F030CCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F030F4Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F030K6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F030R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F030RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F031C4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F031C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F031E6Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F031F4Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F031F6Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F031G4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F031G6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F031K4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F031K6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F031K6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F038C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F038E6Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F038F6Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F038G6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F038K6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F042C4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F042C4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F042C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F042C6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F042F4Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F042F6Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F042G4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F042G6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F042K4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F042K4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F042K6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F042K6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F042T6Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F048C6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F048G6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F048T6Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F051C4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F051C4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F051C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F051C6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F051C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F051C8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F051K4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F051K4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F051K6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F051K6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F051K8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F051K8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F051R4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F051R6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F051R8Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F051R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F051T8Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F058C8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F058R8Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F058R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F058T8Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F070C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F070CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F070F6Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F070RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F071C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F071C8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F071CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F071CBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F071CBYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F071RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F071V8Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F071V8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F071VBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F071VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F072C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F072C8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F072CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F072CBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F072CBYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F072R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F072RBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F072RBIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F072RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F072V8Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F072V8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F072VBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F072VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F078CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F078CBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F078CBYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F078RBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F078RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F078VBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F078VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F091CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F091CBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F091CCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F091CCUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F091RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F091RCHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F091RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F091RCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F091VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F091VCHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F091VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F098CCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F098CCUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F098RCHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F098RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F098RCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F098VCHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F098VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100C4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100R4Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100R4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100R6Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100R6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100R8Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100RBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100RDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100V8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100VDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100ZCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100ZDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F100ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101C4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101C8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101CBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101R4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101R6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101RBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101RDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101RFTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101RGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101T4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101T6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101T8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101TBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101V8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101VDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101VFTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101ZCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101ZDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101ZFTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F101ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F102C4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F102C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F102C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F102CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F102R4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F102R6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F102R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F102RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103C4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103C6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103CBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103R4Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103R4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103R6Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103R6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103R8Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103RBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103RCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103RDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103RDYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103REYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103RFTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103RGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103T4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103T6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103T8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103TBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103V8Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103V8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103VBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103VBIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103VCHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103VDHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103VDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103VEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103VFTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103ZCHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103ZCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103ZDHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103ZDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103ZEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103ZFHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103ZFTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103ZGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F103ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F105R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F105RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F105RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F105V8Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F105V8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F105VBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F105VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F105VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F107RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F107RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F107VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F107VCHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F107VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F205RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F205RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F205RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F205REYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F205RFTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F205RGEx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F205RGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F205RGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F205VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F205VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F205VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F205VFTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F205VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F205ZCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F205ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F205ZFTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F205ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F207ICHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F207ICTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F207IEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F207IETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F207IFHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F207IFTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F207IGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F207IGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F207VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F207VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F207VFTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F207VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F207ZCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F207ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F207ZFTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F207ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F215RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F215RGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F215VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F215VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F215ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F215ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F217IEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F217IETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F217IGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F217IGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F217VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F217VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F217ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F217ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F301C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F301C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F301C8Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F301K6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F301K6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F301K8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F301K8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F301R6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F301R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302C8Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302CCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302K6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302K8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302R6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302RDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302VCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302VDHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302VDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302VEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302ZDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F302ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303C8Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303CCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303K6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303K6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303K8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303K8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303R6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303RDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303VCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303VDHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303VDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303VEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303VEYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303ZDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F303ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F318C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F318C8Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F318K8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F328C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F334C4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F334C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F334C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F334C8Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F334K4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F334K4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F334K6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F334K6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F334K8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F334K8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F334R6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F334R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F358CCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F358RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F358VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F373C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F373CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F373CCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F373R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F373RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F373RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F373V8Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F373V8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F373VBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F373VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F373VCHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F373VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F378CCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F378RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F378RCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F378VCHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F378VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F398VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401CBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401CBYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401CCFx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401CCUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401CCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401CDUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401CDYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401CEUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401CEYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401RDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401VBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401VCHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401VDHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401VDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401VEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F401VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F405OEYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F405OGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F405RGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F405VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F405ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F407IEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F407IETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F407IGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F407IGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F407VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F407VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F407ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F407ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F410C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F410C8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F410CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F410CBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F410R8Ix     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F410R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F410RBIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F410RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F410T8Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F410TBYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F411CCUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F411CCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F411CEUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F411CEYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F411RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F411RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F411VCHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F411VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F411VEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F411VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F412CEUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F412CGUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F412RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F412REYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F412REYxP    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F412RGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F412RGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F412RGYxP    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F412VEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F412VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F412VGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F412VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F412ZEJx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F412ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F412ZGJx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F412ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F413CGUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F413CHUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F413MGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F413MHYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F413RGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F413RHTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F413VGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F413VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F413VHHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F413VHTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F413ZGJx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F413ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F413ZHJx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F413ZHTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F415OGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F415RGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F415VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F415ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F417IEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F417IETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F417IGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F417IGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F417VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F417VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F417ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F417ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F423CHUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F423MHYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F423RHTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F423VHHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F423VHTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F423ZHJx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F423ZHTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F427AGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F427AIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F427IGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F427IGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F427IIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F427IITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F427VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F427VITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F427ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F427ZITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429AGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429AIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429BETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429BGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429BITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429IEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429IETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429IGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429IGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429IIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429IITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429NEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429NGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429NIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429VITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429ZGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429ZITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F429ZIYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F437AIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F437IGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F437IGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F437IIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F437IITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F437VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F437VITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F437ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F437ZITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F439AIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F439BGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F439BITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F439IGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F439IGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F439IIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F439IITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F439NGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F439NIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F439VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F439VITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F439ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F439ZGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F439ZITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F439ZIYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F446MCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F446MEYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F446RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F446RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F446VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F446VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F446ZCHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F446ZCJx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F446ZCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F446ZEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F446ZEJx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F446ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469AEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469AEYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469AGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469AGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469AIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469AIYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469BETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469BGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469BITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469IEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469IETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469IGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469IGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469IIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469IITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469NEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469NGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469NIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469VITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F469ZITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F479AGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F479AGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F479AIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F479AIYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F479BGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F479BITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F479IGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F479IGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F479IIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F479IITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F479NGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F479NIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F479VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F479VITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F479ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F479ZITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F722ICKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F722ICTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F722IEKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F722IETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F722RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F722RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F722VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F722VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F722ZCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F722ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F723ICKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F723ICTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F723IEKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F723IETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F723VCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F723VEYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F723ZCIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F723ZCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F723ZEIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F723ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F732IEKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F732IETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F732RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F732VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F732ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F733IEKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F733IETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F733VEYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F733ZEIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F733ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F745IEKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F745IETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F745IGKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F745IGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F745VEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F745VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F745VGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F745VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F745ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F745ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F746BETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F746BGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F746IEKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F746IETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F746IGKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F746IGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F746NEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F746NGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F746VEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F746VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F746VGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F746VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F746ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F746ZEYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F746ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F746ZGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F756BGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F756IGKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F756IGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F756NGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F756VGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F756VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F756ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F756ZGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F765BGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F765BITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F765IGKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F765IGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F765IIKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F765IITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F765NGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F765NIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F765VGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F765VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F765VIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F765VITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F765ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F765ZITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F767BGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F767BITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F767IGKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F767IGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F767IIKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F767IITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F767NGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F767NIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F767VGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F767VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F767VIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F767VITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F767ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F767ZITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F769AGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F769AIYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F769BGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F769BITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F769IGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F769IITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F769NGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F769NIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F777BITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F777IIKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F777IITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F777NIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F777VIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F777VITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F777ZITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F779AIYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F779BITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F779IITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32F779NIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G030C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G030C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G030F6Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G030J6Mx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G030K6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G030K8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031C4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031C4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031C6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031C8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031F4Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031F6Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031F8Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031G4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031G6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031G8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031J4Mx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031J6Mx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031K4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031K4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031K6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031K6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031K8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031K8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G031Y8Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G041C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G041C6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G041C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G041C8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G041F6Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G041F8Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G041G6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G041G8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G041J6Mx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G041K6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G041K6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G041K8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G041K8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G041Y8Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G070CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G070KBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G070RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071C6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071C8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071CBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071EBYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071G6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071G8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071G8UxN    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071GBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071GBUxN    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071K6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071K6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071K8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071K8TxN    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071K8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071K8UxN    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071KBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071KBTxN    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071KBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071KBUxN    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071R6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071RBIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G071RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G081CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G081CBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G081EBYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G081GBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G081GBUxN    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G081KBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G081KBTxN    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G081KBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G081KBUxN    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G081RBIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32G081RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H743AGIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H743AIIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H743BITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H743IIKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H743IITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H743VGHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H743VIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H743VITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H743XIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H743ZITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H750IBKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H750IBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H750VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H750XBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H753AIIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H753BITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H753IIKx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H753IITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H753VIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H753VITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H753XIHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32H753ZITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L011D3Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L011D4Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L011E3Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L011E4Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L011F3Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L011F3Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L011F4Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L011F4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L011G3Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L011G4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L011K3Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L011K3Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L011K4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L011K4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L021D4Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L021F4Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L021F4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L021G4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L021K4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L021K4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L031C4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L031C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L031C6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L031E4Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L031E6Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L031F4Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L031F6Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L031G4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L031G6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L031G6UxS    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L031K4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L031K4Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L031K6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L031K6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L041C4Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L041C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L041E6Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L041F6Px     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L041G6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L041G6UxS    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L041K6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L041K6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L051C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L051C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L051K6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L051K6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L051K8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L051K8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L051R6Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L051R6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L051R8Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L051R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L051T6Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L051T8Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L052C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L052C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L052K6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L052K6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L052K8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L052K8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L052R6Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L052R6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L052R8Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L052R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L052T6Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L052T8Fx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L052T8Yx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L053C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L053C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L053R6Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L053R6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L053R8Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L053R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L062K8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L062K8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L063C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L063R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071CBYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071CZTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071CZYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071K8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071KBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071KBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071KZTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071KZUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071RBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071RZHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071RZTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071V8Ix     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071V8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071VBIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071VZIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L071VZTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072CBYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072CZEx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072CZTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072CZYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072KBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072KBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072KZTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072KZUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072RBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072RBIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072RZHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072RZIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072RZTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072V8Ix     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072V8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072VBIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072VZIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L072VZTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L073CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L073CZTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L073RBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L073RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L073RZHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L073RZIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L073RZTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L073V8Ix     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L073V8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L073VBIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L073VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L073VZIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L073VZTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L081CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L081CZTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L081KZTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L081KZUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L082CZYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L082KBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L082KBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L082KZTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L082KZUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L083CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L083CZTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L083RBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L083RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L083RZHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L083RZTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L083V8Ix     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L083V8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L083VBIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L083VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L083VZIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L083VZTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L100C6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L100C6UxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L100R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L100R8TxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L100RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L100RBTxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L100RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151C6TxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151C6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151C6UxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151C8TxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151C8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151C8UxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151CBTxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151CBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151CBUxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151CCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151CCUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151QCHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151QDHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151QEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151R6Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151R6HxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151R6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151R6TxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151R8Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151R8HxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151R8TxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151RBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151RBHxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151RBTxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151RCTxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151RCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151RDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151RDYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151UCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151V8Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151V8HxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151V8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151V8TxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151VBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151VBHxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151VBTxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151VCHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151VCTxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151VDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151VDTxX    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151VDYxX    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151VEYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151ZCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151ZDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L151ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152C6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152C6TxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152C6Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152C6UxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152C8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152C8TxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152C8Ux     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152C8UxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152CBTxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152CBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152CBUxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152CCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152CCUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152QCHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152QDHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152QEHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152R6Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152R6HxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152R6Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152R6TxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152R8Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152R8HxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152R8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152R8TxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152RBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152RBHxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152RBTxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152RCTxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152RDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152RDYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152V8Hx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152V8HxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152V8Tx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152V8TxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152VBHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152VBHxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152VBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152VBTxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152VCHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152VCTxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152VDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152VDTxX    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152VEYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152ZCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152ZDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L152ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L162QDHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L162RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L162RCTxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L162RDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L162RDYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L162RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L162VCHx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L162VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L162VCTxA    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L162VDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L162VDYxX    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L162VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L162VEYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L162ZDTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L162ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L431CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L431CBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L431CBYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L431CCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L431CCUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L431CCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L431KBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L431KCUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L431RBIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L431RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L431RBYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L431RCIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L431RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L431RCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L431VCIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L431VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L432KBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L432KCUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L433CBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L433CBUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L433CBYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L433CCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L433CCUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L433CCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L433RBIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L433RBTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L433RBYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L433RCIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L433RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L433RCTxP    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L433RCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L433VCIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L433VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L442KCUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L443CCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L443CCUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L443CCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L443RCIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L443RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L443RCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L443VCIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L443VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L451CCUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L451CEUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L451RCIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L451RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L451RCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L451REIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L451RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L451REYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L451VCIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L451VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L451VEIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L451VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L452CCUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L452CEUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L452RCIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L452RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L452RCYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L452REIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L452RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L452RETxP    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L452REYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L452VCIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L452VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L452VEIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L452VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L462CEUx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L462REIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L462RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L462REYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L462VEIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L462VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L471QEIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L471QGIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L471RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L471RGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L471VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L471VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L471ZEJx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L471ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L471ZGJx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L471ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L475RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L475RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L475RGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L475VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L475VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L475VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L476JEYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L476JGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L476JGYxP    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L476MEYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L476MGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L476QEIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L476QGIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L476RCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L476RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L476RGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L476VCTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L476VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L476VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L476ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L476ZGJx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L476ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L476ZGTxP    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L486JGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L486QGIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L486RGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L486VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L486ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L496AEIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L496AGIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L496AGIxP    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L496QEIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L496QGIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L496QGIxP    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L496RETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L496RGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L496RGTxP    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L496VETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L496VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L496VGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L496VGYxP    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L496ZETx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L496ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L496ZGTxP    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4A6AGIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4A6AGIxP    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4A6QGIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4A6QGIxP    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4A6RGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4A6RGTxP    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4A6VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4A6VGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4A6VGYxP    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4A6ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4A6ZGTxP    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R5AGIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R5AIIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R5QGIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R5QIIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R5VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R5VITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R5ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R5ZGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R5ZITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R5ZITxP    |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R5ZIYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R7AIIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R7VITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R7ZITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R9AGIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R9AIIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R9VGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R9VITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R9ZGJx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R9ZGTx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R9ZGYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R9ZIJx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R9ZITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4R9ZIYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4S5AIIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4S5QIIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4S5VITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4S5ZITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4S5ZIYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4S7AIIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4S7VITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4S7ZITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4S9AIIx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4S9VITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4S9ZIJx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4S9ZITx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| STM32L4S9ZIYx     |      ARM       | `FLASH1`;`RAM1` |        `2.0.0+`        | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+|   CHIP NAME    | ARCHITECTURE |  REQUIREMENTS   | SUPPORTED IN VERSION |        GPIO        |        ADC         |        I2C         |        PWM         |        SPI         |        UART        |      ONE WIRE      |
+| :------------: | :----------: | :-------------: | :------------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: | :----------------: |
+| STM32F030C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F030C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F030CCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F030F4Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F030K6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F030R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F030RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F031C4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F031C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F031E6Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F031F4Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F031F6Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F031G4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F031G6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F031K4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F031K6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F031K6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F038C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F038E6Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F038F6Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F038G6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F038K6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F042C4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F042C4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F042C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F042C6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F042F4Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F042F6Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F042G4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F042G6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F042K4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F042K4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F042K6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F042K6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F042T6Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F048C6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F048G6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F048T6Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F051C4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F051C4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F051C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F051C6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F051C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F051C8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F051K4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F051K4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F051K6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F051K6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F051K8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F051K8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F051R4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F051R6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F051R8Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F051R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F051T8Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F058C8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F058R8Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F058R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F058T8Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F070C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F070CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F070F6Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F070RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F071C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F071C8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F071CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F071CBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F071CBYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F071RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F071V8Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F071V8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F071VBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F071VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F072C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F072C8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F072CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F072CBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F072CBYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F072R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F072RBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F072RBIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F072RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F072V8Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F072V8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F072VBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F072VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F078CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F078CBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F078CBYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F078RBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F078RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F078VBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F078VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F091CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F091CBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F091CCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F091CCUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F091RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F091RCHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F091RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F091RCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F091VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F091VCHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F091VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F098CCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F098CCUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F098RCHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F098RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F098RCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F098VCHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F098VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100C4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100R4Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100R4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100R6Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100R6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100R8Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100RBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100RDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100V8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100VDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100ZCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100ZDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F100ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101C4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101C8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101CBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101R4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101R6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101RBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101RDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101RFTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101RGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101T4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101T6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101T8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101TBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101V8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101VDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101VFTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101ZCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101ZDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101ZFTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F101ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F102C4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F102C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F102C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F102CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F102R4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F102R6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F102R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F102RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103C4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103C6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103CBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103R4Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103R4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103R6Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103R6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103R8Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103RBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103RCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103RDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103RDYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103REYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103RFTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103RGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103T4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103T6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103T8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103TBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103V8Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103V8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103VBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103VBIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103VCHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103VDHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103VDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103VEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103VFTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103ZCHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103ZCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103ZDHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103ZDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103ZEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103ZFHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103ZFTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103ZGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F103ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F105R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F105RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F105RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F105V8Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F105V8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F105VBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F105VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F105VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F107RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F107RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F107VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F107VCHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F107VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F205RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F205RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F205RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F205REYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F205RFTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F205RGEx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F205RGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F205RGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F205VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F205VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F205VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F205VFTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F205VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F205ZCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F205ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F205ZFTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F205ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F207ICHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F207ICTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F207IEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F207IETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F207IFHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F207IFTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F207IGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F207IGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F207VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F207VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F207VFTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F207VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F207ZCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F207ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F207ZFTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F207ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F215RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F215RGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F215VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F215VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F215ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F215ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F217IEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F217IETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F217IGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F217IGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F217VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F217VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F217ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F217ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F301C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F301C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F301C8Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F301K6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F301K6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F301K8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F301K8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F301R6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F301R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302C8Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302CCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302K6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302K8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302R6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302RDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302VCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302VDHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302VDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302VEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302ZDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F302ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303C8Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303CCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303K6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303K6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303K8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303K8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303R6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303RDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303VCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303VDHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303VDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303VEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303VEYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303ZDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F303ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F318C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F318C8Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F318K8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F328C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F334C4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F334C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F334C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F334C8Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F334K4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F334K4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F334K6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F334K6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F334K8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F334K8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F334R6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F334R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F358CCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F358RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F358VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F373C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F373CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F373CCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F373R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F373RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F373RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F373V8Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F373V8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F373VBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F373VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F373VCHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F373VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F378CCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F378RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F378RCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F378VCHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F378VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F398VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401CBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401CBYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401CCFx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401CCUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401CCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401CDUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401CDYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401CEUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401CEYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401RDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401VBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401VCHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401VDHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401VDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401VEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F401VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F405OEYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F405OGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F405RGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F405VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F405ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F407IEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F407IETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F407IGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F407IGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F407VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F407VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F407ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F407ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F410C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F410C8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F410CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F410CBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F410R8Ix  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F410R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F410RBIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F410RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F410T8Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F410TBYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F411CCUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F411CCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F411CEUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F411CEYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F411RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F411RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F411VCHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F411VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F411VEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F411VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F412CEUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F412CGUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F412RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F412REYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F412REYxP |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F412RGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F412RGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F412RGYxP |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F412VEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F412VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F412VGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F412VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F412ZEJx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F412ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F412ZGJx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F412ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F413CGUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F413CHUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F413MGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F413MHYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F413RGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F413RHTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F413VGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F413VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F413VHHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F413VHTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F413ZGJx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F413ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F413ZHJx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F413ZHTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F415OGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F415RGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F415VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F415ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F417IEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F417IETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F417IGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F417IGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F417VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F417VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F417ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F417ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F423CHUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F423MHYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F423RHTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F423VHHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F423VHTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F423ZHJx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F423ZHTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F427AGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F427AIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F427IGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F427IGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F427IIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F427IITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F427VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F427VITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F427ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F427ZITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429AGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429AIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429BETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429BGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429BITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429IEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429IETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429IGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429IGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429IIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429IITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429NEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429NGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429NIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429VITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429ZGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429ZITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F429ZIYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F437AIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F437IGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F437IGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F437IIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F437IITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F437VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F437VITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F437ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F437ZITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F439AIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F439BGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F439BITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F439IGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F439IGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F439IIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F439IITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F439NGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F439NIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F439VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F439VITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F439ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F439ZGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F439ZITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F439ZIYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F446MCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F446MEYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F446RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F446RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F446VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F446VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F446ZCHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F446ZCJx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F446ZCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F446ZEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F446ZEJx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F446ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469AEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469AEYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469AGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469AGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469AIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469AIYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469BETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469BGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469BITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469IEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469IETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469IGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469IGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469IIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469IITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469NEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469NGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469NIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469VITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F469ZITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F479AGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F479AGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F479AIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F479AIYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F479BGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F479BITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F479IGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F479IGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F479IIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F479IITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F479NGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F479NIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F479VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F479VITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F479ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F479ZITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F722ICKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F722ICTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F722IEKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F722IETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F722RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F722RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F722VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F722VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F722ZCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F722ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F723ICKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F723ICTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F723IEKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F723IETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F723VCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F723VEYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F723ZCIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F723ZCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F723ZEIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F723ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F732IEKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F732IETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F732RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F732VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F732ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F733IEKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F733IETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F733VEYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F733ZEIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F733ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F745IEKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F745IETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F745IGKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F745IGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F745VEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F745VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F745VGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F745VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F745ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F745ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F746BETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F746BGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F746IEKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F746IETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F746IGKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F746IGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F746NEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F746NGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F746VEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F746VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F746VGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F746VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F746ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F746ZEYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F746ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F746ZGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F756BGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F756IGKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F756IGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F756NGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F756VGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F756VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F756ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F756ZGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F765BGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F765BITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F765IGKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F765IGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F765IIKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F765IITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F765NGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F765NIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F765VGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F765VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F765VIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F765VITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F765ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F765ZITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F767BGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F767BITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F767IGKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F767IGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F767IIKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F767IITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F767NGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F767NIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F767VGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F767VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F767VIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F767VITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F767ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F767ZITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F769AGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F769AIYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F769BGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F769BITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F769IGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F769IITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F769NGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F769NIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F777BITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F777IIKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F777IITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F777NIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F777VIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F777VITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F777ZITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F779AIYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F779BITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F779IITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32F779NIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G030C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G030C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G030F6Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G030J6Mx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G030K6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G030K8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031C4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031C4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031C6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031C8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031F4Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031F6Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031F8Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031G4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031G6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031G8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031J4Mx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031J6Mx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031K4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031K4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031K6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031K6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031K8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031K8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G031Y8Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G041C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G041C6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G041C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G041C8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G041F6Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G041F8Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G041G6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G041G8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G041J6Mx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G041K6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G041K6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G041K8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G041K8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G041Y8Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G070CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G070KBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G070RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071C6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071C8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071CBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071EBYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071G6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071G8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071G8UxN |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071GBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071GBUxN |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071K6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071K6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071K8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071K8TxN |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071K8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071K8UxN |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071KBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071KBTxN |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071KBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071KBUxN |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071R6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071RBIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G071RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G081CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G081CBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G081EBYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G081GBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G081GBUxN |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G081KBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G081KBTxN |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G081KBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G081KBUxN |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G081RBIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32G081RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H743AGIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H743AIIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H743BITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H743IIKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H743IITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H743VGHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H743VIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H743VITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H743XIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H743ZITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H750IBKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H750IBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H750VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H750XBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H753AIIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H753BITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H753IIKx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H753IITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H753VIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H753VITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H753XIHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32H753ZITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L011D3Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L011D4Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L011E3Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L011E4Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L011F3Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L011F3Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L011F4Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L011F4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L011G3Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L011G4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L011K3Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L011K3Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L011K4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L011K4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L021D4Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L021F4Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L021F4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L021G4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L021K4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L021K4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L031C4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L031C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L031C6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L031E4Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L031E6Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L031F4Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L031F6Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L031G4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L031G6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L031G6UxS |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L031K4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L031K4Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L031K6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L031K6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L041C4Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L041C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L041E6Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L041F6Px  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L041G6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L041G6UxS |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L041K6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L041K6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L051C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L051C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L051K6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L051K6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L051K8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L051K8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L051R6Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L051R6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L051R8Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L051R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L051T6Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L051T8Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L052C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L052C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L052K6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L052K6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L052K8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L052K8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L052R6Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L052R6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L052R8Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L052R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L052T6Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L052T8Fx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L052T8Yx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L053C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L053C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L053R6Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L053R6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L053R8Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L053R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L062K8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L062K8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L063C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L063R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071CBYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071CZTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071CZYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071K8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071KBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071KBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071KZTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071KZUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071RBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071RZHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071RZTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071V8Ix  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071V8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071VBIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071VZIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L071VZTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072CBYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072CZEx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072CZTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072CZYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072KBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072KBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072KZTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072KZUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072RBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072RBIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072RZHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072RZIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072RZTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072V8Ix  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072V8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072VBIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072VZIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L072VZTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L073CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L073CZTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L073RBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L073RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L073RZHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L073RZIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L073RZTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L073V8Ix  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L073V8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L073VBIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L073VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L073VZIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L073VZTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L081CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L081CZTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L081KZTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L081KZUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L082CZYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L082KBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L082KBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L082KZTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L082KZUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L083CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L083CZTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L083RBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L083RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L083RZHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L083RZTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L083V8Ix  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L083V8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L083VBIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L083VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L083VZIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L083VZTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L100C6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L100C6UxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L100R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L100R8TxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L100RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L100RBTxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L100RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151C6TxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151C6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151C6UxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151C8TxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151C8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151C8UxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151CBTxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151CBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151CBUxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151CCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151CCUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151QCHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151QDHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151QEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151R6Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151R6HxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151R6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151R6TxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151R8Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151R8HxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151R8TxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151RBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151RBHxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151RBTxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151RCTxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151RCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151RDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151RDYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151UCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151V8Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151V8HxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151V8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151V8TxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151VBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151VBHxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151VBTxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151VCHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151VCTxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151VDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151VDTxX |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151VDYxX |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151VEYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151ZCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151ZDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L151ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152C6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152C6TxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152C6Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152C6UxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152C8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152C8TxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152C8Ux  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152C8UxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152CBTxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152CBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152CBUxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152CCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152CCUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152QCHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152QDHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152QEHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152R6Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152R6HxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152R6Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152R6TxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152R8Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152R8HxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152R8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152R8TxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152RBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152RBHxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152RBTxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152RCTxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152RDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152RDYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152V8Hx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152V8HxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152V8Tx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152V8TxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152VBHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152VBHxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152VBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152VBTxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152VCHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152VCTxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152VDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152VDTxX |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152VEYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152ZCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152ZDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L152ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L162QDHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L162RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L162RCTxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L162RDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L162RDYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L162RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L162VCHx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L162VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L162VCTxA |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L162VDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L162VDYxX |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L162VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L162VEYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L162ZDTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L162ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L431CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L431CBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L431CBYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L431CCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L431CCUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L431CCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L431KBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L431KCUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L431RBIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L431RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L431RBYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L431RCIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L431RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L431RCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L431VCIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L431VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L432KBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L432KCUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L433CBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L433CBUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L433CBYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L433CCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L433CCUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L433CCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L433RBIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L433RBTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L433RBYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L433RCIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L433RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L433RCTxP |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L433RCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L433VCIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L433VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L442KCUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L443CCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L443CCUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L443CCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L443RCIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L443RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L443RCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L443VCIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L443VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L451CCUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L451CEUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L451RCIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L451RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L451RCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L451REIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L451RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L451REYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L451VCIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L451VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L451VEIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L451VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L452CCUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L452CEUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L452RCIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L452RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L452RCYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L452REIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L452RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L452RETxP |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L452REYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L452VCIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L452VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L452VEIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L452VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L462CEUx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L462REIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L462RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L462REYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L462VEIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L462VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L471QEIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L471QGIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L471RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L471RGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L471VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L471VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L471ZEJx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L471ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L471ZGJx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L471ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L475RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L475RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L475RGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L475VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L475VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L475VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L476JEYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L476JGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L476JGYxP |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L476MEYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L476MGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L476QEIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L476QGIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L476RCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L476RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L476RGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L476VCTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L476VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L476VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L476ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L476ZGJx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L476ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L476ZGTxP |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L486JGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L486QGIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L486RGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L486VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L486ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L496AEIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L496AGIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L496AGIxP |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L496QEIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L496QGIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L496QGIxP |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L496RETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L496RGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L496RGTxP |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L496VETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L496VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L496VGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L496VGYxP |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L496ZETx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L496ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L496ZGTxP |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4A6AGIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4A6AGIxP |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4A6QGIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4A6QGIxP |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4A6RGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4A6RGTxP |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4A6VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4A6VGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4A6VGYxP |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4A6ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4A6ZGTxP |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R5AGIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R5AIIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R5QGIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R5QIIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R5VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R5VITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R5ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R5ZGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R5ZITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R5ZITxP |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R5ZIYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R7AIIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R7VITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R7ZITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R9AGIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R9AIIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R9VGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R9VITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R9ZGJx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R9ZGTx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R9ZGYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R9ZIJx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R9ZITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4R9ZIYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4S5AIIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4S5QIIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4S5VITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4S5ZITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4S5ZIYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4S7AIIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4S7VITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4S7ZITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4S9AIIx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4S9VITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4S9ZIJx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4S9ZITx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| STM32L4S9ZIYx  |     ARM      | `FLASH1`;`RAM1` |       `2.0.0+`       | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
 
 [BACK TO TOP](#list-of-supported-chips)
 
diff --git a/api/gl/lib/src/gl_shapes.c b/api/gl/lib/src/gl_shapes.c
index cf048b23a..b8c23e4e8 100644
--- a/api/gl/lib/src/gl_shapes.c
+++ b/api/gl/lib/src/gl_shapes.c
@@ -40,6 +40,7 @@
 #include "gl_shapes.h"
 #include "gl_utils.h"
 #include <math.h>
+#include <stdint.h>
 #include <stdlib.h>
 #include <stddef.h>
 #include <stdbool.h>
@@ -683,6 +684,22 @@ static void _draw_slice_crop(gl_arc_t* arc, gl_rectangle_t* border_rect)
     tg_angle_start = tan(arc->start_angle * storage);
     tg_angle_end = tan(arc->end_angle * storage);
 
+    // whatsnew: IR fix for issue of bad conversion for special case 
+    // added check if result is +Inf, or -Inf
+    // since cast to integer is undefined 
+    // added max and min int instead 
+    if (tg_angle_start > INT32_MAX) {
+        tg_angle_start = INT32_MAX;
+    } else if (tg_angle_start < INT32_MIN) {
+      tg_angle_start = INT32_MIN;
+    }
+
+    if (tg_angle_end > INT32_MAX) {
+        tg_angle_end = INT32_MAX;
+    } else if (tg_angle_end < INT32_MIN) {
+        tg_angle_end = INT32_MIN;
+    }
+
     // finding pint A
     storage = sqrt(1.0 + tg_angle_start * tg_angle_start);
     x_ring_left = arc->radius / storage;
@@ -696,8 +713,11 @@ static void _draw_slice_crop(gl_arc_t* arc, gl_rectangle_t* border_rect)
     if (90 < arc->start_angle && arc->start_angle<= 270)
     {
         x_left *= -1;
-        y_left *= -1;
-        y_ring_left *= -1;
+        // whatsnew: IR fix for issue no need to negate it if already is negative
+        if(y_left > 0) {
+            y_left *= -1;
+            y_ring_left *= -1;
+        }
         x_ring_left *= -1;
     }
 
@@ -720,8 +740,11 @@ static void _draw_slice_crop(gl_arc_t* arc, gl_rectangle_t* border_rect)
     if (90 < arc->end_angle && arc->end_angle<= 270)
     {
         x_right *= -1;
-        y_right *= -1;
-        y_ring_right *= -1;
+        // whatsnew: IR fix for issue no need to negate it if already is negative
+        if(y_right > 0) {
+            y_right *= -1;
+            y_ring_right *= -1;
+        }
         x_ring_right *= -1;
     }
 
diff --git a/api/vtft/lib_vtft/src/vtft_touch.c b/api/vtft/lib_vtft/src/vtft_touch.c
index 509450f83..e2628b474 100644
--- a/api/vtft/lib_vtft/src/vtft_touch.c
+++ b/api/vtft/lib_vtft/src/vtft_touch.c
@@ -44,14 +44,33 @@
 // Currently used VTFT instance. Needed for TP callbacks.
 static vtft_t *_current_instance = 0;
 
+/**
+ * @attention @b https://github.com/MikroElektronika/mikrosdk_v2/issues/4
+ * @note @ref _get_active_component API fails to return adequate handler
+ *       for @b PIC18F57Q43 MCU specifically.
+ *       Workaround applied by creating a global variable which is further
+ *       used in the API itself.
+ *       The issue will be resolved in on of the following updates.
+ */
+#if defined(__MIKROC_AI_FOR_PIC__) && defined(PIC18F57Q43)
+static vtft_screen* active_screen;
+#endif
+
 // Local Function Definitions
 
 // Returns the frontmost active component at the given coordinates.
 static vtft_active_component * __generic_ptr _get_active_component(vtft_t * instance, vtft_coord_t x, vtft_coord_t y)
 {
     int32_t i;
+    // TODO - when fixed, revert to previous state.
+    #if defined(__MIKROC_AI_FOR_PIC__) && defined(PIC18F57Q43)
+    active_screen = instance->current_screen;
+    vtft_component * __generic_ptr * __generic_ptr components = active_screen->components;
+    volatile vtft_index_t component_count = active_screen->component_count;
+    #else
     vtft_component * __generic_ptr * __generic_ptr components = instance->current_screen->components;
     vtft_index_t component_count = instance->current_screen->component_count;
+    #endif
 
     for (i = component_count - 1; i >= 0; i--)
     {
@@ -313,4 +332,3 @@ void _tp_event_handler( tp_event_t event, tp_coord_t x, tp_coord_t y, tp_touch_i
         break;
     }
 }
-
diff --git a/bsp/board/CMakeLists.txt b/bsp/board/CMakeLists.txt
index 644b4f60f..22b85e377 100644
--- a/bsp/board/CMakeLists.txt
+++ b/bsp/board/CMakeLists.txt
@@ -95,6 +95,16 @@ if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_QUAIL")
     set(MCU_CARD  FALSE)
 endif()
 
+if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_EASYAVR_PRO_V8")
+    set(BOARD_PATH   "board_easyavr_pro_v8")
+endif()
+
+if(${_MSDK_BOARD_NAME_} STREQUAL "BOARD_EASYAVR_V7")
+    set(BOARD_PATH   "board_easyavr_v7")
+    set(MCU_CARD  FALSE)
+    set(DIP_SOCKET  TRUE)
+endif()
+
 ## CLICKER BOARDS
 if(${_MSDK_BOARD_NAME_} STREQUAL "STM32_M4_CLICKER")
     set(BOARD_PATH   "clicker_stm32_m4")
@@ -424,8 +434,22 @@ if (MCU_CARD)
         list(APPEND INCLUDE_HEADERS_PATH_LIST include/mcu_cards/${MCU_CARD_PATH})
 endif()
 if(DIP_SOCKET)
-        list(APPEND HEADERS_LIST include/boards/${BOARD_PATH}/dip_sockets/${BOARD_DIP_SOCKET_PATH}/dip_socket.h)
+        # TODO
+        # Add appropriate dip_socket header files per MCU.
+        # At the moment all non AVR MCUs take one socket header file.
+        # e.g. if DIP40 socket on the board has both A and B sockets, socket B will be taken by default.
         list(APPEND INCLUDE_HEADERS_PATH_LIST include/boards/${BOARD_PATH}/dip_sockets/${BOARD_DIP_SOCKET_PATH})
+        if ( (${MSDK_FILTERED_DIP_SOCKET_TYPE} MATCHES "^dip[24]0$") AND (${_MSDK_BOARD_NAME_} STREQUAL "BOARD_EASYAVR_V7") )
+            list(APPEND INCLUDE_HEADERS_PATH_LIST include/boards/${BOARD_PATH}/dip_sockets)
+            if (${MSDK_FILTERED_DIP_SOCKET_TYPE} STREQUAL "dip20")
+                list(APPEND HEADERS_LIST include/boards/${BOARD_PATH}/dip_sockets/dip20b/dip_socket.h)
+            endif()
+            if (${MSDK_FILTERED_DIP_SOCKET_TYPE} STREQUAL "dip40")
+                list(APPEND HEADERS_LIST include/boards/${BOARD_PATH}/dip_sockets/dip40b/dip_socket.h)
+            endif()
+        else()
+            list(APPEND HEADERS_LIST include/boards/${BOARD_PATH}/dip_sockets/${BOARD_DIP_SOCKET_PATH}/dip_socket.h)
+        endif()
 endif()
 
 if (SHIELD)
diff --git a/bsp/board/include/boards/board_easyavr_pro_v8/board.h b/bsp/board/include/boards/board_easyavr_pro_v8/board.h
new file mode 100644
index 000000000..bf872de27
--- /dev/null
+++ b/bsp/board/include/boards/board_easyavr_pro_v8/board.h
@@ -0,0 +1,182 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  board.h
+ * @brief Main board pin mapping.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+// Hardware revision number
+#define BOARD_REV_MAJOR (1)
+#define BOARD_REV_MINOR (00)
+
+#define BOARD_NAME "EasyAVR PRO v8"
+
+#include "mcu_card.h"
+#include "mikrobus.h"
+
+/// Mapping
+#define MIKROBUS_1 1
+#define MIKROBUS_1_AN LEFT_CN_PIN_144
+#define MIKROBUS_1_RST LEFT_CN_PIN_143
+#define MIKROBUS_1_CS LEFT_CN_PIN_142
+#define MIKROBUS_1_SCK LEFT_CN_PIN_141
+#define MIKROBUS_1_MISO LEFT_CN_PIN_140
+#define MIKROBUS_1_MOSI LEFT_CN_PIN_139
+#define MIKROBUS_1_PWM LEFT_CN_PIN_138
+#define MIKROBUS_1_RX LEFT_CN_PIN_136
+#define MIKROBUS_1_INT LEFT_CN_PIN_137
+#define MIKROBUS_1_TX LEFT_CN_PIN_135
+#define MIKROBUS_1_SCL LEFT_CN_PIN_134
+#define MIKROBUS_1_SDA LEFT_CN_PIN_133
+
+#define MIKROBUS_2 2
+#define MIKROBUS_2_AN LEFT_CN_PIN_132
+#define MIKROBUS_2_RST LEFT_CN_PIN_131
+#define MIKROBUS_2_CS LEFT_CN_PIN_130
+#define MIKROBUS_2_SCK LEFT_CN_PIN_129
+#define MIKROBUS_2_MISO LEFT_CN_PIN_128
+#define MIKROBUS_2_MOSI LEFT_CN_PIN_127
+#define MIKROBUS_2_PWM LEFT_CN_PIN_126
+#define MIKROBUS_2_RX LEFT_CN_PIN_124
+#define MIKROBUS_2_INT LEFT_CN_PIN_125
+#define MIKROBUS_2_TX LEFT_CN_PIN_123
+#define MIKROBUS_2_SCL LEFT_CN_PIN_122
+#define MIKROBUS_2_SDA LEFT_CN_PIN_121
+
+#define MIKROBUS_3 3
+#define MIKROBUS_3_AN LEFT_CN_PIN_120
+#define MIKROBUS_3_RST LEFT_CN_PIN_119
+#define MIKROBUS_3_CS LEFT_CN_PIN_118
+#define MIKROBUS_3_SCK LEFT_CN_PIN_117
+#define MIKROBUS_3_MISO LEFT_CN_PIN_116
+#define MIKROBUS_3_MOSI LEFT_CN_PIN_115
+#define MIKROBUS_3_PWM LEFT_CN_PIN_114
+#define MIKROBUS_3_RX LEFT_CN_PIN_112
+#define MIKROBUS_3_INT LEFT_CN_PIN_113
+#define MIKROBUS_3_TX LEFT_CN_PIN_111
+#define MIKROBUS_3_SCL LEFT_CN_PIN_110
+#define MIKROBUS_3_SDA LEFT_CN_PIN_109
+
+#define MIKROBUS_4 4
+#define MIKROBUS_4_AN LEFT_CN_PIN_108
+#define MIKROBUS_4_RST LEFT_CN_PIN_107
+#define MIKROBUS_4_CS LEFT_CN_PIN_106
+#define MIKROBUS_4_SCK LEFT_CN_PIN_105
+#define MIKROBUS_4_MISO LEFT_CN_PIN_104
+#define MIKROBUS_4_MOSI LEFT_CN_PIN_103
+#define MIKROBUS_4_PWM LEFT_CN_PIN_102
+#define MIKROBUS_4_RX LEFT_CN_PIN_100
+#define MIKROBUS_4_INT LEFT_CN_PIN_101
+#define MIKROBUS_4_TX LEFT_CN_PIN_099
+#define MIKROBUS_4_SCL LEFT_CN_PIN_098
+#define MIKROBUS_4_SDA LEFT_CN_PIN_097
+
+#define MIKROBUS_5 5
+#define MIKROBUS_5_AN LEFT_CN_PIN_096
+#define MIKROBUS_5_RST LEFT_CN_PIN_095
+#define MIKROBUS_5_CS LEFT_CN_PIN_094
+#define MIKROBUS_5_SCK LEFT_CN_PIN_093
+#define MIKROBUS_5_MISO LEFT_CN_PIN_092
+#define MIKROBUS_5_MOSI LEFT_CN_PIN_091
+#define MIKROBUS_5_PWM LEFT_CN_PIN_090
+#define MIKROBUS_5_RX LEFT_CN_PIN_088
+#define MIKROBUS_5_INT LEFT_CN_PIN_089
+#define MIKROBUS_5_TX LEFT_CN_PIN_087
+#define MIKROBUS_5_SCL LEFT_CN_PIN_086
+#define MIKROBUS_5_SDA LEFT_CN_PIN_085
+
+#define USB_UART_TX RIGHT_CN_PIN_160
+#define USB_UART_RX RIGHT_CN_PIN_159
+
+#define TFT_RST LEFT_CN_PIN_025
+#define TFT_CS LEFT_CN_PIN_026
+#define TFT_D_C LEFT_CN_PIN_027
+#define TFT_RD LEFT_CN_PIN_028
+#define TFT_WR LEFT_CN_PIN_029
+#define TFT_TE LEFT_CN_PIN_055
+#define TFT_GPIO LEFT_CN_PIN_054
+#define TFT_BPWM LEFT_CN_PIN_057
+#define TFT_D0 LEFT_CN_PIN_030
+#define TFT_D1 LEFT_CN_PIN_031
+#define TFT_D2 LEFT_CN_PIN_032
+#define TFT_D3 LEFT_CN_PIN_033
+#define TFT_D4 LEFT_CN_PIN_034
+#define TFT_D5 LEFT_CN_PIN_035
+#define TFT_D6 LEFT_CN_PIN_036
+#define TFT_D7 LEFT_CN_PIN_037
+#define TFT_D8 LEFT_CN_PIN_038
+#define TFT_D9 LEFT_CN_PIN_039
+#define TFT_D10 LEFT_CN_PIN_040
+#define TFT_D11 LEFT_CN_PIN_041
+#define TFT_D12 LEFT_CN_PIN_042
+#define TFT_D13 LEFT_CN_PIN_043
+#define TFT_D14 LEFT_CN_PIN_044
+#define TFT_D15 LEFT_CN_PIN_045
+
+#define CTP_SDA LEFT_CN_PIN_059
+#define CTP_SCL LEFT_CN_PIN_058
+#define CTP_WAKE LEFT_CN_PIN_061
+#define CTP_INT LEFT_CN_PIN_060
+#define CTP_RST LEFT_CN_PIN_062
+
+#define USB_UART_TX RIGHT_CN_PIN_160
+#define USB_UART_RX RIGHT_CN_PIN_159
+
+#define TFT_8BIT_DATA_PORT_CH0 LCD_TFT_8BIT_CH0
+#define TFT_8BIT_DATA_PORT_CH0_MASK LCD_TFT_CH0_8BIT_MASK
+
+#define TFT_16BIT_DATA_PORT_CH0 LCD_TFT_16BIT_CH0
+#define TFT_16BIT_DATA_PORT_CH0_MASK LCD_TFT_16BIT_CH0_MASK
+
+#define TFT_16BIT_DATA_PORT_CH1 LCD_TFT_16BIT_CH1
+#define TFT_16BIT_DATA_PORT_CH1_MASK LCD_TFT_16BIT_CH1_MASK
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _BOARD_H_
+// ------------------------------------------------------------------------- END
diff --git a/bsp/board/include/boards/board_easyavr_v7/board.h b/bsp/board/include/boards/board_easyavr_v7/board.h
new file mode 100644
index 000000000..0e1c623de
--- /dev/null
+++ b/bsp/board/include/boards/board_easyavr_v7/board.h
@@ -0,0 +1,111 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  board.h
+ * @brief Main board pin mapping.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+// Hardware revision number
+#define BOARD_REV_MAJOR (1)
+#define BOARD_REV_MINOR (01)
+
+#define BOARD_NAME "EasyAVR v7"
+
+#include "dip_socket.h"
+#include "mikrobus.h"
+
+/// Mapping
+#define MIKROBUS_1      1
+#define MIKROBUS_1_AN   MIKROBUS_1_DIP_AN
+#define MIKROBUS_1_RST  MIKROBUS_1_DIP_RST
+#define MIKROBUS_1_CS   MIKROBUS_1_DIP_CS
+#define MIKROBUS_1_SCK  MIKROBUS_1_DIP_SCK
+#define MIKROBUS_1_MISO MIKROBUS_1_DIP_MISO
+#define MIKROBUS_1_MOSI MIKROBUS_1_DIP_MOSI
+#define MIKROBUS_1_PWM  MIKROBUS_1_DIP_PWM
+#define MIKROBUS_1_INT  MIKROBUS_1_DIP_INT
+#define MIKROBUS_1_RX   MIKROBUS_1_DIP_RX
+#define MIKROBUS_1_TX   MIKROBUS_1_DIP_TX
+#define MIKROBUS_1_SCL  MIKROBUS_1_DIP_SCL
+#define MIKROBUS_1_SDA  MIKROBUS_1_DIP_SDA
+
+#define MIKROBUS_2      2
+#define MIKROBUS_2_AN   MIKROBUS_2_DIP_AN
+#define MIKROBUS_2_RST  MIKROBUS_2_DIP_RST
+#define MIKROBUS_2_CS   MIKROBUS_2_DIP_CS
+#define MIKROBUS_2_SCK  MIKROBUS_2_DIP_SCK
+#define MIKROBUS_2_MISO MIKROBUS_2_DIP_MISO
+#define MIKROBUS_2_MOSI MIKROBUS_2_DIP_MOSI
+#define MIKROBUS_2_PWM  MIKROBUS_2_DIP_PWM
+#define MIKROBUS_2_INT  MIKROBUS_2_DIP_INT
+#define MIKROBUS_2_RX   MIKROBUS_2_DIP_RX
+#define MIKROBUS_2_TX   MIKROBUS_2_DIP_TX
+#define MIKROBUS_2_SCL  MIKROBUS_2_DIP_SCL
+#define MIKROBUS_2_SDA  MIKROBUS_2_DIP_SDA
+
+#define MIKROBUS_3      3
+#define MIKROBUS_3_AN   MIKROBUS_3_DIP_AN
+#define MIKROBUS_3_RST  MIKROBUS_3_DIP_RST
+#define MIKROBUS_3_CS   MIKROBUS_3_DIP_CS
+#define MIKROBUS_3_SCK  MIKROBUS_3_DIP_SCK
+#define MIKROBUS_3_MISO MIKROBUS_3_DIP_MISO
+#define MIKROBUS_3_MOSI MIKROBUS_3_DIP_MOSI
+#define MIKROBUS_3_PWM  MIKROBUS_3_DIP_PWM
+#define MIKROBUS_3_INT  MIKROBUS_3_DIP_INT
+#define MIKROBUS_3_RX   MIKROBUS_3_DIP_RX
+#define MIKROBUS_3_TX   MIKROBUS_3_DIP_TX
+#define MIKROBUS_3_SCL  MIKROBUS_3_DIP_SCL
+#define MIKROBUS_3_SDA  MIKROBUS_3_DIP_SDA
+
+#define USB_UART_TX     USB_UART_DIP_TX
+#define USB_UART_RX     USB_UART_DIP_RX
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _BOARD_H_
+// ------------------------------------------------------------------------- END
diff --git a/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip14/dip_socket.h b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip14/dip_socket.h
new file mode 100644
index 000000000..76412fc16
--- /dev/null
+++ b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip14/dip_socket.h
@@ -0,0 +1,101 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  dip_socket.h
+ * @brief Dip socket mikrobus pin mapping.
+ */
+
+#ifndef _DIP_SOCKET_H_
+#define _DIP_SOCKET_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_target.h"
+
+/// Mapping
+#define MIKROBUS_1_DIP_AN   PA7
+#define MIKROBUS_1_DIP_RST  PA6
+#define MIKROBUS_1_DIP_CS   PA5
+#define MIKROBUS_1_DIP_SCK  PA4
+#define MIKROBUS_1_DIP_MISO PA5
+#define MIKROBUS_1_DIP_MOSI PA6
+#define MIKROBUS_1_DIP_PWM      // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_INT      // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_RX       // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_TX       // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_SCL  PA4
+#define MIKROBUS_1_DIP_SDA  PA6
+
+#define MIKROBUS_2_DIP_AN   PA0
+#define MIKROBUS_2_DIP_RST  PA1
+#define MIKROBUS_2_DIP_CS   PA3
+#define MIKROBUS_2_DIP_SCK  PA4
+#define MIKROBUS_2_DIP_MISO PA5
+#define MIKROBUS_2_DIP_MOSI PA6
+#define MIKROBUS_2_DIP_PWM      // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_INT      // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_RX       // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_TX       // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_SCL  PA4
+#define MIKROBUS_2_DIP_SDA  PA6
+
+#define MIKROBUS_3_DIP_AN   PA4
+#define MIKROBUS_3_DIP_RST  PB0
+#define MIKROBUS_3_DIP_CS       // Pin not routed to mikroBUS.
+#define MIKROBUS_3_DIP_SCK  PA4
+#define MIKROBUS_3_DIP_MISO PA5
+#define MIKROBUS_3_DIP_MOSI PA6
+#define MIKROBUS_3_DIP_PWM  PB3
+#define MIKROBUS_3_DIP_INT  PB2
+#define MIKROBUS_3_DIP_RX       // Pin not routed to mikroBUS.
+#define MIKROBUS_3_DIP_TX       // Pin not routed to mikroBUS.
+#define MIKROBUS_3_DIP_SCL  PA4
+#define MIKROBUS_3_DIP_SDA  PA6
+
+#define USB_UART_DIP_TX         // UART not supported
+#define USB_UART_DIP_RX         // UART not supported
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _DIP_SOCKET_H_
+// ------------------------------------------------------------------------- END
diff --git a/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip20/dip_socket.h b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip20/dip_socket.h
new file mode 100644
index 000000000..a659b9623
--- /dev/null
+++ b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip20/dip_socket.h
@@ -0,0 +1,58 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  dip_socket.h
+ * @brief Dip socket mikrobus pin mapping.
+ */
+
+#ifndef _DIP_SOCKET_H_
+#define _DIP_SOCKET_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "dip20b/dip_socket.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _DIP_SOCKET_H_
+// ------------------------------------------------------------------------- END
diff --git a/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip20a/dip_socket.h b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip20a/dip_socket.h
new file mode 100644
index 000000000..e6d0efc41
--- /dev/null
+++ b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip20a/dip_socket.h
@@ -0,0 +1,101 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  dip_socket.h
+ * @brief Dip socket mikrobus pin mapping.
+ */
+
+#ifndef _DIP_SOCKET_H_
+#define _DIP_SOCKET_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_target.h"
+
+/// Mapping
+#define MIKROBUS_1_DIP_AN       // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_RST      // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_CS       // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_SCK  PB7
+#define MIKROBUS_1_DIP_MISO PB6
+#define MIKROBUS_1_DIP_MOSI PB5
+#define MIKROBUS_1_DIP_PWM  PD4
+#define MIKROBUS_1_DIP_INT  PD2
+#define MIKROBUS_1_DIP_RX   PD0
+#define MIKROBUS_1_DIP_TX   PD1
+#define MIKROBUS_1_DIP_SCL      // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_SDA      // Pin not routed to mikroBUS.
+
+#define MIKROBUS_2_DIP_AN   PA0
+#define MIKROBUS_2_DIP_RST  PA1
+#define MIKROBUS_2_DIP_CS       // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_SCK  PB7
+#define MIKROBUS_2_DIP_MISO PB6
+#define MIKROBUS_2_DIP_MOSI PB5
+#define MIKROBUS_2_DIP_PWM  PD5
+#define MIKROBUS_2_DIP_INT  PD3
+#define MIKROBUS_2_DIP_RX   PD0
+#define MIKROBUS_2_DIP_TX   PD1
+#define MIKROBUS_2_DIP_SCL      // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_SDA      // Pin not routed to mikroBUS.
+
+#define MIKROBUS_3_DIP_AN       // Pin not routed to mikroBUS.
+#define MIKROBUS_3_DIP_RST  PB0
+#define MIKROBUS_3_DIP_CS   PB4
+#define MIKROBUS_3_DIP_SCK  PB7
+#define MIKROBUS_3_DIP_MISO PB6
+#define MIKROBUS_3_DIP_MOSI PB5
+#define MIKROBUS_3_DIP_PWM  PB3
+#define MIKROBUS_3_DIP_INT  PB2
+#define MIKROBUS_3_DIP_RX   PD2
+#define MIKROBUS_3_DIP_TX   PD3
+#define MIKROBUS_3_DIP_SCL      // Pin not routed to mikroBUS.
+#define MIKROBUS_3_DIP_SDA      // Pin not routed to mikroBUS.
+
+#define USB_UART_DIP_TX     PD1
+#define USB_UART_DIP_RX     PD0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _DIP_SOCKET_H_
+// ------------------------------------------------------------------------- END
diff --git a/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip20b/dip_socket.h b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip20b/dip_socket.h
new file mode 100644
index 000000000..19e25b563
--- /dev/null
+++ b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip20b/dip_socket.h
@@ -0,0 +1,101 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  dip_socket.h
+ * @brief Dip socket mikrobus pin mapping.
+ */
+
+#ifndef _DIP_SOCKET_H_
+#define _DIP_SOCKET_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_target.h"
+
+/// Mapping
+#define MIKROBUS_1_DIP_AN   PA7
+#define MIKROBUS_1_DIP_RST  PA6
+#define MIKROBUS_1_DIP_CS   PA5
+#define MIKROBUS_1_DIP_SCK  PB2
+#define MIKROBUS_1_DIP_MISO PB1
+#define MIKROBUS_1_DIP_MOSI PB0
+#define MIKROBUS_1_DIP_PWM      // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_INT      // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_RX       // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_TX       // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_SCL  PB2
+#define MIKROBUS_1_DIP_SDA  PB0
+
+#define MIKROBUS_2_DIP_AN   PA0
+#define MIKROBUS_2_DIP_RST  PA1
+#define MIKROBUS_2_DIP_CS   PA3
+#define MIKROBUS_2_DIP_SCK  PB2
+#define MIKROBUS_2_DIP_MISO PB1
+#define MIKROBUS_2_DIP_MOSI PB0
+#define MIKROBUS_2_DIP_PWM      // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_INT      // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_RX       // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_TX       // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_SCL  PB2
+#define MIKROBUS_2_DIP_SDA  PB0
+
+#define MIKROBUS_3_DIP_AN   PA4
+#define MIKROBUS_3_DIP_RST  PB0
+#define MIKROBUS_3_DIP_CS   PB4
+#define MIKROBUS_3_DIP_SCK  PB2
+#define MIKROBUS_3_DIP_MISO PB1
+#define MIKROBUS_3_DIP_MOSI PB0
+#define MIKROBUS_3_DIP_PWM  PB3
+#define MIKROBUS_3_DIP_INT  PB2
+#define MIKROBUS_3_DIP_RX       // Pin not routed to mikroBUS.
+#define MIKROBUS_3_DIP_TX       // Pin not routed to mikroBUS.
+#define MIKROBUS_3_DIP_SCL  PB2
+#define MIKROBUS_3_DIP_SDA  PB0
+
+#define USB_UART_DIP_TX         // UART not supported
+#define USB_UART_DIP_RX         // UART not supported
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _DIP_SOCKET_H_
+// ------------------------------------------------------------------------- END
diff --git a/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip28/dip_socket.h b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip28/dip_socket.h
new file mode 100644
index 000000000..2eab2f760
--- /dev/null
+++ b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip28/dip_socket.h
@@ -0,0 +1,101 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  dip_socket.h
+ * @brief Dip socket mikrobus pin mapping.
+ */
+
+#ifndef _DIP_SOCKET_H_
+#define _DIP_SOCKET_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_target.h"
+
+/// Mapping
+#define MIKROBUS_1_DIP_AN       // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_RST      // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_CS       // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_SCK  PB5
+#define MIKROBUS_1_DIP_MISO PB4
+#define MIKROBUS_1_DIP_MOSI PB3
+#define MIKROBUS_1_DIP_PWM  PD4
+#define MIKROBUS_1_DIP_INT  PD2
+#define MIKROBUS_1_DIP_RX   PD0
+#define MIKROBUS_1_DIP_TX   PD1
+#define MIKROBUS_1_DIP_SCL  PC5
+#define MIKROBUS_1_DIP_SDA  PC4
+
+#define MIKROBUS_2_DIP_AN       // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_RST      // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_CS       // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_SCK  PB5
+#define MIKROBUS_2_DIP_MISO PB4
+#define MIKROBUS_2_DIP_MOSI PB3
+#define MIKROBUS_2_DIP_PWM  PD5
+#define MIKROBUS_2_DIP_INT  PD3
+#define MIKROBUS_2_DIP_RX   PD0
+#define MIKROBUS_2_DIP_TX   PD1
+#define MIKROBUS_2_DIP_SCL  PC5
+#define MIKROBUS_2_DIP_SDA  PC4
+
+#define MIKROBUS_3_DIP_AN       // Pin not routed to mikroBUS.
+#define MIKROBUS_3_DIP_RST  PB0
+#define MIKROBUS_3_DIP_CS   PB4
+#define MIKROBUS_3_DIP_SCK  PB5
+#define MIKROBUS_3_DIP_MISO PB4
+#define MIKROBUS_3_DIP_MOSI PB3
+#define MIKROBUS_3_DIP_PWM  PB3
+#define MIKROBUS_3_DIP_INT  PB2
+#define MIKROBUS_3_DIP_RX   PD2
+#define MIKROBUS_3_DIP_TX   PD3
+#define MIKROBUS_3_DIP_SCL  PC5
+#define MIKROBUS_3_DIP_SDA  PC4
+
+#define USB_UART_DIP_TX         // UART not supported
+#define USB_UART_DIP_RX         // UART not supported
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _DIP_SOCKET_H_
+// ------------------------------------------------------------------------- END
diff --git a/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip40/dip_socket.h b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip40/dip_socket.h
new file mode 100644
index 000000000..7b46ee485
--- /dev/null
+++ b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip40/dip_socket.h
@@ -0,0 +1,58 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  dip_socket.h
+ * @brief Dip socket mikrobus pin mapping.
+ */
+
+#ifndef _DIP_SOCKET_H_
+#define _DIP_SOCKET_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "dip40b/dip_socket.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _DIP_SOCKET_H_
+// ------------------------------------------------------------------------- END
diff --git a/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip40a/dip_socket.h b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip40a/dip_socket.h
new file mode 100644
index 000000000..5a1210977
--- /dev/null
+++ b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip40a/dip_socket.h
@@ -0,0 +1,101 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  dip_socket.h
+ * @brief Dip socket mikrobus pin mapping.
+ */
+
+#ifndef _DIP_SOCKET_H_
+#define _DIP_SOCKET_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_target.h"
+
+/// Mapping
+#define MIKROBUS_1_DIP_AN   PA7
+#define MIKROBUS_1_DIP_RST  PA6
+#define MIKROBUS_1_DIP_CS   PA5
+#define MIKROBUS_1_DIP_SCK  PB7
+#define MIKROBUS_1_DIP_MISO PB6
+#define MIKROBUS_1_DIP_MOSI PB5
+#define MIKROBUS_1_DIP_PWM  PD4
+#define MIKROBUS_1_DIP_INT  PD2
+#define MIKROBUS_1_DIP_RX   PD0
+#define MIKROBUS_1_DIP_TX   PD1
+#define MIKROBUS_1_DIP_SCL  PC0
+#define MIKROBUS_1_DIP_SDA  PC1
+
+#define MIKROBUS_2_DIP_AN   PA0
+#define MIKROBUS_2_DIP_RST  PA1
+#define MIKROBUS_2_DIP_CS   PA3
+#define MIKROBUS_2_DIP_SCK  PB7
+#define MIKROBUS_2_DIP_MISO PB6
+#define MIKROBUS_2_DIP_MOSI PB5
+#define MIKROBUS_2_DIP_PWM  PD5
+#define MIKROBUS_2_DIP_INT  PD3
+#define MIKROBUS_2_DIP_RX   PD0
+#define MIKROBUS_2_DIP_TX   PD1
+#define MIKROBUS_2_DIP_SCL  PC0
+#define MIKROBUS_2_DIP_SDA  PC1
+
+#define MIKROBUS_3_DIP_AN   PA4
+#define MIKROBUS_3_DIP_RST  PB0
+#define MIKROBUS_3_DIP_CS   PB4
+#define MIKROBUS_3_DIP_SCK  PB7
+#define MIKROBUS_3_DIP_MISO PB6
+#define MIKROBUS_3_DIP_MOSI PB5
+#define MIKROBUS_3_DIP_PWM  PB3
+#define MIKROBUS_3_DIP_INT  PB2
+#define MIKROBUS_3_DIP_RX   PD2
+#define MIKROBUS_3_DIP_TX   PD3
+#define MIKROBUS_3_DIP_SCL  PC0
+#define MIKROBUS_3_DIP_SDA  PC1
+
+#define USB_UART_DIP_TX     PD1
+#define USB_UART_DIP_RX     PD0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _DIP_SOCKET_H_
+// ------------------------------------------------------------------------- END
diff --git a/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip40b/dip_socket.h b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip40b/dip_socket.h
new file mode 100644
index 000000000..5a1210977
--- /dev/null
+++ b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip40b/dip_socket.h
@@ -0,0 +1,101 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  dip_socket.h
+ * @brief Dip socket mikrobus pin mapping.
+ */
+
+#ifndef _DIP_SOCKET_H_
+#define _DIP_SOCKET_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_target.h"
+
+/// Mapping
+#define MIKROBUS_1_DIP_AN   PA7
+#define MIKROBUS_1_DIP_RST  PA6
+#define MIKROBUS_1_DIP_CS   PA5
+#define MIKROBUS_1_DIP_SCK  PB7
+#define MIKROBUS_1_DIP_MISO PB6
+#define MIKROBUS_1_DIP_MOSI PB5
+#define MIKROBUS_1_DIP_PWM  PD4
+#define MIKROBUS_1_DIP_INT  PD2
+#define MIKROBUS_1_DIP_RX   PD0
+#define MIKROBUS_1_DIP_TX   PD1
+#define MIKROBUS_1_DIP_SCL  PC0
+#define MIKROBUS_1_DIP_SDA  PC1
+
+#define MIKROBUS_2_DIP_AN   PA0
+#define MIKROBUS_2_DIP_RST  PA1
+#define MIKROBUS_2_DIP_CS   PA3
+#define MIKROBUS_2_DIP_SCK  PB7
+#define MIKROBUS_2_DIP_MISO PB6
+#define MIKROBUS_2_DIP_MOSI PB5
+#define MIKROBUS_2_DIP_PWM  PD5
+#define MIKROBUS_2_DIP_INT  PD3
+#define MIKROBUS_2_DIP_RX   PD0
+#define MIKROBUS_2_DIP_TX   PD1
+#define MIKROBUS_2_DIP_SCL  PC0
+#define MIKROBUS_2_DIP_SDA  PC1
+
+#define MIKROBUS_3_DIP_AN   PA4
+#define MIKROBUS_3_DIP_RST  PB0
+#define MIKROBUS_3_DIP_CS   PB4
+#define MIKROBUS_3_DIP_SCK  PB7
+#define MIKROBUS_3_DIP_MISO PB6
+#define MIKROBUS_3_DIP_MOSI PB5
+#define MIKROBUS_3_DIP_PWM  PB3
+#define MIKROBUS_3_DIP_INT  PB2
+#define MIKROBUS_3_DIP_RX   PD2
+#define MIKROBUS_3_DIP_TX   PD3
+#define MIKROBUS_3_DIP_SCL  PC0
+#define MIKROBUS_3_DIP_SDA  PC1
+
+#define USB_UART_DIP_TX     PD1
+#define USB_UART_DIP_RX     PD0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _DIP_SOCKET_H_
+// ------------------------------------------------------------------------- END
diff --git a/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip8/dip_socket.h b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip8/dip_socket.h
new file mode 100644
index 000000000..8b9c2ee19
--- /dev/null
+++ b/bsp/board/include/boards/board_easyavr_v7/dip_sockets/dip8/dip_socket.h
@@ -0,0 +1,101 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  dip_socket.h
+ * @brief Dip socket mikrobus pin mapping.
+ */
+
+#ifndef _DIP_SOCKET_H_
+#define _DIP_SOCKET_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_target.h"
+
+/// Mapping
+#define MIKROBUS_1_DIP_AN       // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_RST      // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_CS       // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_SCK      // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_MISO     // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_MOSI     // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_PWM      // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_INT      // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_RX       // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_TX       // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_SCL      // Pin not routed to mikroBUS.
+#define MIKROBUS_1_DIP_SDA      // Pin not routed to mikroBUS.
+
+#define MIKROBUS_2_DIP_AN       // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_RST      // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_CS       // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_SCK      // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_MISO     // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_MOSI     // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_PWM      // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_INT      // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_RX       // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_TX       // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_SCL      // Pin not routed to mikroBUS.
+#define MIKROBUS_2_DIP_SDA      // Pin not routed to mikroBUS.
+
+#define MIKROBUS_3_DIP_AN       // Pin not routed to mikroBUS.
+#define MIKROBUS_3_DIP_RST  PB0
+#define MIKROBUS_3_DIP_CS   PB4
+#define MIKROBUS_3_DIP_SCK      // Pin not routed to mikroBUS.
+#define MIKROBUS_3_DIP_MISO     // Pin not routed to mikroBUS.
+#define MIKROBUS_3_DIP_MOSI     // Pin not routed to mikroBUS.
+#define MIKROBUS_3_DIP_PWM  PB3
+#define MIKROBUS_3_DIP_INT      // Pin not routed to mikroBUS.
+#define MIKROBUS_3_DIP_RX       // Pin not routed to mikroBUS.
+#define MIKROBUS_3_DIP_TX       // Pin not routed to mikroBUS.
+#define MIKROBUS_3_DIP_SCL      // Pin not routed to mikroBUS.
+#define MIKROBUS_3_DIP_SDA      // Pin not routed to mikroBUS.
+
+#define USB_UART_DIP_TX         // UART not supported
+#define USB_UART_DIP_RX         // UART not supported
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _DIP_SOCKET_H_
+// ------------------------------------------------------------------------- END
diff --git a/bsp/board/include/mcu_cards/sibrain_for_atmega/mcu_card.h b/bsp/board/include/mcu_cards/sibrain_for_atmega/mcu_card.h
new file mode 100644
index 000000000..6e84b0e18
--- /dev/null
+++ b/bsp/board/include/mcu_cards/sibrain_for_atmega/mcu_card.h
@@ -0,0 +1,419 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  mcu_card.h
+ * @brief MCU card connections mapping.
+ */
+
+#ifndef _MCU_CARD_H_
+#define _MCU_CARD_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_target.h"
+
+// Hardware revision number
+#define MCU_CARD_REV_MAJOR (0)
+#define MCU_CARD_REV_MINOR (81)
+
+#define NC HAL_PIN_NC
+
+// TODO
+#define PORT_MASK_LOW  (uint8_t)0xF
+#define PORT_MASK_HIGH (uint8_t)0xF0
+
+// Left connector
+#define LEFT_CN_PIN_001 PA0
+#define LEFT_CN_PIN_002 PA1
+#define LEFT_CN_PIN_003 PA2
+#define LEFT_CN_PIN_004 PA3
+#define LEFT_CN_PIN_005 PA4
+#define LEFT_CN_PIN_006 PA5
+#define LEFT_CN_PIN_007 PA6
+#define LEFT_CN_PIN_008 PA7
+#define LEFT_CN_PIN_009 NC
+#define LEFT_CN_PIN_010 NC
+#define LEFT_CN_PIN_011 NC
+#define LEFT_CN_PIN_012 PB0
+#define LEFT_CN_PIN_013 PB1
+#define LEFT_CN_PIN_014 PB2
+#define LEFT_CN_PIN_015 PB3
+#define LEFT_CN_PIN_016 PB4
+#define LEFT_CN_PIN_017 PB5
+#define LEFT_CN_PIN_018 PB6
+#define LEFT_CN_PIN_019 PB7
+#define LEFT_CN_PIN_020 NC
+#define LEFT_CN_PIN_021 NC
+#define LEFT_CN_PIN_022 NC
+#define LEFT_CN_PIN_023 NC
+#define LEFT_CN_PIN_024 NC
+#define LEFT_CN_PIN_025 PD7
+#define LEFT_CN_PIN_026 PD6
+#define LEFT_CN_PIN_027 PD5
+#define LEFT_CN_PIN_028 PD4
+#define LEFT_CN_PIN_029 PD3
+#define LEFT_CN_PIN_030 PA0
+#define LEFT_CN_PIN_031 PA1
+#define LEFT_CN_PIN_032 PA2
+#define LEFT_CN_PIN_033 PA3
+#define LEFT_CN_PIN_034 PA4
+#define LEFT_CN_PIN_035 PA5
+#define LEFT_CN_PIN_036 PA6
+#define LEFT_CN_PIN_037 PA7
+#define LEFT_CN_PIN_038 PC0
+#define LEFT_CN_PIN_039 PC1
+#define LEFT_CN_PIN_040 PC2
+#define LEFT_CN_PIN_041 PC3
+#define LEFT_CN_PIN_042 PC4
+#define LEFT_CN_PIN_043 PC5
+#define LEFT_CN_PIN_044 PC6
+#define LEFT_CN_PIN_045 PC7
+#define LEFT_CN_PIN_046 NC
+#define LEFT_CN_PIN_047 NC
+#define LEFT_CN_PIN_048 NC
+#define LEFT_CN_PIN_049 NC
+#define LEFT_CN_PIN_050 NC
+#define LEFT_CN_PIN_051 NC
+#define LEFT_CN_PIN_052 NC
+#define LEFT_CN_PIN_053 NC
+#define LEFT_CN_PIN_054 PB0
+#define LEFT_CN_PIN_055 PJ1
+#define LEFT_CN_PIN_056 PB7
+#define LEFT_CN_PIN_057 PJ0
+#define LEFT_CN_PIN_058 PE4
+#define LEFT_CN_PIN_059 PE5
+#define LEFT_CN_PIN_060 PD1
+#define LEFT_CN_PIN_061 PD0
+#define LEFT_CN_PIN_062 PD2
+#define LEFT_CN_PIN_063 NC
+#define LEFT_CN_PIN_064 NC
+#define LEFT_CN_PIN_065 NC
+#define LEFT_CN_PIN_066 NC
+#define LEFT_CN_PIN_067 NC
+#define LEFT_CN_PIN_068 NC
+#define LEFT_CN_PIN_069 PC0
+#define LEFT_CN_PIN_070 PC1
+#define LEFT_CN_PIN_071 PC2
+#define LEFT_CN_PIN_072 PC3
+#define LEFT_CN_PIN_073 PC4
+#define LEFT_CN_PIN_074 PC5
+#define LEFT_CN_PIN_075 PC6
+#define LEFT_CN_PIN_076 PC7
+#define LEFT_CN_PIN_077 PD0
+#define LEFT_CN_PIN_078 PD1
+#define LEFT_CN_PIN_079 PD2
+#define LEFT_CN_PIN_080 PD3
+#define LEFT_CN_PIN_081 PD4
+#define LEFT_CN_PIN_082 PD5
+#define LEFT_CN_PIN_083 PD6
+#define LEFT_CN_PIN_084 PD7
+#define LEFT_CN_PIN_085 PE5
+#define LEFT_CN_PIN_086 PE4
+#define LEFT_CN_PIN_087 PE1
+#define LEFT_CN_PIN_088 PE0
+#define LEFT_CN_PIN_089 PH7
+#define LEFT_CN_PIN_090 PB7
+#define LEFT_CN_PIN_091 PB2
+#define LEFT_CN_PIN_092 PB3
+#define LEFT_CN_PIN_093 PB1
+#define LEFT_CN_PIN_094 PE2
+#define LEFT_CN_PIN_095 PE3
+#define LEFT_CN_PIN_096 PF5
+#define LEFT_CN_PIN_097 PE5
+#define LEFT_CN_PIN_098 PE4
+#define LEFT_CN_PIN_099 PE1
+#define LEFT_CN_PIN_100 PE0
+#define LEFT_CN_PIN_101 PH6
+#define LEFT_CN_PIN_102 PB7
+#define LEFT_CN_PIN_103 PB2
+#define LEFT_CN_PIN_104 PB3
+#define LEFT_CN_PIN_105 PB1
+#define LEFT_CN_PIN_106 PE6
+#define LEFT_CN_PIN_107 PE7
+#define LEFT_CN_PIN_108 PF3
+#define LEFT_CN_PIN_109 PE5
+#define LEFT_CN_PIN_110 PE4
+#define LEFT_CN_PIN_111 PE1
+#define LEFT_CN_PIN_112 PE0
+#define LEFT_CN_PIN_113 PH5
+#define LEFT_CN_PIN_114 PB6
+#define LEFT_CN_PIN_115 PB2
+#define LEFT_CN_PIN_116 PB3
+#define LEFT_CN_PIN_117 PB1
+#define LEFT_CN_PIN_118 PH3
+#define LEFT_CN_PIN_119 PH2
+#define LEFT_CN_PIN_120 PF2
+#define LEFT_CN_PIN_121 PE5
+#define LEFT_CN_PIN_122 PE4
+#define LEFT_CN_PIN_123 PE1
+#define LEFT_CN_PIN_124 PE0
+#define LEFT_CN_PIN_125 PH4
+#define LEFT_CN_PIN_126 PB5
+#define LEFT_CN_PIN_127 PB2
+#define LEFT_CN_PIN_128 PB3
+#define LEFT_CN_PIN_129 PB1
+#define LEFT_CN_PIN_130 PH1
+#define LEFT_CN_PIN_131 PH0
+#define LEFT_CN_PIN_132 PF1
+#define LEFT_CN_PIN_133 PE5
+#define LEFT_CN_PIN_134 PE4
+#define LEFT_CN_PIN_135 PE1
+#define LEFT_CN_PIN_136 PE0
+#define LEFT_CN_PIN_137 PD1
+#define LEFT_CN_PIN_138 PB4
+#define LEFT_CN_PIN_139 PB2
+#define LEFT_CN_PIN_140 PB3
+#define LEFT_CN_PIN_141 PB1
+#define LEFT_CN_PIN_142 PG1
+#define LEFT_CN_PIN_143 PG0
+#define LEFT_CN_PIN_144 PF0
+#define LEFT_CN_PIN_145 NC
+#define LEFT_CN_PIN_146 NC
+#define LEFT_CN_PIN_147 NC
+#define LEFT_CN_PIN_148 NC
+#define LEFT_CN_PIN_149 NC
+#define LEFT_CN_PIN_150 NC
+#define LEFT_CN_PIN_151 NC
+#define LEFT_CN_PIN_152 NC
+#define LEFT_CN_PIN_153 NC
+#define LEFT_CN_PIN_154 NC
+#define LEFT_CN_PIN_155 NC
+#define LEFT_CN_PIN_156 NC
+#define LEFT_CN_PIN_157 NC
+#define LEFT_CN_PIN_158 NC
+#define LEFT_CN_PIN_159 NC
+#define LEFT_CN_PIN_160 NC
+#define LEFT_CN_PIN_161 NC
+#define LEFT_CN_PIN_162 NC
+#define LEFT_CN_PIN_163 NC
+#define LEFT_CN_PIN_164 NC
+#define LEFT_CN_PIN_165 NC
+#define LEFT_CN_PIN_166 NC
+#define LEFT_CN_PIN_167 NC
+#define LEFT_CN_PIN_168 NC
+
+// Right connector
+#define RIGHT_CN_PIN_001 PE0
+#define RIGHT_CN_PIN_002 PE1
+#define RIGHT_CN_PIN_003 PE2
+#define RIGHT_CN_PIN_004 PE3
+#define RIGHT_CN_PIN_005 PE4
+#define RIGHT_CN_PIN_006 PE5
+#define RIGHT_CN_PIN_007 PE6
+#define RIGHT_CN_PIN_008 PE7
+#define RIGHT_CN_PIN_009 NC
+#define RIGHT_CN_PIN_010 NC
+#define RIGHT_CN_PIN_011 NC
+#define RIGHT_CN_PIN_012 PG0
+#define RIGHT_CN_PIN_013 PG1
+#define RIGHT_CN_PIN_014 PG2
+#define RIGHT_CN_PIN_015 PG3
+#define RIGHT_CN_PIN_016 PG4
+#define RIGHT_CN_PIN_017 NC
+#define RIGHT_CN_PIN_018 NC
+#define RIGHT_CN_PIN_019 NC
+#define RIGHT_CN_PIN_020 NC
+#define RIGHT_CN_PIN_021 NC
+#define RIGHT_CN_PIN_022 NC
+#define RIGHT_CN_PIN_023 NC
+#define RIGHT_CN_PIN_024 NC
+#define RIGHT_CN_PIN_025 NC
+#define RIGHT_CN_PIN_026 NC
+#define RIGHT_CN_PIN_027 NC
+#define RIGHT_CN_PIN_028 NC
+#define RIGHT_CN_PIN_029 NC
+#define RIGHT_CN_PIN_030 NC
+#define RIGHT_CN_PIN_031 NC
+#define RIGHT_CN_PIN_032 NC
+#define RIGHT_CN_PIN_033 NC
+#define RIGHT_CN_PIN_034 NC
+#define RIGHT_CN_PIN_035 NC
+#define RIGHT_CN_PIN_036 NC
+#define RIGHT_CN_PIN_037 NC
+#define RIGHT_CN_PIN_038 NC
+#define RIGHT_CN_PIN_039 NC
+#define RIGHT_CN_PIN_040 NC
+#define RIGHT_CN_PIN_041 NC
+#define RIGHT_CN_PIN_042 NC
+#define RIGHT_CN_PIN_043 NC
+#define RIGHT_CN_PIN_044 NC
+#define RIGHT_CN_PIN_045 NC
+#define RIGHT_CN_PIN_046 NC
+#define RIGHT_CN_PIN_047 NC
+#define RIGHT_CN_PIN_048 NC
+#define RIGHT_CN_PIN_049 NC
+#define RIGHT_CN_PIN_050 NC
+#define RIGHT_CN_PIN_051 NC
+#define RIGHT_CN_PIN_052 NC
+#define RIGHT_CN_PIN_053 NC
+#define RIGHT_CN_PIN_054 NC
+#define RIGHT_CN_PIN_055 NC
+#define RIGHT_CN_PIN_056 NC
+#define RIGHT_CN_PIN_057 NC
+#define RIGHT_CN_PIN_058 NC
+#define RIGHT_CN_PIN_059 NC
+#define RIGHT_CN_PIN_060 NC
+#define RIGHT_CN_PIN_061 NC
+#define RIGHT_CN_PIN_062 NC
+#define RIGHT_CN_PIN_063 NC
+#define RIGHT_CN_PIN_064 NC
+#define RIGHT_CN_PIN_065 NC
+#define RIGHT_CN_PIN_066 NC
+#define RIGHT_CN_PIN_067 NC
+#define RIGHT_CN_PIN_068 NC
+#define RIGHT_CN_PIN_069 NC
+#define RIGHT_CN_PIN_070 NC
+#define RIGHT_CN_PIN_071 NC
+#define RIGHT_CN_PIN_072 NC
+#define RIGHT_CN_PIN_073 NC
+#define RIGHT_CN_PIN_074 NC
+#define RIGHT_CN_PIN_075 NC
+#define RIGHT_CN_PIN_076 NC
+#define RIGHT_CN_PIN_077 NC
+#define RIGHT_CN_PIN_078 NC
+#define RIGHT_CN_PIN_079 NC
+#define RIGHT_CN_PIN_080 NC
+#define RIGHT_CN_PIN_081 NC
+#define RIGHT_CN_PIN_082 NC
+#define RIGHT_CN_PIN_083 NC
+#define RIGHT_CN_PIN_084 NC
+#define RIGHT_CN_PIN_085 NC
+#define RIGHT_CN_PIN_086 NC
+#define RIGHT_CN_PIN_087 NC
+#define RIGHT_CN_PIN_088 NC
+#define RIGHT_CN_PIN_089 NC
+#define RIGHT_CN_PIN_090 NC
+#define RIGHT_CN_PIN_091 NC
+#define RIGHT_CN_PIN_092 NC
+#define RIGHT_CN_PIN_093 NC
+#define RIGHT_CN_PIN_094 NC
+#define RIGHT_CN_PIN_095 NC
+#define RIGHT_CN_PIN_096 NC
+#define RIGHT_CN_PIN_097 NC
+#define RIGHT_CN_PIN_098 NC
+#define RIGHT_CN_PIN_099 NC
+#define RIGHT_CN_PIN_100 NC
+#define RIGHT_CN_PIN_101 NC
+#define RIGHT_CN_PIN_102 NC
+#define RIGHT_CN_PIN_103 NC
+#define RIGHT_CN_PIN_104 NC
+#define RIGHT_CN_PIN_105 NC
+#define RIGHT_CN_PIN_106 NC
+#define RIGHT_CN_PIN_107 NC
+#define RIGHT_CN_PIN_108 NC
+#define RIGHT_CN_PIN_109 NC
+#define RIGHT_CN_PIN_110 NC
+#define RIGHT_CN_PIN_111 NC
+#define RIGHT_CN_PIN_112 NC
+#define RIGHT_CN_PIN_113 NC
+#define RIGHT_CN_PIN_114 NC
+#define RIGHT_CN_PIN_115 NC
+#define RIGHT_CN_PIN_116 NC
+#define RIGHT_CN_PIN_117 NC
+#define RIGHT_CN_PIN_118 NC
+#define RIGHT_CN_PIN_119 NC
+#define RIGHT_CN_PIN_120 NC
+#define RIGHT_CN_PIN_121 NC
+#define RIGHT_CN_PIN_122 NC
+#define RIGHT_CN_PIN_123 NC
+#define RIGHT_CN_PIN_124 NC
+#define RIGHT_CN_PIN_125 PF3
+#define RIGHT_CN_PIN_126 PF2
+#define RIGHT_CN_PIN_127 PF1
+#define RIGHT_CN_PIN_128 PF0
+#define RIGHT_CN_PIN_129 NC
+#define RIGHT_CN_PIN_130 NC
+#define RIGHT_CN_PIN_131 NC
+#define RIGHT_CN_PIN_132 NC
+#define RIGHT_CN_PIN_133 NC
+#define RIGHT_CN_PIN_134 NC
+#define RIGHT_CN_PIN_135 NC
+#define RIGHT_CN_PIN_136 NC
+#define RIGHT_CN_PIN_137 NC
+#define RIGHT_CN_PIN_138 NC
+#define RIGHT_CN_PIN_139 NC
+#define RIGHT_CN_PIN_140 NC
+#define RIGHT_CN_PIN_141 NC
+#define RIGHT_CN_PIN_142 NC
+#define RIGHT_CN_PIN_143 PJ6
+#define RIGHT_CN_PIN_144 PJ5
+#define RIGHT_CN_PIN_145 PJ5
+#define RIGHT_CN_PIN_146 PJ3
+#define RIGHT_CN_PIN_147 PJ2
+#define RIGHT_CN_PIN_148 PJ1
+#define RIGHT_CN_PIN_149 PJ0
+#define RIGHT_CN_PIN_150 PH7
+#define RIGHT_CN_PIN_151 PH6
+#define RIGHT_CN_PIN_152 PH5
+#define RIGHT_CN_PIN_153 PH4
+#define RIGHT_CN_PIN_154 PH3
+#define RIGHT_CN_PIN_155 PH2
+#define RIGHT_CN_PIN_156 PH1
+#define RIGHT_CN_PIN_157 PH0
+#define RIGHT_CN_PIN_158 NC
+#define RIGHT_CN_PIN_159 PE0
+#define RIGHT_CN_PIN_160 PE1
+#define RIGHT_CN_PIN_161 PF7
+#define RIGHT_CN_PIN_162 PF6
+#define RIGHT_CN_PIN_163 PF5
+#define RIGHT_CN_PIN_164 PF4
+#define RIGHT_CN_PIN_165 PF3
+#define RIGHT_CN_PIN_166 PF2
+#define RIGHT_CN_PIN_167 PF1
+#define RIGHT_CN_PIN_168 PF0
+
+// TODO
+
+#define LCD_TFT_8BIT_CH0 PORT_A
+#define LCD_TFT_CH0_8BIT_MASK 0xFF
+
+#define LCD_TFT_16BIT_CH0 PORT_A
+#define LCD_TFT_16BIT_CH0_MASK 0xFF
+
+#define LCD_TFT_16BIT_CH1 PORT_C
+#define LCD_TFT_16BIT_CH1_MASK 0xFF
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _MCU_CARD_H_
+// ------------------------------------------------------------------------- END
diff --git a/bsp/generic/include/generic_pointer.h b/bsp/generic/include/generic_pointer.h
index facca04a1..68c76ccd7 100644
--- a/bsp/generic/include/generic_pointer.h
+++ b/bsp/generic/include/generic_pointer.h
@@ -50,7 +50,7 @@ extern "C"{
 
 // TODO Update macro as new toolchains are added
 
-#ifndef __MIKROC_AI_FOR_PIC__
+#if !defined(__MIKROC_AI_FOR_PIC__) && !defined(__MIKROC_AI_FOR_AVR__)
 #define __generic_ptr
 #else
 #define __generic_ptr __generic
diff --git a/cmake/utils.cmake b/cmake/utils.cmake
index 337aa4cb1..a0fce5ccc 100644
--- a/cmake/utils.cmake
+++ b/cmake/utils.cmake
@@ -109,7 +109,9 @@ function(find_chip_architecture _chip_architecture)
         endif()
     elseif(${CORE_NAME} MATCHES "RISCV")
         set(${_chip_architecture} "riscv" PARENT_SCOPE)
-    else()
+    elseif((${CORE_NAME} MATCHES "GT64K") OR (${CORE_NAME} MATCHES "LTE64K"))
+        set(${_chip_architecture} "avr_8bit" PARENT_SCOPE)
+        else()
         set(${_chip_architecture} "__chip_error__" PARENT_SCOPE)
     endif()
 endfunction()
@@ -136,7 +138,9 @@ function(find_cortex listArg)
     set(${list} ${local_list} PARENT_SCOPE)
 endfunction()
 
-
+#############################################################################
+## Function to find path to adequate mcu header file
+#############################################################################
 function(find_mcu_header_path listArg _mcu_header_path _mcu_name_first_7_chars)
 
     set(local_list ${listArg})
@@ -159,3 +163,58 @@ function(find_mcu_header_path listArg _mcu_header_path _mcu_name_first_7_chars)
 
     set(${list} ${local_list} PARENT_SCOPE)
 endfunction()
+
+#############################################################################
+## Function to check if module is supported for specific MCU
+#############################################################################
+function(set_module_support listArg listModules chip_name layer)
+    set(local_list ${listArg})
+    set(local_list_modules ${listModules})
+    string(TOLOWER ${chip_name} check_chip)
+
+    if(layer STREQUAL "drv_layer")
+        list(APPEND local_list MikroSDK.Driver.ADC)
+        list(APPEND local_list MikroSDK.Driver.GPIO.In)
+        list(APPEND local_list MikroSDK.Driver.GPIO.Out)
+        list(APPEND local_list MikroSDK.Driver.GPIO.Port)
+        list(APPEND local_list MikroSDK.Driver.I2C.Master)
+        list(APPEND local_list MikroSDK.Driver.PWM)
+        list(APPEND local_list MikroSDK.Driver.SPI.Master)
+        list(APPEND local_list MikroSDK.Driver.UART)
+    elseif (layer STREQUAL "hal_layer")
+        list(APPEND local_list MikroSDK.Hal.ADC)
+        list(APPEND local_list MikroSDK.Hal.GPIO)
+        list(APPEND local_list MikroSDK.Hal.I2C.Master)
+        list(APPEND local_list MikroSDK.Hal.PWM)
+        list(APPEND local_list MikroSDK.Hal.SPI.Master)
+        list(APPEND local_list MikroSDK.Hal.UART)
+        list(APPEND local_list MikroSDK.Hal.OneWire)
+    elseif(layer STREQUAL "hal_ll_layer")
+        list(APPEND local_list MikroSDK.HalLowLevel.ADC)
+        list(APPEND local_list MikroSDK.HalLowLevel.GPIO)
+        list(APPEND local_list MikroSDK.HalLowLevel.I2C.Master)
+        list(APPEND local_list MikroSDK.HalLowLevel.TIM)
+        list(APPEND local_list MikroSDK.HalLowLevel.SPI.Master)
+        list(APPEND local_list MikroSDK.HalLowLevel.UART)
+        list(APPEND local_list MikroSDK.HalLowLevel.OneWire)
+    endif()
+
+    list(APPEND local_list_modules msdk_adc)
+    list(APPEND local_list_modules msdk_gpio_in)
+    list(APPEND local_list_modules msdk_gpio_out)
+    list(APPEND local_list_modules msdk_gpio_port)
+    list(APPEND local_list_modules msdk_i2c_master)
+    list(APPEND local_list_modules msdk_pwm)
+    list(APPEND local_list_modules msdk_spi_master)
+    list(APPEND local_list_modules msdk_uart)
+
+    if(${check_chip} MATCHES "^at.+$")
+        message(INFO " One Wire not implemented for ${chip_name} for ${layer}.")
+    else()
+        list(APPEND local_list MikroSDK.Driver.OneWire)
+        list(APPEND local_list_modules msdk_onewire)
+    endif()
+
+    set(${list} ${local_list} PARENT_SCOPE)
+    set(${list} ${local_list_modules} PARENT_SCOPE)
+endfunction()
diff --git a/components/tft8/lib/CMakeLists.txt b/components/tft8/lib/CMakeLists.txt
index 3c8c13a84..9a16ed9c2 100644
--- a/components/tft8/lib/CMakeLists.txt
+++ b/components/tft8/lib/CMakeLists.txt
@@ -21,7 +21,7 @@ elseif(${_MSDK_MCU_CARD_NAME_} MATCHES "(^MCU_CARD_(.+)_STM32$)")
         list(APPEND tft8_def_list "__8_bit_interface__")
     endif()
 elseif(${_MSDK_MCU_CARD_NAME_} MATCHES "(^MCU_CARD_(.+)_PIC$)")
-    if(${_MSDK_MCU_CARD_NAME_} MATCHES "(^MCU_CARD_(([247])|(10))_FOR_PIC$)")
+    if(${_MSDK_MCU_CARD_NAME_} MATCHES "(^MCU_CARD_(([247])|([1][01]))_FOR_PIC$)")
         list(APPEND tft8_def_list "__8_bit_interface__")
     else()
         list(APPEND tft8_def_list "__16_bit_interface__")
@@ -42,6 +42,8 @@ elseif(${_MSDK_MCU_CARD_NAME_} MATCHES "(^MCU_CARD_(.+)TIVA$)")
     list(APPEND tft8_def_list "__16_bit_interface__")
 elseif(${_MSDK_MCU_CARD_NAME_} MATCHES "(^MCU_CARD_(.+)RISC_V$)")
     list(APPEND tft8_def_list "__8_bit_interface__")
+elseif(${_MSDK_MCU_CARD_NAME_} MATCHES "(^SIBRAIN_FOR_ATMEGA$)")
+    list(APPEND tft8_def_list "__16_bit_interface__")
 else()
     list(APPEND tft8_def_list "__16_bit_interface__")  ## by default select 16-bit port
 endif()
diff --git a/drv/lib/CMakeLists.txt b/drv/lib/CMakeLists.txt
index 958a1de8e..374d01aa3 100644
--- a/drv/lib/CMakeLists.txt
+++ b/drv/lib/CMakeLists.txt
@@ -1,11 +1,35 @@
 # ALL MODULES
 add_subdirectory(src/lib_drv)
-add_subdirectory(src/lib_drv_analog_in)
-add_subdirectory(src/lib_drv_digital_in)
-add_subdirectory(src/lib_drv_digital_out)
-add_subdirectory(src/lib_drv_i2c_master)
-add_subdirectory(src/lib_drv_port)
-add_subdirectory(src/lib_drv_pwm)
-add_subdirectory(src/lib_drv_spi_master)
-add_subdirectory(src/lib_drv_uart)
-add_subdirectory(src/lib_drv_one_wire)
+
+# SEPARATE MODULES
+set(module_list "")
+set(module_list_supported "")
+set_module_support(module_list module_list_supported ${MCU_NAME} "drv_layer")
+
+if (msdk_adc IN_LIST module_list_supported)
+    add_subdirectory(src/lib_drv_analog_in)
+endif()
+if (msdk_gpio_in IN_LIST module_list_supported)
+    add_subdirectory(src/lib_drv_digital_in)
+endif()
+if (msdk_gpio_out IN_LIST module_list_supported)
+    add_subdirectory(src/lib_drv_digital_out)
+endif()
+if (msdk_gpio_port IN_LIST module_list_supported)
+    add_subdirectory(src/lib_drv_i2c_master)
+endif()
+if (msdk_i2c_master IN_LIST module_list_supported)
+    add_subdirectory(src/lib_drv_port)
+endif()
+if (msdk_pwm IN_LIST module_list_supported)
+    add_subdirectory(src/lib_drv_pwm)
+endif()
+if (msdk_spi_master IN_LIST module_list_supported)
+    add_subdirectory(src/lib_drv_spi_master)
+endif()
+if (msdk_uart IN_LIST module_list_supported)
+    add_subdirectory(src/lib_drv_uart)
+endif()
+if (msdk_onewire IN_LIST module_list_supported)
+    add_subdirectory(src/lib_drv_one_wire)
+endif()
diff --git a/drv/lib/include/drv_one_wire.h b/drv/lib/include/drv_one_wire.h
index fd856e901..cdce63cd5 100644
--- a/drv/lib/include/drv_one_wire.h
+++ b/drv/lib/include/drv_one_wire.h
@@ -118,7 +118,12 @@ typedef struct {
  *       asm nop;    // To give an example...
  *   }
  *
- *   int main() {
+ * @endcode
+ *
+ *   Implementation example:
+ *
+ * @code
+ *
  *       // One Wire driver initialization configuration structure.
  *       static one_wire_t one_wire_object_1;
  *
@@ -139,8 +144,6 @@ typedef struct {
  *       // defined at the top of this code.
  *       one_wire_reset( &one_wire );
  *
- *   }
- *
  * @endcode
  */
 
diff --git a/drv/lib/src/lib_drv/CMakeLists.txt b/drv/lib/src/lib_drv/CMakeLists.txt
index 87c60027f..3120818e3 100644
--- a/drv/lib/src/lib_drv/CMakeLists.txt
+++ b/drv/lib/src/lib_drv/CMakeLists.txt
@@ -1,15 +1,11 @@
 mikrosdk_add_interface_library(lib_drv MikroSDK.Driver)
 
-target_link_libraries(lib_drv  INTERFACE
-    MikroSDK.Driver.ADC
-    MikroSDK.Driver.GPIO.In
-    MikroSDK.Driver.GPIO.Out
-    MikroSDK.Driver.GPIO.Port
-    MikroSDK.Driver.I2C.Master
-    MikroSDK.Driver.PWM
-    MikroSDK.Driver.SPI.Master
-    MikroSDK.Driver.UART
-    MikroSDK.Driver.OneWire
+set(module_list "")
+set(module_list_supported "")
+set_module_support(module_list module_list_supported ${MCU_NAME} "drv_layer")
+
+target_link_libraries(lib_drv INTERFACE
+    ${module_list}
 )
 
 target_include_directories(lib_drv
diff --git a/drv/lib/src/lib_drv_analog_in/CMakeLists.txt b/drv/lib/src/lib_drv_analog_in/CMakeLists.txt
index 860cc8cc0..b5c5a57ed 100644
--- a/drv/lib/src/lib_drv_analog_in/CMakeLists.txt
+++ b/drv/lib/src/lib_drv_analog_in/CMakeLists.txt
@@ -14,6 +14,10 @@ elseif(${MCU_NAME} MATCHES "(^TM(.+)$)")
     list(APPEND drv_def_list ANALOG_IN_RESOLUTION_CMAKE=ANALOG_IN_RESOLUTION_12_BIT)
 elseif(${MCU_NAME} MATCHES "(^GD32(.+)$)")
     list(APPEND drv_def_list ANALOG_IN_RESOLUTION_CMAKE=ANALOG_IN_RESOLUTION_12_BIT)
+elseif(${MCU_NAME} MATCHES "(^ATXMEGA(.+)$)")
+    list(APPEND drv_def_list ANALOG_IN_RESOLUTION_CMAKE=ANALOG_IN_RESOLUTION_12_BIT)
+elseif(${MCU_NAME} MATCHES "(^AT(.+)$)")
+    list(APPEND drv_def_list ANALOG_IN_RESOLUTION_CMAKE=ANALOG_IN_RESOLUTION_10_BIT)
 else()
     list(APPEND drv_def_list ANALOG_IN_RESOLUTION_CMAKE=ANALOG_IN_RESOLUTION_NOT_SET)
 endif()
diff --git a/hal/interface/CMakeLists.txt b/hal/interface/CMakeLists.txt
index 443d94f73..c592d774e 100644
--- a/hal/interface/CMakeLists.txt
+++ b/hal/interface/CMakeLists.txt
@@ -25,6 +25,8 @@ elseif(${MCU_NAME} MATCHES "(^PIC18(.+)$)")
     set(vendor_id "pic18")
 elseif(${MCU_NAME} MATCHES "(^GD32VF(.+)$)")
     set(vendor_id "gigadevice")
+elseif(${MCU_NAME} MATCHES "AT")
+    set(vendor_id "avr")
 else()
     set(vendor_id "__implementation_error__")
 endif()
diff --git a/hal/lib/CMakeLists.txt b/hal/lib/CMakeLists.txt
index 2b13a52e5..41f5945de 100644
--- a/hal/lib/CMakeLists.txt
+++ b/hal/lib/CMakeLists.txt
@@ -1,10 +1,29 @@
 # ALL MODULES
 add_subdirectory(src/lib_hal)
-#  SEPERATE MODULES
-add_subdirectory(src/lib_hal_adc)
-add_subdirectory(src/lib_hal_gpio)
-add_subdirectory(src/lib_hal_i2c_master)
-add_subdirectory(src/lib_hal_pwm)
-add_subdirectory(src/lib_hal_spi_master)
-add_subdirectory(src/lib_hal_uart)
-add_subdirectory(src/lib_hal_one_wire)
+
+# SEPARATE MODULES
+set(module_list "")
+set(module_list_supported "")
+set_module_support(module_list module_list_supported ${MCU_NAME} "hal_layer")
+
+if (msdk_adc IN_LIST module_list_supported)
+    add_subdirectory(src/lib_hal_adc)
+endif()
+if (msdk_gpio_in IN_LIST module_list_supported)
+    add_subdirectory(src/lib_hal_gpio)
+endif()
+if (msdk_i2c_master IN_LIST module_list_supported)
+    add_subdirectory(src/lib_hal_i2c_master)
+endif()
+if (msdk_pwm IN_LIST module_list_supported)
+    add_subdirectory(src/lib_hal_pwm)
+endif()
+if (msdk_spi_master IN_LIST module_list_supported)
+    add_subdirectory(src/lib_hal_spi_master)
+endif()
+if (msdk_uart IN_LIST module_list_supported)
+    add_subdirectory(src/lib_hal_uart)
+endif()
+if (msdk_onewire IN_LIST module_list_supported)
+    add_subdirectory(src/lib_hal_one_wire)
+endif()
diff --git a/hal/lib/include/hal_one_wire.h b/hal/lib/include/hal_one_wire.h
index 54c2974de..0fb6df774 100644
--- a/hal/lib/include/hal_one_wire.h
+++ b/hal/lib/include/hal_one_wire.h
@@ -117,7 +117,12 @@ typedef enum {
  *       asm nop;    // To give an example...
  *   }
  *
- *   int main() {
+ * @endcode
+ *
+ *   Implementation example:
+ *
+ * @code
+ *
  *       // One Wire driver initialization configuration structure.
  *       static hal_one_wire_t hal_one_wire_object_1;
  *
@@ -138,8 +143,6 @@ typedef enum {
  *       // defined at the top of this code.
  *       hal_one_wire_reset( &hal_one_wire );
  *
- *   }
- *
  * @endcode
  */
 
diff --git a/hal/lib/src/lib_hal/CMakeLists.txt b/hal/lib/src/lib_hal/CMakeLists.txt
index cf7c91ef9..77343d545 100644
--- a/hal/lib/src/lib_hal/CMakeLists.txt
+++ b/hal/lib/src/lib_hal/CMakeLists.txt
@@ -1,12 +1,10 @@
 add_library(lib_hal INTERFACE)
-add_library(MikroSDK.Hal  ALIAS lib_hal)
+add_library(MikroSDK.Hal ALIAS lib_hal)
 
-target_link_libraries(lib_hal  INTERFACE
-    MikroSDK.Hal.ADC
-    MikroSDK.Hal.GPIO
-    MikroSDK.Hal.I2C.Master
-    MikroSDK.Hal.PWM
-    MikroSDK.Hal.SPI.Master
-    MikroSDK.Hal.UART
-    MikroSDK.Hal.OneWire
+set(module_list "")
+set(module_list_supported "")
+set_module_support(module_list module_list_supported ${MCU_NAME} "hal_layer")
+
+target_link_libraries(lib_hal INTERFACE
+    ${module_list}
 )
diff --git a/hal/lib/src/lib_hal_adc/CMakeLists.txt b/hal/lib/src/lib_hal_adc/CMakeLists.txt
index 724c0f6da..f2d004330 100644
--- a/hal/lib/src/lib_hal_adc/CMakeLists.txt
+++ b/hal/lib/src/lib_hal_adc/CMakeLists.txt
@@ -14,6 +14,10 @@ elseif(${MCU_NAME} MATCHES "(^TM(.+)$)")
     list(APPEND hal_def_list HAL_ADC_RESOLUTION_CMAKE=HAL_ADC_RESOLUTION_12_BIT)
 elseif(${MCU_NAME} MATCHES "(^GD32(.+)$)")
     list(APPEND hal_def_list HAL_ADC_RESOLUTION_CMAKE=HAL_ADC_RESOLUTION_12_BIT)
+elseif(${MCU_NAME} MATCHES "(^ATXMEGA(.+)$)")
+    list(APPEND hal_def_list HAL_ADC_RESOLUTION_CMAKE=HAL_ADC_RESOLUTION_12_BIT)
+elseif(${MCU_NAME} MATCHES "(^AT(.+)$)")
+    list(APPEND hal_def_list HAL_ADC_RESOLUTION_CMAKE=HAL_ADC_RESOLUTION_10_BIT)
 else()
     list(APPEND hal_def_list HAL_ADC_RESOLUTION_CMAKE=HAL_ADC_RESOLUTION_NOT_SET)
 endif()
diff --git a/manifest.json b/manifest.json
index 7c1c5261f..fffababae 100644
--- a/manifest.json
+++ b/manifest.json
@@ -1,54784 +1,7 @@
 {
-    "sdk-version": "2.6.0",
+    "sdk-version": "2.7.0",
     "display-name": "mikroSDK",
     "description": "MikroSDK 2.0 is an embedded software development framework designed to simplify and accelerate application development on Mikroe hardware platform, specifically for Click Boards and other extension board drivers, on a broad range of microcontroller vendors and architectures. It includes peripheral libraries and drivers, middleware, board support, and application layer libraries among others.",
     "icon": "images/icon-mikroSDK.png",
-    "manifest-version": "1.0.6",
-    "supported-families": [
-        "STM32",
-        "PIC18",
-        "PIC32MZ",
-        "PIC32MX",
-        "Kinetis K Series",
-        "Kinetis V Series",
-        "Tiva"
-    ],
-    "boards": [
-        {
-            "display-name": "Fusion for ARM v8",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "image-path": "images/board-fusion-for-arm-v8.png",
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_FUSION_FOR_ARM_V8"
-            },
-            "has-mcu-card": true,
-            "default-card": "MCU CARD for STM32 STM32F407ZG",
-            "mcu-card-generation-id": "8th-generation",
-            "supported-families": [
-                "STM32",
-                "Kinetis K Series",
-                "Kinetis V Series",
-                "Tiva"
-            ],
-            "mikrobus-sockets": 5,
-            "target-vendors": [
-                "STMicrocontrollers",
-                "NXP",
-                "Texas Instruments"
-            ],
-            "order": 8,
-            "tft-socket": true,
-            "description": "Fusion for ARM v8 offers universal support for Cortex M0, M3, M4, and M7 Microcontrollers on one board. The development board is equipped with a wide range of superior features that allow more complex projects to be created flawlessly."
-        },
-        {
-            "display-name": "Fusion for STM32 v8",
-            "image-path": "images/board-fusion-for-stm32-v8.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_FUSION_FOR_STM32_V8"
-            },
-            "has-mcu-card": true,
-            "default-card": "MCU CARD for STM32 STM32F407ZG",
-            "mcu-card-generation-id": "8th-generation",
-            "supported-families": [
-                "STM32"
-            ],
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "order": 8,
-            "mikrobus-sockets": 5,
-            "tft-socket": true,
-            "description": "Fusion for STM32 v8 offers support for Cortex M0, M3, M4, and M7 Microcontrollers on the board. FUSION development boards are ideal for rapid prototyping with everything that engineers might need for their project development, with new world standards."
-        },
-        {
-            "display-name": "Fusion for KINETIS v8",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "image-path": "images/board-fusion-for-kinetis-v8.png",
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_FUSION_FOR_KINETIS_V8"
-            },
-            "has-mcu-card": true,
-            "default-card": "MCU CARD for Kinetis MK64FN1M0VDC12",
-            "mcu-card-generation-id": "8th-generation",
-            "supported-families": [
-                "Kinetis K Series",
-                "Kinetis V Series"
-            ],
-            "mikrobus-sockets": 5,
-            "target-vendors": [
-                "NXP"
-            ],
-            "order": 8,
-            "tft-socket": true,
-            "description": "Fusion for Kinetis v8 offers support for Cortex M4, M4DSP and M7 Microcontrollers on the board. FUSION development boards are ideal for rapid prototyping with everything that engineers might need for their project development, with new world standards."
-        },
-        {
-            "display-name": "Fusion for TIVA v8",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "image-path": "images/board-fusion-for-tiva-v8.png",
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_FUSION_FOR_TIVA_V8"
-            },
-            "has-mcu-card": true,
-            "default-card": "MCU CARD for TIVA TM4C129XNCZAD",
-            "mcu-card-generation-id": "8th-generation",
-            "supported-families": [
-                "Tiva"
-            ],
-            "mikrobus-sockets": 5,
-            "target-vendors": [
-                "Texas Instruments"
-            ],
-            "order": 8,
-            "tft-socket": true,
-            "description": "Fusion for TIVA v8 offers support for Cortex M4 Microcontrollers on the board. FUSION development boards are ideal for rapid prototyping with everything that engineers might need for their project development, with new world standards."
-        },
-        {
-            "display-name": "EasyMX PRO v7 for TIVA",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "image-path": "images/board-easymx-pro-v7-for-tiva.png",
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_EASYMX_PRO_V7_FOR_TIVA"
-            },
-            "has-mcu-card": true,
-            "default-card": "EasyMx PRO v7 for Tiva MCU card with TM4C129XNCZAD",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "Tiva"
-            ],
-            "mikrobus-sockets": 2,
-            "target-vendors": [
-                "Texas Instruments"
-            ],
-            "order": 7,
-            "tft-socket": true,
-            "description": "Full-featured development board for TI`s Tiva C Series ARM Cortex-M4 microntrollers. It contains many on-board modules necessary for developing a variety of applications, including multimedia, Ethernet, USB, CAN and other."
-        },
-        {
-            "display-name": "Mikromedia 3 for STM32F2 CAPACITIVE",
-            "image-path": "images/mikromedia-3-for-stm32-capacitive.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F207VG|100|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "resolution": {
-                "height": "240",
-                "width": "320"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "order": 8,
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA3FORSTM32F2CAPACITIVE",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "240",
-                "MSDK_TFT_WIDTH": "320",
-                "MSDK_SHIELD": "shield_mikromedia_v8_3"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &MIKROMEDIA_3_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X46_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 3 for STM32 CAPACITIVE is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 3 for STM32F4 CAPACITIVE",
-            "image-path": "images/mikromedia-3-for-stm32-capacitive.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F407VG|100|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "resolution": {
-                "height": "240",
-                "width": "320"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "order": 8,
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA3FORSTM32F4CAPACITIVE",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "240",
-                "MSDK_TFT_WIDTH": "320",
-                "MSDK_SHIELD": "shield_mikromedia_v8_3"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &MIKROMEDIA_3_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X46_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 3 for STM32 CAPACITIVE is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 3 for STM32F2 CAPACITIVE FPI frame",
-            "image-path": "images/mikromedia-3-capacitive-fpi-frame.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F207VG|100|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "240",
-                "width": "320"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA3FORSTM32F2CAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "240",
-                "MSDK_TFT_WIDTH": "320"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &MIKROMEDIA_3_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X46_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 3 for STM32F4 CAPACITIVE FPI with frame is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 3 for STM32F4 CAPACITIVE FPI frame",
-            "image-path": "images/mikromedia-3-capacitive-fpi-frame.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F407VG|100|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "240",
-                "width": "320"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA3FORSTM32F4CAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "240",
-                "MSDK_TFT_WIDTH": "320"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &MIKROMEDIA_3_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X46_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 3 for STM32F4 CAPACITIVE FPI with frame is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 3 for STM32F2 CAPACITIVE FPI bezel",
-            "image-path": "images/mikromedia-3-capacitive-fpi-bezel.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F207VG|100|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "resolution": {
-                "height": "240",
-                "width": "320"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "order": 8,
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA3FORSTM32F2CAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "240",
-                "MSDK_TFT_WIDTH": "320"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &MIKROMEDIA_3_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X46_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 3 for STM32F4 CAPACITIVE FPI with bezel is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 3 for STM32F4 CAPACITIVE FPI bezel",
-            "image-path": "images/mikromedia-3-capacitive-fpi-bezel.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F407VG|100|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "resolution": {
-                "height": "240",
-                "width": "320"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "order": 8,
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA3FORSTM32F4CAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "240",
-                "MSDK_TFT_WIDTH": "320"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &MIKROMEDIA_3_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X46_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 3 for STM32F4 CAPACITIVE FPI with bezel is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 4 for STM32F4 CAPACITIVE",
-            "image-path": "images/mikromedia-4-for-stm32-capacitive.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F407ZG|144|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "272",
-                "width": "480"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA4FORSTM32F4CAPACITIVE",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "272",
-                "MSDK_TFT_WIDTH": "480",
-                "MSDK_SHIELD": "shield_mikromedia_v8_4"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_4_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X16_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_0;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 4 for STM32 CAPACITIVE is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 4 for STM32F2 CAPACITIVE FPI frame",
-            "image-path": "images/mikromedia-4-capacitive-fpi-frame.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F207VG|100|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "272",
-                "width": "480"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA4FORSTM32F2CAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "272",
-                "MSDK_TFT_WIDTH": "480"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_4_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X16_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_0;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 4 for STM32F2 CAPACITIVE FPI with frame is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 4 for STM32F4 CAPACITIVE FPI frame",
-            "image-path": "images/mikromedia-4-capacitive-fpi-frame.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F407VG|100|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "272",
-                "width": "480"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA4FORSTM32F4CAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "272",
-                "MSDK_TFT_WIDTH": "480"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_4_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X16_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_0;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 4 for STM32F4 CAPACITIVE FPI with frame is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 4 for STM32F2 CAPACITIVE FPI bezel",
-            "image-path": "images/mikromedia-4-capacitive-fpi-bezel.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F207VG|100|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "272",
-                "width": "480"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA4FORSTM32F2CAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "272",
-                "MSDK_TFT_WIDTH": "480"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_4_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X16_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 4 for STM32F2 CAPACITIVE FPI with bezel is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 4 for STM32F4 CAPACITIVE FPI bezel",
-            "image-path": "images/mikromedia-4-capacitive-fpi-bezel.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F407VG|100|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "272",
-                "width": "480"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA4FORSTM32F4CAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "272",
-                "MSDK_TFT_WIDTH": "480"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_4_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X16_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 4 for STM32F4 CAPACITIVE FPI with bezel is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 4 for STM32F7 CAPACITIVE",
-            "image-path": "images/mikromedia-4-for-stm32-capacitive.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F746ZG|144|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "272",
-                "width": "480"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA4FORSTM32F7CAPACITIVE",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "272",
-                "MSDK_TFT_WIDTH": "480",
-                "MSDK_SHIELD": "shield_mikromedia_v8_4"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_4_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X16_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_0;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 4 for STM32 CAPACITIVE is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia Plus for STM32",
-            "image-path": "images/mikromedia-plus-for-stm32.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F407ZG|144|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "272",
-                "width": "480"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIAPLUSFORSTM32",
-                "MSDK_TFT_TP": "__TP_STMPE811__",
-                "MSDK_TFT_TYPE": "__TFT_RESISTIVE__",
-                "MSDK_TFT_HEIGHT": "272",
-                "MSDK_TFT_WIDTH": "480",
-                "MSDK_SHIELD": "shield_mikromedia_plus_stm32"
-            },
-            "init-code": "#include \"stmpe811.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic stmpe811_t stmpe811;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    stmpe811_cfg_t stmpe811_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_4_RESISTIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    stmpe811_cfg_setup( &stmpe811_cfg );\n    STMPE811_MAP_PINS( stmpe811_cfg );\n    stmpe811_init( &stmpe811, &stmpe811_cfg, &tp_interface );\n    stmpe811_default_cfg( &stmpe811 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &stmpe811 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia Plus for STM32 is not limited to multimedia-based applications only. USB, Ethernet and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia Plus for STM32F7",
-            "image-path": "images/mikromedia-plus-for-stm32.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F746ZG|144|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "272",
-                "width": "480"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIAPLUSFORSTM32F7",
-                "MSDK_TFT_TP": "__TP_STMPE811__",
-                "MSDK_TFT_TYPE": "__TFT_RESISTIVE__",
-                "MSDK_TFT_HEIGHT": "272",
-                "MSDK_TFT_WIDTH": "480",
-                "MSDK_SHIELD": "shield_mikromedia_plus_stm32"
-            },
-            "init-code": "#include \"stmpe811.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic stmpe811_t stmpe811;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    stmpe811_cfg_t stmpe811_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_4_RESISTIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    stmpe811_cfg_setup( &stmpe811_cfg );\n    STMPE811_MAP_PINS( stmpe811_cfg );\n    stmpe811_init( &stmpe811, &stmpe811_cfg, &tp_interface );\n    stmpe811_default_cfg( &stmpe811 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &stmpe811 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia Plus for STM32F7 is not limited to multimedia-based applications only. USB, Ethernet and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 5 for STM32F4 CAPACITIVE",
-            "image-path": "images/mikromedia-5-for-stm32-capacitive.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F407ZG|144|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA5FORSTM32F4CAPACITIVE",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "480",
-                "MSDK_TFT_WIDTH": "800",
-                "MSDK_SHIELD": "shield_mikromedia_v8_5"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_5_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X06_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 5 for STM32 CAPACITIVE is not limited to multimedia-based applications only. USB, Ethernet, WiFi and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, RTC, and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 5 for STM32F7 CAPACITIVE",
-            "image-path": "images/mikromedia-5-for-stm32-capacitive.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F746ZG|144|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA5FORSTM32F7CAPACITIVE",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "480",
-                "MSDK_TFT_WIDTH": "800",
-                "MSDK_SHIELD": "shield_mikromedia_v8_5"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_5_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X06_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 5 for STM32F7 CAPACITIVE is not limited to multimedia-based applications only. USB, Ethernet, WiFi and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, RTC, and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 5 for STM32F4 CAPACITIVE FPI frame",
-            "image-path": "images/mikromedia-5-capacitive-fpi-frame.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F407ZG|144|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA5FORSTM32F4CAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "480",
-                "MSDK_TFT_WIDTH": "800"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_5_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X06_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 5 for STM32F4 CAPACITIVE FPI with frame is not limited to multimedia-based applications only. USB, WiFi and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, RTC, expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 5 for STM32F7 CAPACITIVE FPI frame",
-            "image-path": "images/mikromedia-5-capacitive-fpi-frame.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F746ZG|144|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA5FORSTM32F7CAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "480",
-                "MSDK_TFT_WIDTH": "800"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_5_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X06_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 5 for STM32F7 CAPACITIVE FPI with frame is not limited to multimedia-based applications only. USB, WiFi and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, RTC, expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 5 for STM32F4 CAPACITIVE FPI bezel",
-            "image-path": "images/mikromedia-5-capacitive-fpi-bezel.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F407ZG|144|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA5FORSTM32F4CAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "480",
-                "MSDK_TFT_WIDTH": "800"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_5_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X06_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 5 for STM32F4 CAPACITIVE FPI with bezel is not limited to multimedia-based applications only. USB, WiFi and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, RTC, expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 5 for STM32F7 CAPACITIVE FPI bezel",
-            "image-path": "images/mikromedia-5-capacitive-fpi-bezel.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F746ZG|144|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA5FORSTM32F7CAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "480",
-                "MSDK_TFT_WIDTH": "800"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_5_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X06_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 5 for STM32F7 CAPACITIVE FPI with bezel is not limited to multimedia-based applications only. USB, WiFi and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, RTC, expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 7 for STM32F4",
-            "image-path": "images/mikromedia-7-for-stm32.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F407ZG|144|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA7FORSTM32F4",
-                "MSDK_TFT_TP": "__TP_STMPE811__",
-                "MSDK_TFT_TYPE": "__TFT_RESISTIVE__",
-                "MSDK_TFT_HEIGHT": "480",
-                "MSDK_TFT_WIDTH": "800",
-                "MSDK_SHIELD": "shield_mikromedia_7_stm32"
-            },
-            "init-code": "#include \"stmpe811.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic stmpe811_t stmpe811;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    stmpe811_cfg_t stmpe811_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_7_RESISTIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    stmpe811_cfg_setup( &stmpe811_cfg );\n    STMPE811_MAP_PINS( stmpe811_cfg );\n    stmpe811_init( &stmpe811, &stmpe811_cfg, &tp_interface );\n    stmpe811_default_cfg( &stmpe811 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &stmpe811 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 7 for STM32F4 is not limited to multimedia-based applications only. USB, Ethernet, WiFi and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, RTC, and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 7 for STM32F7",
-            "image-path": "images/mikromedia-7-for-stm32.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F746ZG|144|Tx",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA7FORSTM32F7",
-                "MSDK_TFT_TP": "__TP_STMPE811__",
-                "MSDK_TFT_TYPE": "__TFT_RESISTIVE__",
-                "MSDK_TFT_HEIGHT": "480",
-                "MSDK_TFT_WIDTH": "800",
-                "MSDK_SHIELD": "shield_mikromedia_7_stm32"
-            },
-            "init-code": "#include \"stmpe811.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic stmpe811_t stmpe811;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    stmpe811_cfg_t stmpe811_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_7_RESISTIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    stmpe811_cfg_setup( &stmpe811_cfg );\n    STMPE811_MAP_PINS( stmpe811_cfg );\n    stmpe811_init( &stmpe811, &stmpe811_cfg, &tp_interface );\n    stmpe811_default_cfg( &stmpe811 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &stmpe811 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 7 for STM32F7 is not limited to multimedia-based applications only. USB, Ethernet, WiFi and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, RTC, and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 7 CAPACITIVE",
-            "image-path": "images/mikromedia-7-capacitive.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "minimum-required-pin-count": "144",
-            "has-mcu-card": true,
-            "mcu-card-generation-id": "8th-generation",
-            "supported-families": [
-                "STM32",
-                "PIC32MZ",
-                "Kinetis K Series",
-                "Kinetis V Series",
-                "Tiva"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "target-vendors": [
-                "STMicrocontrollers",
-                "Microchip",
-                "NXP",
-                "Texas Instruments"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA7CAPACITIVE",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "480",
-                "MSDK_TFT_WIDTH": "800",
-                "MSDK_SHIELD": "shield_mikromedia_v8_7"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_7_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X26_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 7 CAPACITIVE is not limited to multimedia-based applications only. USB, Ethernet, WiFi and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, RTC, and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 7 CAPACITIVE FPI frame",
-            "image-path": "images/mikromedia-7-capacitive-fpi-frame.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "minimum-required-pin-count": "144",
-            "has-mcu-card": true,
-            "mcu-card-generation-id": "8th-generation",
-            "supported-families": [
-                "STM32",
-                "PIC32MZ",
-                "Kinetis K Series",
-                "Kinetis V Series",
-                "Tiva"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "target-vendors": [
-                "STMicrocontrollers",
-                "Microchip",
-                "NXP",
-                "Texas Instruments"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA7CAPACITIVE",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "480",
-                "MSDK_TFT_WIDTH": "800",
-                "MSDK_SHIELD": "shield_mikromedia_v8_7"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_7_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X26_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 7 CAPACITIVE FPI with frame is not limited to multimedia-based applications only. USB, Ethernet, WiFi and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, RTC, and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 7 CAPACITIVE FPI bezel",
-            "image-path": "images/mikromedia-7-capacitive-fpi-bezel.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "minimum-required-pin-count": "144",
-            "has-mcu-card": true,
-            "mcu-card-generation-id": "8th-generation",
-            "supported-families": [
-                "STM32",
-                "PIC32MZ",
-                "Kinetis K Series",
-                "Kinetis V Series",
-                "Tiva"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "target-vendors": [
-                "STMicrocontrollers",
-                "Microchip",
-                "NXP",
-                "Texas Instruments"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA7CAPACITIVE",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "480",
-                "MSDK_TFT_WIDTH": "800",
-                "MSDK_SHIELD": "shield_mikromedia_v8_7"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_7_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X26_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 7 CAPACITIVE FPI with bezel is not limited to multimedia-based applications only. USB, Ethernet, WiFi and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, RTC, and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "UNI CLICKER",
-            "image-path": "images/clicker-uni.png",
-            "category": "Starter boards",
-            "vendor": "mikroE",
-            "has-mcu-card": true,
-            "mcu-card-generation-id": "8th-generation",
-            "supported-families": [
-                "STM32",
-                "PIC18",
-                "PIC32MX",
-                "PIC32MZ",
-                "Kinetis K Series",
-                "Kinetis V Series",
-                "Tiva"
-            ],
-            "order": 8,
-            "target-vendors": [
-                "STMicrocontrollers",
-                "Microchip",
-                "NXP",
-                "Texas Instruments"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "UNI_CLICKER"
-            },
-            "mikrobus-sockets": 4,
-            "tft-socket": false,
-            "description": "Featuring a MCU Card socket, four mikroBUS sockets, power management, and more, this board represents a perfect solution for rapid development of the most diverse applications."
-        },
-        {
-            "display-name": "EasyPIC v8",
-            "image-path": "images/board-easypic-v8.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "default-device-id": "PIC18F47K42|40|DIP40",
-            "supported-families": [
-                "PIC18"
-            ],
-            "target-vendors": [
-                "Microchip"
-            ],
-            "suported-packages": [
-                "DIP40",
-                "DIP28",
-                "DIP20",
-                "DIP18",
-                "DIP14",
-                "DIP8"
-            ],
-            "order": 8,
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_EASYPIC_V8"
-            },
-            "mikrobus-sockets": 5,
-            "tft-socket": false,
-            "description": "EasyPIC v8 covering a wide range of 8-bit PIC MCUs, from the smallest PIC MCU devices with only 8 pins, all the way up to 40-pin \"giants\". Board comes with PIC18F47K42 and 8MHz Crystal oscillator."
-        },
-        {
-            "display-name": "EasyPIC PRO v8",
-            "image-path": "images/board-easypic-pro-v8.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "has-mcu-card": true,
-            "default-card": "MCU CARD for PIC PIC18F97J94",
-            "mcu-card-generation-id": "8th-generation",
-            "supported-families": [
-                "PIC18"
-            ],
-            "target-vendors": [
-                "Microchip"
-            ],
-            "order": 8,
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_EASYPIC_PRO_V8"
-            },
-            "mikrobus-sockets": 5,
-            "tft-socket": true,
-            "description": "EasyPIC PRO v8 offers universal support for Microchip 8bit Microcontrollers on one board. The development board is equipped with a wide range of superior features that allow more complex projects to be created flawlessly."
-        },
-        {
-            "display-name": "EasyPIC v7",
-            "image-path": "images/board-easypic-v7.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "default-device-id": "PIC18F45K22|40|DIP40",
-            "supported-families": [
-                "PIC18"
-            ],
-            "target-vendors": [
-                "Microchip"
-            ],
-            "suported-packages": [
-                "DIP40",
-                "DIP28",
-                "DIP20",
-                "DIP18",
-                "DIP14",
-                "DIP8"
-            ],
-            "order": 7,
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_EASYPIC_V7"
-            },
-            "mikrobus-sockets": 2,
-            "tft-socket": false,
-            "description": "EasyPIC v7 is top selling PIC Development Board for 370+ Microchip PIC MCUs in DIP packaging. It features USB 2.0 programmer/debugger and over 17 essential modules necessary in development. Board comes with PIC18F45K22."
-        },
-        {
-            "display-name": "EasyPIC v7a",
-            "image-path": "images/board-easypic-v7a.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "default-device-id": "PIC18F45K22|40|DIP40",
-            "supported-families": [
-                "PIC18"
-            ],
-            "target-vendors": [
-                "Microchip"
-            ],
-            "suported-packages": [
-                "DIP40",
-                "DIP28",
-                "DIP20",
-                "DIP18",
-                "DIP14",
-                "DIP8"
-            ],
-            "order": 7,
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_EASYPIC_V7"
-            },
-            "mikrobus-sockets": 2,
-            "tft-socket": false,
-            "description": "Full-featured development board for high pin-count 8-bit PIC microcontrollers, supported by a powerful CODEGRIP Suite. It contains many on-board modules necessary for the development variety of applications, including graphics, Ethernet, USB, and other."
-        },
-        {
-            "display-name": "EasyPIC PRO v7",
-            "image-path": "images/board-easypic-pro-v7.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "has-mcu-card": true,
-            "default-card": "EasyPIC PRO v7 MCUcard with PIC18F87K22",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "PIC18"
-            ],
-            "target-vendors": [
-                "Microchip"
-            ],
-            "order": 7,
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_EASYPIC_PRO_V7"
-            },
-            "mikrobus-sockets": 3,
-            "tft-socket": false,
-            "description": "Full-featured development board for high pin-count 8-bit PIC microntrollers. It contains many on-board modules necessary for rapid development of various applications."
-        },
-        {
-            "display-name": "EasyPIC PRO v7a",
-            "image-path": "images/board-easypic-pro-v7a.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "has-mcu-card": true,
-            "default-card": "EasyPIC PRO v7 MCUcard with PIC18F87K22",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "PIC18"
-            ],
-            "target-vendors": [
-                "Microchip"
-            ],
-            "order": 7,
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_EASYPIC_PRO_V7"
-            },
-            "mikrobus-sockets": 3,
-            "tft-socket": false,
-            "description": "Full-featured development board for high pin-count 8-bit PIC microntrollers. It contains many on-board modules necessary for development variety of applications, including graphics, Ethernet, USB, data logging and other."
-        },
-        {
-            "display-name": "EasyMx PRO v7 for STM32",
-            "image-path": "images/board-easymx-pro-v7-stm32.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_EASYMX_PRO_V7_FOR_STM32"
-            },
-            "has-mcu-card": true,
-            "default-card": "EasyMx PRO v7 for STM32 MCUcard with STM32F107VCT6",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "mikrobus-sockets": 2,
-            "tft-socket": false,
-            "description": "Development board for STM32 ARM Cortex -M0, -M3, M4, M7 devices. It contains many on-board modules necessary for the application development, including multimedia, Ethernet, USB, CAN and other."
-        },
-        {
-            "display-name": "Clicker 2 for STM32",
-            "image-path": "images/clicker-2-for-stm32.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F407VG|100|Tx",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "CLICKER_2_FOR_STM32"
-            },
-            "mikrobus-sockets": 2,
-            "tft-socket": false,
-            "description": "Clicker 2 for STM32 is a compact development kit with two mikroBUS sockets for click board connectivity. You can use it to quickly build your own gadgets with unique functionalities and features. It carries the STM32F407VG, a 32-bit microcontroller."
-        },
-        {
-            "display-name": "Clicker 2 for PIC18FK",
-            "image-path": "images/clicker-2-for-pic18fk.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC18F67K40|64|TQFP",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "PIC18"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "Microchip"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "CLICKER_2_FOR_PIC18FK"
-            },
-            "mikrobus-sockets": 2,
-            "tft-socket": false,
-            "description": "Clicker 2 for PIC18FK is a compact development kit with two mikroBUS sockets for click board connectivity. You can use it to quickly build your own gadgets with unique functionalities and features. It carries the PIC18F67K40, a 8-bit microcontroller."
-        },
-        {
-            "display-name": "Clicker 2 for PIC18FJ",
-            "image-path": "images/clicker-2-for-pic18fj.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC18F87J50|80|TQFP",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "PIC18"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "Microchip"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "CLICKER_2_FOR_PIC18FJ"
-            },
-            "default-cfg": "mcu_config/cfg_clicker_2_for_pic18fj.json",
-            "mikrobus-sockets": 2,
-            "tft-socket": false,
-            "description": "Clicker 2 for PIC18FJ is a compact development kit with two mikroBUS sockets for click board connectivity. You can use it to quickly build your own gadgets with unique functionalities and features. It carries the PIC18F87J50, a 8-bit microcontroller."
-        },
-        {
-            "display-name": "Fusion for PIC32 v8",
-            "image-path": "images/board-fusion-for-pic32-v8.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_FUSION_FOR_PIC32_V8"
-            },
-            "has-mcu-card": true,
-            "default-card": "MCU CARD for PIC32 PIC32MX795F512L",
-            "mcu-card-generation-id": "8th-generation",
-            "supported-families": [
-                "PIC32MZ",
-                "PIC32MX"
-            ],
-            "target-vendors": [
-                "Microchip"
-            ],
-            "order": 8,
-            "mikrobus-sockets": 5,
-            "tft-socket": true,
-            "description": "Fusion for PIC32 v8 offers universal support for PIC32 Microcontrollers on one board. The development board is equipped with a wide range of superior features that allow more complex projects to be created flawlessly."
-        },
-        {
-            "display-name": "EasyPIC Fusion v7",
-            "image-path": "images/board-easypic-fusion-v7.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_EASYPIC_FUSION_V7"
-            },
-            "has-mcu-card": true,
-            "default-card": "EasyPIC FUSION v7 ETH MCUcard with PIC32MX795F512L",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "PIC32MZ",
-                "PIC32MX"
-            ],
-            "target-vendors": [
-                "Microchip"
-            ],
-            "order": 7,
-            "mikrobus-sockets": 2,
-            "tft-socket": true,
-            "description": "EasyPIC Fusion v7 combines support for three different architectures: dsPIC33, PIC24 and PIC32 in a single development board It contains many on-board modules, including multimedia, Ethernet, USB, CAN and other. On-board mikroProg programmer and debugger supports 101 microcontrollers via MCU cards."
-        },
-        {
-            "display-name": "Clicker 4 for STM32",
-            "image-path": "images/clicker-4-for-stm32.png",
-            "category": "Development boards",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F767BI|208|Tx",
-            "mcu-card-generation-id": "8th-generation",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "CLICKER_4_FOR_STM32"
-            },
-            "default-cfg": "",
-            "mikrobus-sockets": 4,
-            "tft-socket": false,
-            "description": "Featuring powerful STM32F767BI MCU, four mikroBUS sockets, additional module pinout connections, power management, and more, this board represents a perfect solution for rapid development of the most diverse applications."
-        },
-        {
-            "display-name": "Generic Board",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "image-path": "images/board-generic.png",
-            "sdk-config": {
-                "BOARD_NAME": "GENERIC_BOARD"
-            },
-            "has-mcu-card": false,
-            "supported-families": [
-                "PIC18",
-                "PIC32MX",
-                "PIC32MZ",
-                "STM32",
-                "Tiva",
-                "Kinetis K Series",
-                "Kinetis V Series"
-            ],
-            "target-vendors": [
-                "Microchip",
-                "STMicrocontrollers",
-                "Texas Instruments",
-                "NXP"
-            ],
-            "description": "This is a generic board definition. It can be combined with any of supported MCUs."
-        },
-        {
-            "display-name": "Curiosity HPC",
-            "category": "Development board",
-            "vendor": "Microchip",
-            "image-path": "images/board-curiosity-hpc.png",
-            "default-device-id": "PIC18F47Q10|40|DIP40",
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_CURIOSITY_HPC"
-            },
-            "has-mcu-card": false,
-            "supported-families": [
-                "PIC18"
-            ],
-            "suported-packages": [
-                "DIP40",
-                "DIP28"
-            ],
-            "target-vendors": [
-                "Microchip"
-            ],
-            "order": 6,
-            "mikrobus-sockets": 2,
-            "tft-socket": false,
-            "description": "Curiosity HPC is the perfect platform to harness the power of modern 8-bit PIC Microcontrollers. Its layout and external connections offer unparalleled access to the Core Independent Peripherals (CIPs) available on many newer 8-bit PIC MCUs. These CIPs enable the user to integrate various system functions onto a single MCU, simplifying the design and keeping system power consumption and BOM cost low."
-        },
-        {
-            "display-name": "Flip and Click PIC32MZ",
-            "image-path": "images/flip-and-click-pic32mz.png",
-            "category": "Starter board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC32MZ2048EFH100|100|TFBGA",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "PIC32MZ"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "Microchip"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "FLIP_AND_CLICK_PIC32MZ"
-            },
-            "default-cfg": "",
-            "mikrobus-sockets": 4,
-            "tft-socket": false,
-            "description": "This two-sided dev board is a beginner-friendly rapid prototyping hardware tool featuring PIC32MZ2048EFH100 MCU, four mikroBUS slots, additional module pinout connections, power management, and more, this board represents a perfect solution for rapid development of the most diverse applications."
-        },
-        {
-            "display-name": "PIC32MX Clicker",
-            "image-path": "images/clicker-pic32mx.png",
-            "category": "Starter board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC32MX534F064H|64|TQFP",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "PIC32MX"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "Microchip"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "PIC32MX_CLICKER"
-            },
-            "default-cfg": "mcu_config/cfg_pic32mx_clicker.json",
-            "mikrobus-sockets": 1,
-            "tft-socket": false,
-            "description": "Featuring PIC32MX534F064H MCU, one mikroBUS socket, additional module pinout connections, power management, and more, this board represents a perfect solution for rapid development of the most diverse applications."
-        },
-        {
-            "display-name": "PIC32MZ Clicker",
-            "image-path": "images/clicker-pic32mz.png",
-            "category": "Starter board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC32MZ1024EFH064|64|TQFP",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "PIC32MZ"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "Microchip"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "PIC32MZ_CLICKER"
-            },
-            "default-cfg": "",
-            "mikrobus-sockets": 1,
-            "tft-socket": false,
-            "description": "Featuring PIC32MZ1024EFH064 MCU, one mikroBUS socket, additional module pinout connections, power management, and more, this board represents a perfect solution for rapid development of the most diverse applications."
-        },
-        {
-            "display-name": "Clicker 2 for PIC32MX",
-            "image-path": "images/clicker-2-for-pic32mx.png",
-            "category": "Starter board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC32MX460F512L|100|TQFP",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "PIC32MX"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "Microchip"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "CLICKER_2_FOR_PIC32MX"
-            },
-            "default-cfg": "",
-            "mikrobus-sockets": 2,
-            "tft-socket": false,
-            "description": "Featuring PIC32MX460F512L MCU, two mikroBUS sockets, additional module pinout connections, power management, and more, this board represents a perfect solution for rapid development of the most diverse applications."
-        },
-        {
-            "display-name": "Clicker 2 for PIC32MZ",
-            "image-path": "images/clicker-2-for-pic32mz.png",
-            "category": "Starter board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC32MZ2048EFH100|100|TQFP",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "PIC32MZ"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "Microchip"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "CLICKER_2_FOR_PIC32MZ"
-            },
-            "default-cfg": "mcu_config/cfg_clicker_2_for_pic32mz.json",
-            "mikrobus-sockets": 2,
-            "tft-socket": false,
-            "description": "Featuring PIC32MZ2048EFH100 MCU, two mikroBUS sockets, additional module pinout connections, power management, and more, this board represents a perfect solution for rapid development of the most diverse applications."
-        },
-        {
-            "display-name": "STM32 M4 Clicker",
-            "image-path": "images/clicker-stm32-m4.png",
-            "category": "Starter board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F415RG|64|Tx",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "STM32_M4_CLICKER"
-            },
-            "mikrobus-sockets": 1,
-            "tft-socket": false,
-            "description": "STM32 M4 clicker is an amazingly compact starter development kit which brings innovative mikroBUS host socket to your favorite microcontroller. Board features all you need to get started: 32-bit STM32F415RG microcontroller, USB connector, two LEDs and push buttons, reset button and headers for interfacing with external electronics."
-        },
-        {
-            "display-name": "Fusion for PIC v8",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "image-path": "images/board-fusion-for-pic-v8.png",
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_FUSION_FOR_PIC_V8"
-            },
-            "has-mcu-card": true,
-            "default-card": "MCU CARD for PIC PIC18F97J94",
-            "mcu-card-generation-id": "8th-generation",
-            "supported-families": [
-                "PIC18",
-                "PIC32MX",
-                "PIC32MZ"
-            ],
-            "mikrobus-sockets": 5,
-            "target-vendors": [
-                "Microchip"
-            ],
-            "order": 8,
-            "tft-socket": true,
-            "description": "Fusion for PIC v8 offers universal support for PIC, dsPIC, PIC24, PIC32 Microcontrollers on one board. The development board is equipped with a wide range of superior features that can ensure more complex projects to be created flawlessly."
-        },
-        {
-            "display-name": "PICPLC16 v7a",
-            "image-path": "images/board-picplc16-v7a.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC18F97J60|100|TQFP",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "PIC18"
-            ],
-            "target-vendors": [
-                "Microchip"
-            ],
-            "order": 7,
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_PICPLC16_V7"
-            },
-            "mikrobus-sockets": 3,
-            "tft-socket": false,
-            "description": "The PICPLC16 v7 is a PLC system used to develop industrial, home and office control devices. The system features a PIC18F97J60 microcontroller and is equipped with 16 relays, 16 optocoupled inputs, Ethernet, LIN, etc."
-        },
-        {
-            "display-name": "Mikromedia 3 for PIC CAPACITIVE",
-            "image-path": "images/mikromedia-3-for-pic-capacitive.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC18F97J94|100|TQFP",
-            "supported-families": [
-                "PIC18"
-            ],
-            "resolution": {
-                "height": "240",
-                "width": "320"
-            },
-            "target-vendors": [
-                "Microchip"
-            ],
-            "order": 8,
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA3FORPICCAPACITIVE",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "240",
-                "MSDK_TFT_WIDTH": "320",
-                "MSDK_SHIELD": "shield_mikromedia_v8_3"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &MIKROMEDIA_3_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X46_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 3 for PIC CAPACITIVE is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 3 for PIC CAPACITIVE FPI frame",
-            "image-path": "images/mikromedia-3-capacitive-fpi-frame.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC18F97J94|100|TQFP",
-            "supported-families": [
-                "PIC18"
-            ],
-            "resolution": {
-                "height": "240",
-                "width": "320"
-            },
-            "target-vendors": [
-                "Microchip"
-            ],
-            "order": 8,
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA3FORPICCAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "240",
-                "MSDK_TFT_WIDTH": "320"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &MIKROMEDIA_3_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X46_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 3 for PIC CAPACITIVE FPI is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 3 for PIC CAPACITIVE FPI bezel",
-            "image-path": "images/mikromedia-3-capacitive-fpi-bezel.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC18F97J94|100|TQFP",
-            "supported-families": [
-                "PIC18"
-            ],
-            "resolution": {
-                "height": "240",
-                "width": "320"
-            },
-            "target-vendors": [
-                "Microchip"
-            ],
-            "order": 8,
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA3FORPICCAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "240",
-                "MSDK_TFT_WIDTH": "320"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &MIKROMEDIA_3_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X46_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 3 for PIC CAPACITIVE FPI is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 3 for PIC32MZ CAPACITIVE",
-            "image-path": "images/mikromedia-3-for-pic32mz-capacitive.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC32MZ2048EFH100|100|TQFP",
-            "supported-families": [
-                "PIC32MZ"
-            ],
-            "resolution": {
-                "height": "240",
-                "width": "320"
-            },
-            "target-vendors": [
-                "Microchip"
-            ],
-            "order": 8,
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA3FORPIC32MZCAPACITIVE",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "240",
-                "MSDK_TFT_WIDTH": "320",
-                "MSDK_SHIELD": "shield_mikromedia_v8_3"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &MIKROMEDIA_3_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X46_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "mcu_config/cfg_mikromedia_3_for_pic32mz_capacitive.json",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 3 for PIC32MZ CAPACITIVE is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 4 for PIC32MZ CAPACITIVE",
-            "image-path": "images/mikromedia-4-for-pic32mz-capacitive.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC32MZ2048EFH144|144|TQFP",
-            "supported-families": [
-                "PIC32MZ"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "272",
-                "width": "480"
-            },
-            "target-vendors": [
-                "Microchip"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA4FORPIC32MZCAPACITIVE",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "272",
-                "MSDK_TFT_WIDTH": "480",
-                "MSDK_SHIELD": "shield_mikromedia_v8_4"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_4_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X16_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_0;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "mcu_config/cfg_mikromedia_4_for_pic32mz_capacitive.json",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 4 for PIC32MZ CAPACITIVE is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 4 for PIC32MZ CAPACITIVE FPI frame",
-            "image-path": "images/mikromedia-4-capacitive-fpi-frame.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC32MZ2048EFH144|144|TQFP",
-            "supported-families": [
-                "PIC32MZ"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "272",
-                "width": "480"
-            },
-            "target-vendors": [
-                "Microchip"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA4FORPIC32MZCAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "272",
-                "MSDK_TFT_WIDTH": "480"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_4_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X16_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_0;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "mcu_config/cfg_mikromedia_4_for_pic32mz_capacitive.json",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 4 for PIC32MZ CAPACITIVE FPI with frame is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 4 for PIC32MZ CAPACITIVE FPI bezel",
-            "image-path": "images/mikromedia-4-capacitive-fpi-bezel.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC32MZ2048EFH144|144|TQFP",
-            "supported-families": [
-                "PIC32MZ"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "272",
-                "width": "480"
-            },
-            "target-vendors": [
-                "Microchip"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA4FORPIC32MZCAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "272",
-                "MSDK_TFT_WIDTH": "480"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_4_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X16_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_0;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "mcu_config/cfg_mikromedia_4_for_pic32mz_capacitive.json",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 4 for PIC32MZ CAPACITIVE FPI with bezel is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 5 for PIC32MZ CAPACITIVE",
-            "image-path": "images/mikromedia-5-for-pic32mz-capacitive.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC32MZ2048EFH144|144|TQFP",
-            "supported-families": [
-                "PIC32MZ"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "target-vendors": [
-                "Microchip"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA5FORPIC32MZCAPACITIVE",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "480",
-                "MSDK_TFT_WIDTH": "800",
-                "MSDK_SHIELD": "shield_mikromedia_v8_5"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_5_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X06_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "mcu_config/cfg_mikromedia_5_for_pic32mz_capacitive.json",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 5 for PIC32MZ CAPACITIVE is not limited to multimedia-based applications only. USB, Ethernet, WiFi and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, RTC, and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 5 for PIC32MZ CAPACITIVE FPI frame",
-            "image-path": "images/mikromedia-5-capacitive-fpi-frame.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC32MZ2048EFH144|144|TQFP",
-            "supported-families": [
-                "PIC32MZ"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "target-vendors": [
-                "Microchip"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA5FORPIC32MZCAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "480",
-                "MSDK_TFT_WIDTH": "800"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_5_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X06_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "mcu_config/cfg_mikromedia_5_for_pic32mz_capacitive.json",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 5 for PIC32MZ CAPACITIVE FPI with frame is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia Plus for PIC32MX7",
-            "image-path": "images/mikromedia-plus-for-pic32mx795f512l.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC32MX795F512L|100|TQFP",
-            "supported-families": [
-                "PIC32MX"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "272",
-                "width": "480"
-            },
-            "target-vendors": [
-                "Microchip"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIAPLUSFORPIC32MX7",
-                "MSDK_TFT_TP": "__TP_STMPE811__",
-                "MSDK_TFT_TYPE": "__TFT_RESISTIVE__",
-                "MSDK_TFT_HEIGHT": "272",
-                "MSDK_TFT_WIDTH": "480"
-            },
-            "init-code": "#include \"stmpe811.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic stmpe811_t stmpe811;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    stmpe811_cfg_t stmpe811_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_4_RESISTIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    stmpe811_cfg_setup( &stmpe811_cfg );\n    STMPE811_MAP_PINS( stmpe811_cfg );\n    stmpe811_init( &stmpe811, &stmpe811_cfg, &tp_interface );\n    stmpe811_default_cfg( &stmpe811 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &stmpe811 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia Plus for PIC32MX7 is not limited to multimedia-based applications only. USB, Ethernet and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "PIC Clicker",
-            "image-path": "images/clicker-pic.png",
-            "category": "Starter board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC18F47J53|44|TQFP",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "PIC18"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "Microchip"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "PIC_CLICKER"
-            },
-            "default-cfg": "",
-            "mikrobus-sockets": 1,
-            "tft-socket": false,
-            "description": "PIC clicker is an amazingly compact starter development kit which brings innovative mikroBU host socket to your favorite microcontroller. Board features PIC18F47J53 microcontroller, USB connector, two LEDs and push buttons, reset button, mikroProg connector and headers for interfacing with external electronics."
-        },
-        {
-            "display-name": "6LoWPAN Clicker",
-            "image-path": "images/clicker-6lowpan.png",
-            "category": "Starter board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "PIC32MX470F512H|64|TQFP",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "PIC32MX"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "Microchip"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "6LOWPAN_CLICKER"
-            },
-            "default-cfg": "",
-            "mikrobus-sockets": 1,
-            "tft-socket": false,
-            "description": "6LoWPAN clicker is a compact development board with a mikroBU socket for Click boards connectivity. It carries Microchip`s PIC32MX470F512H microcontroller."
-        },
-        {
-            "display-name": "Kinetis Clicker",
-            "image-path": "images/clicker-kinetis.png",
-            "category": "Starter board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "MK22FN512VLH12|64|LQFP64",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "Kinetis K Series"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "NXP"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "KINETIS_CLICKER"
-            },
-            "mikrobus-sockets": 1,
-            "tft-socket": false,
-            "description": "Kinetis clicker is an amazingly compact starter development kit which brings click board connectivity an NXP`s Kinetis ARM Cortex-M4 microcontroller. The board features all you need to get started: a low power ARM Cortex-M4 32-bit MK22FN512VLH12 microcontroller, a USB connector, two LEDs and push buttons, reset button and headers for interfacing with external electronics."
-        },
-        {
-            "display-name": "Clicker 2 for Kinetis",
-            "image-path": "images/clicker-2-for-kinetis.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "MK64FN1M0VDC12|121|XFBGA121",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "Kinetis K Series"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "NXP"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "CLICKER_2_FOR_KINETIS"
-            },
-            "mikrobus-sockets": 2,
-            "tft-socket": false,
-            "description": "Clicker 2 for Kinetis is a compact development kit with two mikroBUS sockets for click board connectivity. You can use it to quickly build your own gadgets with unique functionalities and features. It carries the MK64FN1M0VDC12, a 32-bit microcontroller."
-        },
-        {
-            "display-name": "Mikromedia 3 for Kinetis CAPACITIVE",
-            "image-path": "images/mikromedia-3-for-kinetis-capacitive.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "MK64FN1M0VDC12|121|XFBGA121",
-            "supported-families": [
-                "Kinetis K Series"
-            ],
-            "resolution": {
-                "height": "240",
-                "width": "320"
-            },
-            "target-vendors": [
-                "NXP"
-            ],
-            "order": 8,
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA3FORKINETISCAPACITIVE",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "240",
-                "MSDK_TFT_WIDTH": "320",
-                "MSDK_SHIELD": "shield_mikromedia_v8_3"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &MIKROMEDIA_3_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X46_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 3 for Kinetis CAPACITIVE is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 3 for Kinetis CAPACITIVE FPI frame",
-            "image-path": "images/mikromedia-3-capacitive-fpi-frame.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "MK64FN1M0VDC12|121|XFBGA121",
-            "supported-families": [
-                "Kinetis K Series"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "240",
-                "width": "320"
-            },
-            "target-vendors": [
-                "NXP"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA3FORKINETISCAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "240",
-                "MSDK_TFT_WIDTH": "320"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &MIKROMEDIA_3_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X46_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 3 for Kinetis CAPACITIVE FPI with frame is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 3 for Kinetis CAPACITIVE FPI bezel",
-            "image-path": "images/mikromedia-3-capacitive-fpi-bezel.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "MK64FN1M0VDC12|121|XFBGA121",
-            "supported-families": [
-                "Kinetis K Series"
-            ],
-            "resolution": {
-                "height": "240",
-                "width": "320"
-            },
-            "target-vendors": [
-                "NXP"
-            ],
-            "order": 8,
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA3FORKINETISCAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "240",
-                "MSDK_TFT_WIDTH": "320"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &MIKROMEDIA_3_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X46_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 3 for Kinetis CAPACITIVE FPI with bezel is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 4 for Kinetis CAPACITIVE",
-            "image-path": "images/mikromedia-4-for-kinetis-capacitive.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "MK66FX1M0VLQ18|144|LQFP144",
-            "supported-families": [
-                "Kinetis K Series"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "272",
-                "width": "480"
-            },
-            "target-vendors": [
-                "NXP"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA4FORKINETISCAPACITIVE",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "272",
-                "MSDK_TFT_WIDTH": "480",
-                "MSDK_SHIELD": "shield_mikromedia_v8_4"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_4_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X16_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_0;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 4 for Kinetis CAPACITIVE is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 4 for Kinetis CAPACITIVE FPI frame",
-            "image-path": "images/mikromedia-4-capacitive-fpi-frame.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "MK66FX1M0VLQ18|144|LQFP144",
-            "supported-families": [
-                "Kinetis K Series"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "272",
-                "width": "480"
-            },
-            "target-vendors": [
-                "NXP"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA4FORKINETISCAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "272",
-                "MSDK_TFT_WIDTH": "480"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_4_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X16_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_0;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 4 for Kinetis CAPACITIVE FPI with frame is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 4 for Kinetis CAPACITIVE FPI bezel",
-            "image-path": "images/mikromedia-4-capacitive-fpi-bezel.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "MK66FX1M0VLQ18|144|LQFP144",
-            "supported-families": [
-                "Kinetis K Series"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "272",
-                "width": "480"
-            },
-            "target-vendors": [
-                "NXP"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA4FORKINETISCAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "272",
-                "MSDK_TFT_WIDTH": "480"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_4_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X16_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 4 for Kinetis CAPACITIVE FPI with bezel is not limited to multimedia-based applications only. USB, digital motion sensor, battery charging functionality, SD card reader and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 5 for Kinetis CAPACITIVE",
-            "image-path": "images/mikromedia-5-for-kinetis-capacitive.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "MK66FX1M0VLQ18|144|LQFP144",
-            "supported-families": [
-                "Kinetis K Series"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "target-vendors": [
-                "NXP"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA5FORKINETISCAPACITIVE",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "800",
-                "MSDK_TFT_WIDTH": "480",
-                "MSDK_SHIELD": "shield_mikromedia_v8_5"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_5_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X06_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 5 for Kinetis CAPACITIVE is not limited to multimedia-based applications only. USB, Ethernet, WiFi and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, RTC, and much more expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 5 for Kinetis CAPACITIVE FPI frame",
-            "image-path": "images/mikromedia-5-capacitive-fpi-frame.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "MK66FX1M0VLQ18|144|LQFP144",
-            "supported-families": [
-                "Kinetis K Series"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "target-vendors": [
-                "NXP"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA5FORKINETISCAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "800",
-                "MSDK_TFT_WIDTH": "480"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_5_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X06_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 5 for Kinetis CAPACITIVE FPI with frame is not limited to multimedia-based applications only. USB, WiFi and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, RTC, expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Mikromedia 5 for Kinetis CAPACITIVE FPI bezel",
-            "image-path": "images/mikromedia-5-capacitive-fpi-bezel.png",
-            "category": "Smart display",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "MK66FX1M0VLQ18|144|LQFP144",
-            "supported-families": [
-                "Kinetis K Series"
-            ],
-            "order": 8,
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "target-vendors": [
-                "NXP"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "MIKROMEDIA5FORKINETISCAPACITIVEFPI",
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "800",
-                "MSDK_TFT_WIDTH": "480"
-            },
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_5_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X06_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "default-cfg": "",
-            "mikrobus-sockets": 0,
-            "tft-socket": false,
-            "built-in-display": true,
-            "description": "Mikromedia 5 for Kinetis CAPACITIVE FPI with bezel is not limited to multimedia-based applications only. USB, WiFi and RF connectivity options, digital motion sensor, battery charging functionality, piezo-buzzer, SD card reader, RTC, expands its use beyond the multimedia."
-        },
-        {
-            "display-name": "Hexiwear Workstation",
-            "image-path": "images/board-hexiwear-workstation.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "MK64FN1M0VDC12|121|XFBGA121",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "Kinetis K Series"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "NXP"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_HEXIWEAR_WORKSTATION"
-            },
-            "mikrobus-sockets": 4,
-            "tft-socket": false,
-            "description": "While Hexiwear combines style and usability found in high-end consumer devices, with the functionality of sophisticated engineering development platforms, the Hexiwear Workstation offers you the choice of expandability. Equipped with 4 mikroBUS sockets, an onboard programmer and debugger, a microSD card slot, digital temperature sensor, buttons, LEDs and more. Start your IoT adventure today."
-        },
-        {
-            "display-name": "Hexiwear Docking Station",
-            "image-path": "images/board-hexiwear-docking-station.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "MK64FN1M0VDC12|121|XFBGA121",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "Kinetis K Series"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "NXP"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_HEXIWEAR_DOCKING_STATION"
-            },
-            "mikrobus-sockets": 3,
-            "tft-socket": false,
-            "description": "Hexiwear Docking Station is, as its name describes, a connection and expansion board for Hexiwear development platform. This board enables you to add functionality to your system and connect over 1000 Click boards to your Hexiwear device."
-        },
-        {
-            "display-name": "Hexiwear Battery Pack",
-            "image-path": "images/board-hexiwear-battery-pack.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "MK64FN1M0VDC12|121|XFBGA121",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "Kinetis K Series"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "NXP"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_HEXIWEAR_BATTERY_PACK"
-            },
-            "mikrobus-sockets": 1,
-            "tft-socket": false,
-            "description": "Hexiwear Battery Pack will keep your favorite IoT development kit charged. You can add any functionality with the onboard mikroBUS socket. With Click boards add sensors, transceivers, speech recognition modules and more. No more cables and worrying if the battery on it will last the day."
-        },
-        {
-            "display-name": "FlowPaw",
-            "image-path": "images/board-flowpaw.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F407VG|100|Tx",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_FLOWPAW"
-            },
-            "mikrobus-sockets": 4,
-            "tft-socket": false,
-            "description": "FlowPaw is a development board disguised as an electronics toy. Intended to teach children to programming and hardware, the kit comprises a main board, four Click boards, and a graphical programming software called FlowStone STEM."
-        },
-        {
-            "display-name": "Quail Board",
-            "image-path": "images/board-quail.png",
-            "category": "Development board",
-            "vendor": "mikroE",
-            "has-mcu-card": false,
-            "device-id": "STM32F427VI|100|Tx",
-            "mcu-card-generation-id": "7th-generation",
-            "supported-families": [
-                "STM32"
-            ],
-            "order": 7,
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_QUAIL"
-            },
-            "mikrobus-sockets": 4,
-            "tft-socket": false,
-            "description": "Quail is an STM32-powered development solution for building hardware prototypes with click boards and C# managed code. It brings together click boards and Microsofts .NET Micro Framework for embedded devices (NETMF). Write code for your Quail projects in Microsoft Visual Studio (free in the community edition); drivers for individual click boards are provided by the MikroBUS.NET team."
-        },
-        {
-            "display-name": "Sparkfun MicroMod MikroBUS Carrier",
-            "category": "Starter boards",
-            "vendor": "mikroE",
-            "image-path": "images/board-micromod-mikrobus-carrier.png",
-            "sdk-config": {
-                "BOARD_NAME": "BOARD_MICROMOD_MIKROBUS_CARRIER"
-            },
-            "has-mcu-card": true,
-            "default-card": "Sparkfun MicroMod STM32 Processor Board with STM32F405RG",
-            "mcu-card-generation-id": "8th-generation",
-            "supported-families": [
-                "STM32"
-            ],
-            "mikrobus-sockets": 1,
-            "target-vendors": [
-                "STMicrocontrollers"
-            ],
-            "order": 8,
-            "tft-socket": false,
-            "description": "MicroMod is a modular interface ecosystem that connects a microcontroller processor board to various carrier board peripherals. Utilizing the M.2 standard, the MicroMod standard is designed to easily swap out processors on the fly."
-        }
-    ],
-    "extra-boards": [
-        {
-            "display-name": "TFT BOARD 3 CAPACITIVE",
-            "category": "TFT Displays",
-            "vendor": "mikroE",
-            "image-path": "images/tft-board-3-capacitive.png",
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_3_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X46_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "resolution": {
-                "height": "240",
-                "width": "320"
-            },
-            "sdk-config": {
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "240",
-                "MSDK_TFT_WIDTH": "320"
-            },
-            "description": "TFT Board 3 Capacitive is a 3.5 inch display board which features the standardized 2x20-pin display connector. The display board also integrates a capacitive multitouch panel with swipe and zoom gesture support."
-        },
-        {
-            "display-name": "TFT BOARD 3 RESISTIVE",
-            "category": "TFT Displays",
-            "vendor": "mikroE",
-            "image-path": "images/tft-board-3-resistive.png",
-            "init-code": "#include \"stmpe811.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic stmpe811_t stmpe811;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    stmpe811_cfg_t stmpe811_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_3_RESISTIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    stmpe811_cfg_setup( &stmpe811_cfg );\n    STMPE811_MAP_PINS( stmpe811_cfg );\n    stmpe811_init( &stmpe811, &stmpe811_cfg, &tp_interface );\n    stmpe811_default_cfg( &stmpe811 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &stmpe811 );\n}",
-            "resolution": {
-                "height": "240",
-                "width": "320"
-            },
-            "sdk-config": {
-                "MSDK_TFT_TP": "__TP_STMPE811__",
-                "MSDK_TFT_TYPE": "__TFT_RESISTIVE__",
-                "MSDK_TFT_HEIGHT": "240",
-                "MSDK_TFT_WIDTH": "320"
-            },
-            "description": "TFT Board 3 Resistive is a 3.5 inch display board which features the standardized 2x20-pin display connector. The display board also integrates a resistive touch panel."
-        },
-        {
-            "display-name": "TFT BOARD 4 CAPACITIVE",
-            "category": "TFT Displays",
-            "vendor": "mikroE",
-            "image-path": "images/tft-board-4-capacitive.png",
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_4_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X16_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_0;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "resolution": {
-                "height": "272",
-                "width": "480"
-            },
-            "sdk-config": {
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "272",
-                "MSDK_TFT_WIDTH": "480"
-            },
-            "description": "TFT Board 4 Capacitive is a 4.3 inch display board which features the standardized 2x20-pin display connector. The display board also integrates a capacitive multitouch panel with swipe and zoom gesture support."
-        },
-        {
-            "display-name": "TFT BOARD 4 RESISTIVE",
-            "category": "TFT Displays",
-            "vendor": "mikroE",
-            "image-path": "images/tft-board-4-resistive.png",
-            "init-code": "#include \"stmpe811.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic stmpe811_t stmpe811;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    stmpe811_cfg_t stmpe811_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_4_RESISTIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    stmpe811_cfg_setup( &stmpe811_cfg );\n    STMPE811_MAP_PINS( stmpe811_cfg );\n    stmpe811_init( &stmpe811, &stmpe811_cfg, &tp_interface );\n    stmpe811_default_cfg( &stmpe811 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &stmpe811 );\n}",
-            "resolution": {
-                "height": "272",
-                "width": "480"
-            },
-            "sdk-config": {
-                "MSDK_TFT_TP": "__TP_STMPE811__",
-                "MSDK_TFT_TYPE": "__TFT_RESISTIVE__",
-                "MSDK_TFT_HEIGHT": "272",
-                "MSDK_TFT_WIDTH": "480"
-            },
-            "description": "TFT Board 4 Resistive is a 4.3 inch display board which features the standardized 2x20-pin display connector. The display board also integrates a resistive touch panel."
-        },
-        {
-            "display-name": "TFT BOARD 5 CAPACITIVE",
-            "category": "TFT Displays",
-            "vendor": "mikroE",
-            "image-path": "images/tft-board-5-capacitive.png",
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_5_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X06_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "sdk-config": {
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "480",
-                "MSDK_TFT_WIDTH": "800"
-            },
-            "description": "TFT Board 5 Capacitive is a 5 inch display board which features the standardized 2x20-pin display connector. The display board also integrates a capacitive multitouch panel with swipe and zoom gesture support."
-        },
-        {
-            "display-name": "TFT BOARD 5 RESISTIVE",
-            "category": "TFT Displays",
-            "vendor": "mikroE",
-            "image-path": "images/tft-board-5-resistive.png",
-            "init-code": "#include \"stmpe811.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic stmpe811_t stmpe811;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    stmpe811_cfg_t stmpe811_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_5_RESISTIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    stmpe811_cfg_setup( &stmpe811_cfg );\n    STMPE811_MAP_PINS( stmpe811_cfg );\n    stmpe811_init( &stmpe811, &stmpe811_cfg, &tp_interface );\n    stmpe811_default_cfg( &stmpe811 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &stmpe811 );\n}",
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "sdk-config": {
-                "MSDK_TFT_TP": "__TP_STMPE811__",
-                "MSDK_TFT_TYPE": "__TFT_RESISTIVE__",
-                "MSDK_TFT_HEIGHT": "480",
-                "MSDK_TFT_WIDTH": "800"
-            },
-            "description": "TFT Board 5 Resistive is a 5 inch display board which features the standardized 2x20-pin display connector. The display board also integrates a resistive touch panel."
-        },
-        {
-            "display-name": "TFT BOARD 7 CAPACITIVE",
-            "category": "TFT Displays",
-            "vendor": "mikroE",
-            "image-path": "images/tft-board-7-capacitive.png",
-            "init-code": "#include \"ft5xx6.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic ft5xx6_t ft5xx6;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    ft5xx6_cfg_t ft5xx6_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_7_CAPACITIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    ft5xx6_cfg_setup( &ft5xx6_cfg, &FT5X26_CONTROLLER );\n    FT5XX6_MAP_PINS( ft5xx6_cfg );\n    ft5xx6_init( &ft5xx6, &ft5xx6_cfg, &tp_interface );\n    ft5xx6_default_cfg( &ft5xx6 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &ft5xx6 );\n}",
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "sdk-config": {
-                "MSDK_TFT_TP": "__TP_FT5XX6__",
-                "MSDK_TFT_TYPE": "__TFT_CAPACITIVE__",
-                "MSDK_TFT_HEIGHT": "480",
-                "MSDK_TFT_WIDTH": "800"
-            },
-            "description": "TFT Board 7 Capacitive is a 7 inch display board which features the standardized 2x20-pin display connector. The display board also integrates a capacitive multitouch panel with swipe and zoom gesture support."
-        },
-        {
-            "display-name": "TFT BOARD 7 RESISTIVE",
-            "category": "TFT Displays",
-            "vendor": "mikroE",
-            "image-path": "images/tft-board-7-resistive.png",
-            "init-code": "#include \"stmpe811.h\"\n\nstatic gl_driver_t display_driver;\nstatic tp_drv_t tp_interface;\nstatic tp_t tp;\nstatic stmpe811_t stmpe811;\nstatic vtft_t vtft;\n\nvoid board_init()\n{\n    tft8_cfg_t tft_cfg;\n    tp_cfg_t tp_cfg;\n    stmpe811_cfg_t stmpe811_cfg;\n\n    // Initialize TFT display board.\n    TFT8_MAP_PINOUTS(tft_cfg);\n    tft_cfg.board = &TFT_BOARD_7_RESISTIVE;\n    tft8_init(&tft_cfg, &display_driver);\n    tft8_set_backlight(TFT8_MAX_BACKLIGHT);\n\n    // Initialize Graphic library.\n    gl_set_driver(&display_driver);\n\n    // Initialize Touch panel.\n    stmpe811_cfg_setup( &stmpe811_cfg );\n    STMPE811_MAP_PINS( stmpe811_cfg );\n    stmpe811_init( &stmpe811, &stmpe811_cfg, &tp_interface );\n    stmpe811_default_cfg( &stmpe811 );\n\n    //  TP API initialization.\n    tp_cfg_setup( &tp_cfg );\n    tp_cfg.start_pos = TP_ROTATE_180;\n    tp_init( &tp, &tp_cfg, &tp_interface , &stmpe811 );\n}",
-            "resolution": {
-                "height": "480",
-                "width": "800"
-            },
-            "sdk-config": {
-                "MSDK_TFT_TP": "__TP_STMPE811__",
-                "MSDK_TFT_TYPE": "__TFT_RESISTIVE__",
-                "MSDK_TFT_HEIGHT": "480",
-                "MSDK_TFT_WIDTH": "800"
-            },
-            "description": "TFT Board 7 Resistive is a 7 inch display board which features the standardized 2x20-pin display connector. The display board also integrates a resistive touch panel."
-        }
-    ],
-    "mcu-cards": {
-        "8th-generation": [
-            {
-                "display-name": "MCU CARD 3 for STM32 STM32F303RC",
-                "image-path": "images/mcu-card-3-for-stm32.png",
-                "default-cfg": "",
-                "sdk-config": {
-                    "MCU_CARD_NAME": "MCU_CARD_3_FOR_STM32"
-                },
-                "device-id": "STM32F303RC|64|Tx"
-            },
-            {
-                "display-name": "MCU CARD for PIC32 PIC32MX795F512L",
-                "image-path": "images/mcu-card-for-pic32.png",
-                "default-cfg": "",
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-            "sdk-config": {
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-            "sdk-config": {
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-            "sdk-config": {
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-            "sdk-config": {
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-        },
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-            "sdk-config": {
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-            "sdk-config": {
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "device-id": "STM32F100C4|48|Tx",
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-            "family": "STM32",
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-            "pin-count": "48",
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-            "max-speed": "24MHz",
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F100C4",
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
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-        },
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-            "device-id": "STM32F100C6|48|Tx",
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-            "image-path": "images/logo-stm.png",
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-            "max-speed": "24MHz",
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-            "sdk-config": {
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-        },
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-            "device-id": "STM32F100C8|48|Tx",
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-            "max-speed": "24MHz",
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-            "sdk-config": {
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-        },
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-            "family": "STM32",
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-            "sdk-config": {
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "device-id": "STM32F100R4|64|Hx",
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-            "sdk-config": {
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-            "sdk-config": {
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-            }
-        },
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-            }
-        },
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-            "sdk-config": {
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-        },
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F100R8",
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F100RB|64|Hx",
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-            "family": "STM32",
-            "toolchain": [
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-            "max-speed": "24MHz",
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F100RB",
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
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-            "max-speed": "24MHz",
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F100RB",
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F100RC|64|Tx",
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-            "family": "STM32",
-            "toolchain": [
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-            "max-speed": "24MHz",
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F100RC",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F100RD|64|Tx",
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-            "toolchain": [
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-            ],
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-            "image-path": "images/logo-stm.png",
-            "flash-memory": "384KB",
-            "pin-count": "64",
-            "ram-memory": "32KB",
-            "max-speed": "24MHz",
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F100RD",
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F100RE|64|Tx",
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-            "toolchain": [
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-            ],
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-            "image-path": "images/logo-stm.png",
-            "flash-memory": "512KB",
-            "pin-count": "64",
-            "ram-memory": "32KB",
-            "max-speed": "24MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F100RE",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F100V8|100|Tx",
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-            "pin-count": "100",
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-            "max-speed": "24MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F100V8",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F100VB|100|Tx",
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-            "family": "STM32",
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-            "image-path": "images/logo-stm.png",
-            "flash-memory": "128KB",
-            "pin-count": "100",
-            "ram-memory": "8KB",
-            "max-speed": "24MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F100VB",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F100VC|100|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
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-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "256KB",
-            "pin-count": "100",
-            "ram-memory": "24KB",
-            "max-speed": "24MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F100VC",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F100VD|100|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "384KB",
-            "pin-count": "100",
-            "ram-memory": "32KB",
-            "max-speed": "24MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F100VD",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F100VE|100|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "512KB",
-            "pin-count": "100",
-            "ram-memory": "32KB",
-            "max-speed": "24MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F100VE",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F100ZD|144|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "384KB",
-            "pin-count": "144",
-            "ram-memory": "32KB",
-            "max-speed": "24MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F100ZD",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F100ZC|144|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
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-            "flash-memory": "256KB",
-            "pin-count": "144",
-            "ram-memory": "24KB",
-            "max-speed": "24MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F100ZC",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "device-id": "STM32F100ZE|144|Tx",
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-            "family": "STM32",
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-            "flash-memory": "512KB",
-            "pin-count": "144",
-            "ram-memory": "32KB",
-            "max-speed": "24MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F100ZE",
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "device-id": "STM32F101C4|48|Tx",
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-            "family": "STM32",
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-            "image-path": "images/logo-stm.png",
-            "flash-memory": "16KB",
-            "pin-count": "48",
-            "ram-memory": "4KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F101C4",
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "device-id": "STM32F101C6|48|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
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-            "image-path": "images/logo-stm.png",
-            "flash-memory": "32KB",
-            "pin-count": "48",
-            "ram-memory": "6KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F101C6",
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "device-id": "STM32F101C8|48|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
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-            "image-path": "images/logo-stm.png",
-            "flash-memory": "64KB",
-            "pin-count": "48",
-            "ram-memory": "10KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F101C8",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "device-id": "STM32F101C8|48|Ux",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
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-            "image-path": "images/logo-stm.png",
-            "flash-memory": "64KB",
-            "pin-count": "48",
-            "ram-memory": "10KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F101C8",
-                "MSDK_PACKAGE_NAME": "Ux",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "device-id": "STM32F101CB|48|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
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-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "128KB",
-            "pin-count": "48",
-            "ram-memory": "16KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F101CB",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "device-id": "STM32F101CB|48|Ux",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
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-            "image-path": "images/logo-stm.png",
-            "flash-memory": "128KB",
-            "pin-count": "48",
-            "ram-memory": "16KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101CB",
-                "MSDK_PACKAGE_NAME": "Ux",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101R4|64|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "16KB",
-            "pin-count": "64",
-            "ram-memory": "4KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F101R4",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101R6|64|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "32KB",
-            "pin-count": "64",
-            "ram-memory": "6KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101R6",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101R8|64|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "64KB",
-            "pin-count": "64",
-            "ram-memory": "10KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F101R8",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101RB|64|Hx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "128KB",
-            "pin-count": "64",
-            "ram-memory": "6KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101RB",
-                "MSDK_PACKAGE_NAME": "Hx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101RB|64|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "128KB",
-            "pin-count": "64",
-            "ram-memory": "6KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101RB",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101RC|64|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "256KB",
-            "pin-count": "64",
-            "ram-memory": "32KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101RC",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101RD|64|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "384KB",
-            "pin-count": "64",
-            "ram-memory": "48KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101RD",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101RE|64|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "512KB",
-            "pin-count": "64",
-            "ram-memory": "48KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F101RE",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101RF|64|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "512KB",
-            "pin-count": "64",
-            "ram-memory": "48KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101RF",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101RG|64|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "1024KB",
-            "pin-count": "64",
-            "ram-memory": "80KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101RG",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101T4|36|Ux",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "16KB",
-            "pin-count": "36",
-            "ram-memory": "4KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101T4",
-                "MSDK_PACKAGE_NAME": "Ux",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101T6|36|Ux",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
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-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "32KB",
-            "pin-count": "36",
-            "ram-memory": "6KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101T6",
-                "MSDK_PACKAGE_NAME": "Ux",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101T8|36|Ux",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "64KB",
-            "pin-count": "36",
-            "ram-memory": "10KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101T8",
-                "MSDK_PACKAGE_NAME": "Ux",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101TB|36|Ux",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "128KB",
-            "pin-count": "36",
-            "ram-memory": "16KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101TB",
-                "MSDK_PACKAGE_NAME": "Ux",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101V8|100|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "64KB",
-            "pin-count": "100",
-            "ram-memory": "10KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101V8",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101VB|100|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "128KB",
-            "pin-count": "100",
-            "ram-memory": "16KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101VB",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101VC|100|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "256KB",
-            "pin-count": "100",
-            "ram-memory": "32KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101VC",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101VD|100|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "384KB",
-            "pin-count": "100",
-            "ram-memory": "48KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101VD",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101VE|100|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "512KB",
-            "pin-count": "100",
-            "ram-memory": "48KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101VE",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101VF|100|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "768KB",
-            "pin-count": "100",
-            "ram-memory": "80KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101VF",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101VG|100|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "1024KB",
-            "pin-count": "100",
-            "ram-memory": "80KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101VG",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101ZC|144|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "256KB",
-            "pin-count": "144",
-            "ram-memory": "32KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101ZC",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F101ZD|144|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "384KB",
-            "pin-count": "144",
-            "ram-memory": "48KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F101ZD",
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-        },
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-            "sdk-config": {
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-            "pin-count": "100",
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-            "max-speed": "72MHz",
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-            "sdk-config": {
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "device-id": "STM32F101ZE|144|Tx",
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-            "family": "STM32",
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-            "flash-memory": "512KB",
-            "pin-count": "144",
-            "ram-memory": "48KB",
-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-            "flash-memory": "1024KB",
-            "pin-count": "144",
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-            "max-speed": "36MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-            }
-        },
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-            "family": "STM32",
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-            "flash-memory": "16KB",
-            "pin-count": "48",
-            "ram-memory": "4KB",
-            "max-speed": "48MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F102C4",
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-            }
-        },
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-            "family": "STM32",
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-            "pin-count": "48",
-            "ram-memory": "6KB",
-            "max-speed": "48MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F102C6",
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "vendor": "STMicroelectronics",
-            "family": "STM32",
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-            "image-path": "images/logo-stm.png",
-            "flash-memory": "64KB",
-            "pin-count": "48",
-            "ram-memory": "10KB",
-            "max-speed": "48MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F102C8",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F102CB|48|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
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-            ],
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-            "image-path": "images/logo-stm.png",
-            "flash-memory": "128KB",
-            "pin-count": "48",
-            "ram-memory": "16KB",
-            "max-speed": "48MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F102CB",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F102R4|64|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
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-            "image-path": "images/logo-stm.png",
-            "flash-memory": "16KB",
-            "pin-count": "64",
-            "ram-memory": "4KB",
-            "max-speed": "48MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F102R4",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F102R6|64|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
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-            ],
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-            "image-path": "images/logo-stm.png",
-            "flash-memory": "32KB",
-            "pin-count": "64",
-            "ram-memory": "6KB",
-            "max-speed": "48MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F102R6",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F102R8|64|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
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-            "image-path": "images/logo-stm.png",
-            "flash-memory": "64KB",
-            "pin-count": "64",
-            "ram-memory": "10KB",
-            "max-speed": "48MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F102R8",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F102RB|64|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
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-            ],
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-            "image-path": "images/logo-stm.png",
-            "flash-memory": "128KB",
-            "pin-count": "64",
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-            "max-speed": "48MHz",
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F102RB",
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F103C4|48|Tx",
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-            "family": "STM32",
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-            "image-path": "images/logo-stm.png",
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-            "pin-count": "48",
-            "ram-memory": "6KB",
-            "max-speed": "72MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F103C4",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F103C6|48|Tx",
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-            "image-path": "images/logo-stm.png",
-            "flash-memory": "32KB",
-            "pin-count": "48",
-            "ram-memory": "10KB",
-            "max-speed": "72MHz",
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F103C6",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F103C6|48|Ux",
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-            "family": "STM32",
-            "toolchain": [
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-            ],
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-            "max-speed": "72MHz",
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F103C6",
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "device-id": "STM32F103CB|48|Tx",
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-            "image-path": "images/logo-stm.png",
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F103CB",
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "sdk-config": {
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-            }
-        },
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-            "sdk-config": {
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-            }
-        },
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-            "device-id": "STM32F103R4|64|Hx",
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F103R4",
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "sdk-config": {
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
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-            "max-speed": "72MHz",
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F103R6",
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "device-id": "STM32F103R6|64|Tx",
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F103R6",
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F103R8",
-                "MSDK_PACKAGE_NAME": "Hx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "device-id": "STM32F103R8|64|Tx",
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F103R8",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "device-id": "STM32F103RB|64|Hx",
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F103RB",
-                "MSDK_PACKAGE_NAME": "Hx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F103RB|64|Tx",
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-            "max-speed": "72MHz",
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F103RB",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F103RC|64|Tx",
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-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "256KB",
-            "pin-count": "64",
-            "ram-memory": "48KB",
-            "max-speed": "72MHz",
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-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F103RC",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F103RC|64|Yx",
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-            "toolchain": [
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-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "256KB",
-            "pin-count": "64",
-            "ram-memory": "48KB",
-            "max-speed": "72MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F103RC",
-                "MSDK_PACKAGE_NAME": "Yx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F103RD|64|Tx",
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-            "family": "STM32",
-            "toolchain": [
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-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "384KB",
-            "pin-count": "64",
-            "ram-memory": "64KB",
-            "max-speed": "72MHz",
-            "default-cfg": "",
-            "sdk-config": {
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-                "MEMAKE_MCU_NAME": "STM32F103RD",
-                "MSDK_PACKAGE_NAME": "Tx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F103RD|64|Yx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
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-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
-            "flash-memory": "384KB",
-            "pin-count": "64",
-            "ram-memory": "64KB",
-            "max-speed": "72MHz",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M3",
-                "MEMAKE_MCU_NAME": "STM32F103RD",
-                "MSDK_PACKAGE_NAME": "Yx",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F103RE|64|Tx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
-                "mikroCARM"
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-            "sdk-config": {
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-            "sdk-config": {
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-        },
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-            "sdk-config": {
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-            "sdk-config": {
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-            "sdk-config": {
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-            "sdk-config": {
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-            }
-        },
-        {
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-            "sdk-config": {
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "sdk-config": {
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-            "sdk-config": {
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-        },
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-        },
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-        },
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-            "family": "STM32",
-            "toolchain": [
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-            "sdk-config": {
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-        },
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-            "sdk-config": {
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "device-id": "STM32L162RD|64|Tx",
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-            "family": "STM32",
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-            "image-path": "images/logo-stm.png",
-            "flash-memory": "384KB",
-            "pin-count": "64",
-            "ram-memory": "48KB",
-            "max-speed": "32MHz",
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-            "sdk-config": {
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            "family": "STM32",
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-            "flash-memory": "384KB",
-            "pin-count": "64",
-            "ram-memory": "48KB",
-            "max-speed": "32MHz",
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-            "sdk-config": {
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-            }
-        },
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-            "max-speed": "32MHz",
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-            "sdk-config": {
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-        },
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-        },
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-            "sdk-config": {
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-            }
-        },
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-            "sdk-config": {
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-        },
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-            "sdk-config": {
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-            }
-        },
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-            ],
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-            "sdk-config": {
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-            }
-        },
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-            "sdk-config": {
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-            }
-        },
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-            ],
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-            "sdk-config": {
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
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-            }
-        },
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-            }
-        },
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-            "sdk-config": {
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-            }
-        },
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-            "sdk-config": {
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-            }
-        },
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-            "sdk-config": {
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-            }
-        },
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-            "sdk-config": {
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-            }
-        },
-        {
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-            "sdk-config": {
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
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-            "sdk-config": {
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F205ZG|144|Tx",
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-            "family": "STM32",
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-            ],
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-            "sdk-config": {
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-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "STM32F207IC|176|Hx",
-            "vendor": "STMicroelectronics",
-            "family": "STM32",
-            "toolchain": [
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-            ],
-            "architecture": "ARM Cortex-M3",
-            "image-path": "images/logo-stm.png",
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-            "sdk-config": {
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-            "sdk-config": {
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-            "sdk-config": {
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-        },
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-            "sdk-config": {
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-        },
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-            "sdk-config": {
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-            "sdk-config": {
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-            "sdk-config": {
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-        },
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-            "sdk-config": {
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-        },
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-        },
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-            }
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-            }
-        },
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-            }
-        },
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-            "family": "STM32",
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-            "sdk-config": {
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-        },
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-        },
-        {
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-        },
-        {
-            "device-id": "TM4C129LNCZAD|212|NFBGA",
-            "vendor": "Tiva",
-            "family": "Tiva",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M4",
-            "image-path": "images/logo-ti.png",
-            "flash-memory": "1024",
-            "pin-count": "212",
-            "ram-memory": "256",
-            "max-speed": "120",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M4EF",
-                "MEMAKE_MCU_NAME": "TM4C129LNCZAD",
-                "MSDK_PACKAGE_NAME": "",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "TM4C129XKCZAD|212|NFBGA",
-            "vendor": "Tiva",
-            "family": "Tiva",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M4",
-            "image-path": "images/logo-ti.png",
-            "flash-memory": "512",
-            "pin-count": "212",
-            "ram-memory": "256",
-            "max-speed": "120",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M4EF",
-                "MEMAKE_MCU_NAME": "TM4C129XKCZAD",
-                "MSDK_PACKAGE_NAME": "",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "TM4C1290NCPDT|128|TQFP",
-            "vendor": "Tiva",
-            "family": "Tiva",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M4",
-            "image-path": "images/logo-ti.png",
-            "flash-memory": "1024",
-            "pin-count": "128",
-            "ram-memory": "256",
-            "max-speed": "120",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M4EF",
-                "MEMAKE_MCU_NAME": "TM4C1290NCPDT",
-                "MSDK_PACKAGE_NAME": "",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "TM4C1290NCZAD|212|NFBGA",
-            "vendor": "Tiva",
-            "family": "Tiva",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M4",
-            "image-path": "images/logo-ti.png",
-            "flash-memory": "1024",
-            "pin-count": "212",
-            "ram-memory": "256",
-            "max-speed": "120",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M4EF",
-                "MEMAKE_MCU_NAME": "TM4C1290NCZAD",
-                "MSDK_PACKAGE_NAME": "",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "TM4C1292NCPDT|128|TQFP",
-            "vendor": "Tiva",
-            "family": "Tiva",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M4",
-            "image-path": "images/logo-ti.png",
-            "flash-memory": "1024",
-            "pin-count": "128",
-            "ram-memory": "256",
-            "max-speed": "120",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M4EF",
-                "MEMAKE_MCU_NAME": "TM4C1292NCPDT",
-                "MSDK_PACKAGE_NAME": "",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "TM4C1292NCZAD|212|NFBGA",
-            "vendor": "Tiva",
-            "family": "Tiva",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M4",
-            "image-path": "images/logo-ti.png",
-            "flash-memory": "1024",
-            "pin-count": "212",
-            "ram-memory": "256",
-            "max-speed": "120",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M4EF",
-                "MEMAKE_MCU_NAME": "TM4C1292NCZAD",
-                "MSDK_PACKAGE_NAME": "",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "TM4C1294KCPDT|128|TQFP",
-            "vendor": "Tiva",
-            "family": "Tiva",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M4",
-            "image-path": "images/logo-ti.png",
-            "flash-memory": "512",
-            "pin-count": "128",
-            "ram-memory": "256",
-            "max-speed": "120",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M4EF",
-                "MEMAKE_MCU_NAME": "TM4C1294KCPDT",
-                "MSDK_PACKAGE_NAME": "",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "TM4C1294NCPDT|128|TQFP",
-            "vendor": "Tiva",
-            "family": "Tiva",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M4",
-            "image-path": "images/logo-ti.png",
-            "flash-memory": "1024",
-            "pin-count": "128",
-            "ram-memory": "256",
-            "max-speed": "120",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M4EF",
-                "MEMAKE_MCU_NAME": "TM4C1294NCPDT",
-                "MSDK_PACKAGE_NAME": "",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "TM4C1294NCZAD|212|NFBGA",
-            "vendor": "Tiva",
-            "family": "Tiva",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M4",
-            "image-path": "images/logo-ti.png",
-            "flash-memory": "1024",
-            "pin-count": "212",
-            "ram-memory": "256",
-            "max-speed": "120",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M4EF",
-                "MEMAKE_MCU_NAME": "TM4C1294NCZAD",
-                "MSDK_PACKAGE_NAME": "",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "TM4C1297NCZAD|212|NFBGA",
-            "vendor": "Tiva",
-            "family": "Tiva",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M4",
-            "image-path": "images/logo-ti.png",
-            "flash-memory": "1024",
-            "pin-count": "212",
-            "ram-memory": "256",
-            "max-speed": "120",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M4EF",
-                "MEMAKE_MCU_NAME": "TM4C1297NCZAD",
-                "MSDK_PACKAGE_NAME": "",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "TM4C1299KCZAD|212|NFBGA",
-            "vendor": "Tiva",
-            "family": "Tiva",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M4",
-            "image-path": "images/logo-ti.png",
-            "flash-memory": "512",
-            "pin-count": "212",
-            "ram-memory": "256",
-            "max-speed": "120",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M4EF",
-                "MEMAKE_MCU_NAME": "TM4C1299KCZAD",
-                "MSDK_PACKAGE_NAME": "",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "TM4C1299NCZAD|212|NFBGA",
-            "vendor": "Tiva",
-            "family": "Tiva",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M4",
-            "image-path": "images/logo-ti.png",
-            "flash-memory": "1024",
-            "pin-count": "212",
-            "ram-memory": "256",
-            "max-speed": "120",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M4EF",
-                "MEMAKE_MCU_NAME": "TM4C1299NCZAD",
-                "MSDK_PACKAGE_NAME": "",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        },
-        {
-            "device-id": "TM4C123GH6ZXR|168|NFBGA",
-            "vendor": "Tiva",
-            "family": "Tiva",
-            "toolchain": [
-                "mikroCARM"
-            ],
-            "architecture": "ARM Cortex-M4",
-            "image-path": "images/logo-ti.png",
-            "flash-memory": "256",
-            "pin-count": "168",
-            "ram-memory": "32",
-            "max-speed": "80",
-            "default-cfg": "",
-            "sdk-config": {
-                "MEMAKE_CORE_NAME": "M4EF",
-                "MEMAKE_MCU_NAME": "TM4C123GH6ZXR",
-                "MSDK_PACKAGE_NAME": "",
-                "MSDK_HAL_LOW_LEVEL_TARGET": "mikroe"
-            }
-        }
-    ]
+    "manifest-version": "1.0.7"
 }
diff --git a/platform/conversions/lib/CMakeLists.txt b/platform/conversions/lib/CMakeLists.txt
index c66df9e7b..0722ea746 100644
--- a/platform/conversions/lib/CMakeLists.txt
+++ b/platform/conversions/lib/CMakeLists.txt
@@ -10,13 +10,13 @@ target_link_libraries(lib_platform  PUBLIC
 
 set(conversions_def_list "")
 
-if(${MCU_NAME} MATCHES "^PIC18.*")
+if((${MCU_NAME} MATCHES "^PIC18.*") OR (${MCU_NAME} MATCHES "AT"))
     list(APPEND conversions_def_list __CONVERSIONS_CHIPS_PIC__)
 else()
     list(APPEND conversions_def_list __CONVERSIONS_CHIPS_32BIT__)
 endif()
 
-if((${MCU_NAME} MATCHES "^PIC18.*") OR ((${MCU_NAME} MATCHES "^STM.*") AND (${CORE_NAME} MATCHES "M0")))
+if((${MCU_NAME} MATCHES "^PIC18.*") OR ((${MCU_NAME} MATCHES "^STM.*") AND (${CORE_NAME} MATCHES "M0")) OR (${MCU_NAME} MATCHES "AT") )
     list(APPEND conversions_def_list __CONVERSIONS_SUBSET__)
 else()
     list(APPEND conversions_def_list __CONVERSIONS_SET__)
diff --git a/platform/mikrosdk_version/include/mikrosdk_version.h b/platform/mikrosdk_version/include/mikrosdk_version.h
index dc75ea982..293439b77 100644
--- a/platform/mikrosdk_version/include/mikrosdk_version.h
+++ b/platform/mikrosdk_version/include/mikrosdk_version.h
@@ -60,7 +60,7 @@ extern "C"{
   * @note changes in minor version indicate that there have been
   * significant improvements and/or features added
   */
-#define mikroSDK_MINOR_VERSION 6
+#define mikroSDK_MINOR_VERSION 7
 
 /**
   * @brief mikroSDK_PATCH_VERSION
diff --git a/targets/arm/mikroe/common/CMakeLists.txt b/targets/arm/mikroe/common/CMakeLists.txt
index 498dffbbb..fd703ae85 100644
--- a/targets/arm/mikroe/common/CMakeLists.txt
+++ b/targets/arm/mikroe/common/CMakeLists.txt
@@ -1,8 +1,13 @@
 if(${MCU_NAME} MATCHES "(^STM32(.+)$)")
     set(architecture "STM32")
     set(mcu_header_path ${MCU_NAME}${_MSDK_PACKAGE_NAME_})
-    string(SUBSTRING ${mcu_header_path} 0 11 STRIPED_MCU_HEADER_PATH)
-    set(mcu_header_path ${STRIPED_MCU_HEADER_PATH}${_MSDK_PACKAGE_NAME_})
+    if(${MCU_NAME} MATCHES "(^STM32(.+)_[AX]$)")
+        string(SUBSTRING ${mcu_header_path} 0 13 STRIPED_MCU_HEADER_PATH)
+        set(mcu_header_path ${STRIPED_MCU_HEADER_PATH}${_MSDK_PACKAGE_NAME_})
+    else()
+        string(SUBSTRING ${mcu_header_path} 0 11 STRIPED_MCU_HEADER_PATH)
+        set(mcu_header_path ${STRIPED_MCU_HEADER_PATH}${_MSDK_PACKAGE_NAME_})
+    endif()
 elseif(${MCU_NAME} MATCHES "(^MK(.+)$)")
     set(architecture "NXP")
     set(mcu_header_path ${MCU_NAME})
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L100C6UxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L100C6_AUx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L100C6UxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L100C6_AUx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L100R8TxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L100R8_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L100R8TxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L100R8_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L100RBTxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L100RB_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L100RBTxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L100RB_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151C6TxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151C6_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151C6TxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151C6_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151C6UxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151C6_AUx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151C6UxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151C6_AUx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151C8TxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151C8_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151C8TxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151C8_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151C8UxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151C8_AUx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151C8UxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151C8_AUx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151CBTxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151CB_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151CBTxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151CB_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151CBUxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151CB_AUx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151CBUxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151CB_AUx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151R6HxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151R6_AHx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151R6HxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151R6_AHx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151R6TxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151R6_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151R6TxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151R6_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151R8HxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151R8_AHx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151R8HxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151R8_AHx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151R8TxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151R8_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151R8TxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151R8_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151RBHxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151RB_AHx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151RBHxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151RB_AHx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151RBTxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151RB_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151RBTxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151RB_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151RCTxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151RC_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151RCTxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151RC_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151V8HxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151V8_AHx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151V8HxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151V8_AHx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151V8TxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151V8_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151V8TxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151V8_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VBHxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VB_AHx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VBHxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VB_AHx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VBTxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VB_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VBTxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VB_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VCTxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VC_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VCTxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VC_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VDTxX/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VD_XTx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VDTxX/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VD_XTx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VDYxX/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VD_XYx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VDYxX/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L151VD_XYx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152C6TxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152C6_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152C6TxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152C6_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152C6UxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152C6_AUx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152C6UxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152C6_AUx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152C8TxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152C8_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152C8TxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152C8_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152C8UxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152C8_AUx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152C8UxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152C8_AUx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152CBTxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152CB_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152CBTxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152CB_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152CBUxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152CB_AUx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152CBUxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152CB_AUx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152R6HxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152R6_AHx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152R6HxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152R6_AHx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152R6TxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152R6_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152R6TxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152R6_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152R8HxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152R8_AHx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152R8HxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152R8_AHx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152R8TxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152R8_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152R8TxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152R8_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152RBHxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152RB_AHx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152RBHxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152RB_AHx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152RBTxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152RB_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152RBTxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152RB_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152RCTxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152RC_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152RCTxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152RC_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152V8HxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152V8_AHx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152V8HxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152V8_AHx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152V8TxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152V8_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152V8TxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152V8_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152VBHxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152VB_AHx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152VBHxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152VB_AHx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152VBTxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152VB_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152VBTxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152VB_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152VCTxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152VC_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152VCTxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152VC_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152VDTxX/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152VD_XTx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152VDTxX/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L152VD_XTx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L162RCTxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L162RC_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L162RCTxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L162RC_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L162VCTxA/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L162VC_ATx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L162VCTxA/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L162VC_ATx/mcu_definitions.h
diff --git a/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L162VDYxX/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L162VD_XYx/mcu_definitions.h
similarity index 100%
rename from targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L162VDYxX/mcu_definitions.h
rename to targets/arm/mikroe/common/include/mcu_definitions/STM32/STM32L162VD_XYx/mcu_definitions.h
diff --git a/targets/avr_8bit/mikroe/CMakeLists.txt b/targets/avr_8bit/mikroe/CMakeLists.txt
new file mode 100644
index 000000000..373d033a1
--- /dev/null
+++ b/targets/avr_8bit/mikroe/CMakeLists.txt
@@ -0,0 +1,3 @@
+add_subdirectory(common)
+add_subdirectory(core)
+add_subdirectory(avr)
diff --git a/targets/avr_8bit/mikroe/avr/CMakeLists.txt b/targets/avr_8bit/mikroe/avr/CMakeLists.txt
new file mode 100644
index 000000000..db40819bb
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/CMakeLists.txt
@@ -0,0 +1,29 @@
+# ALL MODULES
+add_subdirectory(src/hal_ll)
+
+# SEPARATE MODULES
+set(module_list "")
+set(module_list_supported "")
+set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer")
+
+if (msdk_adc IN_LIST module_list_supported)
+    add_subdirectory(src/adc)
+endif()
+if (msdk_gpio_in IN_LIST module_list_supported)
+    add_subdirectory(src/gpio)
+endif()
+if (msdk_i2c_master IN_LIST module_list_supported)
+    add_subdirectory(src/i2c)
+endif()
+if (msdk_pwm IN_LIST module_list_supported)
+    add_subdirectory(src/tim)
+endif()
+if (msdk_spi_master IN_LIST module_list_supported)
+    add_subdirectory(src/spi_master)
+endif()
+if (msdk_uart IN_LIST module_list_supported)
+    add_subdirectory(src/uart)
+endif()
+if (msdk_onewire IN_LIST module_list_supported)
+    add_subdirectory(src/one_wire)
+endif()
diff --git a/targets/avr_8bit/mikroe/avr/include/adc/hal_ll_adc.h b/targets/avr_8bit/mikroe/avr/include/adc/hal_ll_adc.h
new file mode 100644
index 000000000..d83119871
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/adc/hal_ll_adc.h
@@ -0,0 +1,213 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_adc.h
+ * @brief This file contains all the functions prototypes for the ADC library.
+ */
+
+#ifndef _HAL_LL_ADC_H_
+#define _HAL_LL_ADC_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_ll_target.h"
+
+
+// TODO Izmeniti po potrebi zbog AVR(8-bit) arhitekture.
+
+
+#define HAL_ADC_6BIT_RES_VAL             0x003FU
+#define HAL_ADC_8BIT_RES_VAL             0x00FFU
+#define HAL_ADC_10BIT_RES_VAL            0x03FFU
+#define HAL_ADC_12BIT_RES_VAL            0x0FFFU
+#define HAL_ADC_14BIT_RES_VAL            0x3FFFU
+#define HAL_ADC_16BIT_RES_VAL            0xFFFFU
+
+/**
+ * @brief ADC low level handle.
+ *
+ * The context for storing low level object handler.
+ * User is not to change these values or unexpected behaviour
+ * may occur.
+ */
+typedef struct
+{
+    handle_t *hal_ll_adc_handle;
+    handle_t *hal_drv_adc_handle;
+    bool init_ll_state;
+} hal_ll_adc_handle_register_t;
+
+/**
+ * ADC VREF.
+ */
+typedef enum
+{
+    HAL_LL_ADC_VREF_EXTERNAL = 0,
+    HAL_LL_ADC_VREF_INTERNAL,
+    HAL_LL_ADC_VREF_DEFAULT = HAL_LL_ADC_VREF_EXTERNAL
+} hal_ll_adc_voltage_reference_t;
+
+/**
+ * ADC resolution.
+ */
+typedef enum
+{
+    HAL_LL_ADC_RESOLUTION_NOT_SET = 0,
+    HAL_LL_ADC_RESOLUTION_6_BIT,     /**< 6  bit resolution */
+    HAL_LL_ADC_RESOLUTION_8_BIT,     /**< 8  bit resolution */
+    HAL_LL_ADC_RESOLUTION_10_BIT,    /**< 10 bit resolution */
+    HAL_LL_ADC_RESOLUTION_12_BIT,    /**< 12 bit resolution */
+    HAL_LL_ADC_RESOLUTION_14_BIT,    /**< 14 bit resolution */
+    HAL_LL_ADC_RESOLUTION_16_BIT,    /**< 16 bit resolution */
+
+    /*!< Default resolution. */
+    HAL_LL_ADC_RESOLUTION_DEFAULT = HAL_LL_ADC_RESOLUTION_CMAKE
+} hal_ll_adc_resolution_t;
+
+/**
+ * @brief  Registers handler for future use.
+ *
+ * Registers low level and hal level handlers
+ * for use with appropriate functions.
+ *
+ * @param[in] *handle HAL context object handle.
+ * @param[in] pin Analog input pin.
+ * @param[in] vref_input Voltage reference source.
+ * @param[in] resolution Analog data resolution.
+ * @param[in] *handle_map HAL layer local handle map.
+ * @param[in] *hal_module_id HAL layer module number.
+
+ * @return hal_ll_err_t Module specific error.
+ *
+ * Returns one of pre-defined error values.
+ * Take into consideration that this is hardware specific.
+ */
+hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id);
+
+/**
+ * @brief  Configures specified module.
+ *
+ * Performs module configuration on the hardware
+ * level.
+ *
+ * @param[in]  *handle HAL context object handle.
+ *
+ * @return  hal_ll_err_t Module specific error.
+ *
+ * Returns one of pre-defined values.
+ * Take into consideration that this is hardware specific.
+ */
+hal_ll_err_t hal_ll_module_configure_adc( handle_t *handle );
+
+/**
+ * @brief  Sets ADC resolution.
+ *
+ * Sets specified ADC resolution for module.
+ * Take into consideration that the module
+ * will be re-initialized on the hardware level.
+ *
+ * @param[in] *handle HAL context object handle.
+ * @param[in] resolution ADC resolution.
+ *
+ * @return hal_ll_err_t Module specific error or success.
+ */
+hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution);
+
+/**
+ * @brief  Sets ADC reference voltage source.
+ *
+ * Registers ADC reference voltage source for specified
+ * object.
+ *
+ * @param[in] *handle HAL context object handle.
+ * @param[in] vref_input ADC reference voltage source.
+ *
+ * @return hal_ll_err_t Module specific error or success.
+ */
+hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input);
+
+/**
+ * @brief  Sets ADC reference voltage value.
+ *
+ * Registers ADC reference voltage value for specified
+ * object.
+ *
+ * @param[in] *handle HAL context object handle.
+ * @param[in] vref_input ADC reference voltage value.
+ *
+ * @return void None.
+ */
+void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value);
+
+/**
+ * @brief Executes data read via ADC module.
+ *
+ * Function shall read raw unsigned analog value.
+ *
+ * @param handle ADC handle.
+ * @param *readDatabuf Data buffer where read data
+ *                     shall be placed.
+ *
+ * @return hal_ll_err_t Module specific error.
+ *
+ * Returns one of pre-defined error values.
+ * Take into consideration that this is hardware specific.
+ */
+hal_ll_err_t hal_ll_adc_read(handle_t *handle, uint16_t *readDatabuf );
+
+/**
+ * @brief  Closes ADC HAL and HAL_LOW_LEVEL context object.
+ *
+ * De-allocates hardware resources for specific driver object and
+ * de-initializes the module on a hardware level.
+ *
+ * @param[in] *handle HAL context object handle.
+ *
+ * @return void None.
+ */
+void hal_ll_adc_close( handle_t *handle );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_ADC_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/include/adc/hal_ll_analog_in_map.h b/targets/avr_8bit/mikroe/avr/include/adc/hal_ll_analog_in_map.h
new file mode 100644
index 000000000..b340b661c
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/adc/hal_ll_analog_in_map.h
@@ -0,0 +1,373 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_analog_in_map.h
+ * @brief Macros used for setting pin analog functionality.
+ */
+
+#ifndef _HAL_LL_ANALOG_IN_MAP_H_
+#define _HAL_LL_ANALOG_IN_MAP_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_ll_pin_names.h"
+
+/*!< @brief Helper macro for getting adequate module index number */
+#define hal_ll_adc_module_num(_module_num) (_module_num - 1)
+
+/*!< @brief Macro defining `weak` attribute */
+#define __weak __attribute__((weak))
+
+enum channel {
+    HAL_LL_ADC_CHANNEL_0 = 0,
+    HAL_LL_ADC_CHANNEL_1,
+    HAL_LL_ADC_CHANNEL_2,
+    HAL_LL_ADC_CHANNEL_3,
+    HAL_LL_ADC_CHANNEL_4,
+    HAL_LL_ADC_CHANNEL_5,
+    HAL_LL_ADC_CHANNEL_6,
+    HAL_LL_ADC_CHANNEL_7,
+    HAL_LL_ADC_CHANNEL_8,
+    HAL_LL_ADC_CHANNEL_9,
+    HAL_LL_ADC_CHANNEL_10,
+    HAL_LL_ADC_CHANNEL_11,
+    HAL_LL_ADC_CHANNEL_12,
+    HAL_LL_ADC_CHANNEL_13,
+    HAL_LL_ADC_CHANNEL_14,
+    HAL_LL_ADC_CHANNEL_15
+};
+
+typedef struct {
+    uint8_t pin;
+    uint8_t module_index;
+    uint8_t channel;
+    uint16_t analog_in_register_addr;
+} hal_ll_adc_pin_map_t;
+
+__weak static const hal_ll_adc_pin_map_t _adc_map[] = {
+    //------------ BEGIN
+    #ifdef ADC0_PF0_CH0
+    {PF0, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_0, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PF1_CH1
+    {PF1, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_1, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PF2_CH2
+    {PF2, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_2, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PF3_CH3
+    {PF3, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_3, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PF4_CH4
+    {PF4, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_4, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PF5_CH5
+    {PF5, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_5, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PF6_CH6
+    {PF6, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_6, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PF7_CH7
+    {PF7, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_7, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PK0_CH8
+    {PK0, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_8, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PK1_CH9
+    {PK1, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_9, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PK2_CH10
+    {PK2, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_10, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PK3_CH11
+    {PK3, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_11, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PK4_CH12
+    {PK4, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_12, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PK5_CH13
+    {PK5, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_13, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PK6_CH14
+    {PK6, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_14, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PK7_CH15
+    {PK7, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_15, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PA0_CH0
+    {PA0, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_0, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PA1_CH1
+    {PA1, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_1, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PA2_CH2
+    {PA2, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_2, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PA3_CH3
+    {PA3, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_3, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PA4_CH4
+    {PA4, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_4, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PA5_CH5
+    {PA5, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_5, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PA6_CH6
+    {PA6, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_6, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PA7_CH7
+    {PA7, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_7, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PC0_CH0
+    {PC0, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_0, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PC1_CH1
+    {PC1, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_1, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PC2_CH2
+    {PC2, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_2, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PC3_CH3
+    {PC3, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_3, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PC4_CH4
+    {PC4, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_4, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PC5_CH5
+    {PC5, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_5, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PE2_CH6
+    {PE2, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_6, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PE3_CH7
+    {PE3, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_7, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB4_CH11
+    {PB4, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_11, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB5_CH12
+    {PB5, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_12, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB6_CH13
+    {PB6, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_13, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PD4_CH8
+    {PD4, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_8, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PD6_CH9
+    {PD6, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_9, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PD7_CH10
+    {PD7, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_10, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB0_CH0
+    {PB0, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_0, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB0_CH8
+    {PB0, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_8, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB1_CH1
+    {PB1, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_1, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB1_CH9
+    {PB1, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_9, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB2_CH10
+    {PB2, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_10, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB2_CH2
+    {PB2, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_2, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB3_CH11
+    {PB3, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_11, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB3_CH3
+    {PB3, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_3, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB4_CH12
+    {PB4, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_12, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB4_CH4
+    {PB4, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_4, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB5_CH13
+    {PB5, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_13, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB5_CH5
+    {PB5, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_5, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB6_CH14
+    {PB6, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_14, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB6_CH6
+    {PB6, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_6, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB7_CH15
+    {PB7, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_15, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB7_CH7
+    {PB7, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_7, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PA0_CH0
+    {PA0, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_0, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB0_CH0
+    {PB0, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_0, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB0_CH8
+    {PB0, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB1_CH1
+    {PB1, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_1, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB1_CH9
+    {PB1, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB2_CH10
+    {PB2, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB2_CH2
+    {PB2, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_2, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB3_CH11
+    {PB3, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB3_CH3
+    {PB3, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_3, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB4_CH12
+    {PB4, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_12, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB4_CH4
+    {PB4, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_4, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB5_CH13
+    {PB5, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_13, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB5_CH5
+    {PB5, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_5, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB6_CH14
+    {PB6, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_14, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB6_CH6
+    {PB6, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_6, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB7_CH15
+    {PB7, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_15, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB7_CH7
+    {PB7, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PD0_CH8
+    {PD0, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_8, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PD1_CH9
+    {PD1, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_9, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PD2_CH10
+    {PD2, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_10, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PD3_CH11
+    {PD3, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_11, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PD4_CH12
+    {PD4, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_12, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PD5_CH13
+    {PD5, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_13, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PD6_CH14
+    {PD6, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_14, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PD7_CH15
+    {PD7, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_15, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB0_CH7
+    {PB0, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_7, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB1_CH8
+    {PB1, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_8, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB2_CH9
+    {PB2, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_9, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB3_CH10
+    {PB3, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_10, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC0_PB7_CH14
+    {PB7, hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_ADC_CHANNEL_14, HAL_LL_ADC0_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB0_CH7
+    {PB0, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_7, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB1_CH8
+    {PB1, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_8, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB2_CH9
+    {PB2, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_9, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB3_CH10
+    {PB3, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_10, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB4_CH11
+    {PB4, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_11, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB5_CH12
+    {PB5, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_12, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB6_CH13
+    {PB6, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_13, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+    #ifdef ADC1_PB7_CH14
+    {PB7, hal_ll_adc_module_num(ADC_MODULE_1), HAL_LL_ADC_CHANNEL_14, HAL_LL_ADC1_BASE_ADDRESS},
+    #endif
+
+    { HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR }
+    //------------ END
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_ANALOG_IN_MAP_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/include/gpio/hal_ll_gpio.h b/targets/avr_8bit/mikroe/avr/include/gpio/hal_ll_gpio.h
new file mode 100644
index 000000000..0e163a158
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/gpio/hal_ll_gpio.h
@@ -0,0 +1,218 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_gpio.h
+ * @brief This file contains all the functions prototypes for the GPIO library.
+ */
+
+#ifndef _HAL_LL_GPIO_H_
+#define _HAL_LL_GPIO_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "hal_ll_gpio_port.h"
+
+/**
+ * @brief Function configures pin.
+ *
+ * Configures pin to digital output or digital input.
+ * Sets only the pin defined by pin mask in
+ * hal_ll_gpio_pin_t structure.
+ *
+ * @param *pin Pin object context.
+ * 			   Configured during this functions process.
+ * @param name Pin name -- PA0, PA1...
+ * @param direction Pin direction.
+ * HAL_LL_GPIO_DIGITAL_INPUT
+ * HAL_LL_GPIO_DIGITAL_OUTPUT
+ *
+ * @return None.
+ */
+void hal_ll_gpio_configure_pin(hal_ll_gpio_pin_t *pin, hal_ll_pin_name_t name, hal_ll_gpio_direction_t direction);
+
+/**
+ * @brief Read pin input.
+ *
+ * Checks pin data input register value and
+ * returns logical state.
+ *
+ * @param *pin Pin object context.
+ * 			   Configured during hal_ll_gpio_configure_pin.
+ *
+ * @return uint8_t Pin logical state.
+ * 1/true -- pin high state
+ * 0/false -- pin low state
+ */
+uint8_t hal_ll_gpio_read_pin_input(hal_ll_gpio_pin_t *pin);
+
+/**
+ * @brief Read pin output.
+ *
+ * Checks pin data output register value and
+ * returns logical state.
+ *
+ * @param *pin Pin object context.
+ * 			   Configured during hal_ll_gpio_configure_pin.
+ *
+ * @return uint8_t Pin logical state.
+ * 1/true -- pin high state -- 1.8V or more detected
+ * 0/false -- pin low state -- 1.8V or less detected
+ */
+uint8_t hal_ll_gpio_read_pin_output(hal_ll_gpio_pin_t *pin);
+
+/**
+ * @brief Writes pin output state.
+ *
+ * Sets single pin logical state.
+ *
+ * @param *pin Pin object context.
+ * 			   Configured during hal_ll_gpio_configure_pin.
+ * @param value Pin logical state.
+ * 1/true -- sets pin high state -- over 1.8V
+ * 0/false -- sets pin low state -- less than 1.8V
+ *
+ * @return None
+ */
+void hal_ll_gpio_write_pin_output(hal_ll_gpio_pin_t *pin, uint8_t value);
+
+/**
+ * @brief Toggles pin logical state.
+ *
+ * Checks current state of pin
+ * and toggles it.
+ *
+ * @param *pin Pin object context.
+ * 			   Configured during hal_ll_gpio_configure_pin.
+ *
+ * @return None
+ */
+void hal_ll_gpio_toggle_pin_output(hal_ll_gpio_pin_t *pin);
+
+/**
+ * @brief Sets pin logical state.
+ *
+ * Sets pin logical state to high.
+ *
+ * @param *pin Pin object context.
+ * 			   Configured during hal_ll_gpio_configure_pin.
+ *
+ * @return None
+ */
+void hal_ll_gpio_set_pin_output(hal_ll_gpio_pin_t *pin);
+
+/**
+ * @brief Sets pin logical state.
+ *
+ * Sets pin logical state to low.
+ *
+ * @param *pin Pin object context.
+ * 			   Configured during hal_ll_gpio_configure_pin.
+ *
+ * @return None
+ */
+void hal_ll_gpio_clear_pin_output(hal_ll_gpio_pin_t *pin);
+
+/**
+ * @brief Configures port.
+ *
+ * Configures port according to specified
+ * direction. Takes into consideration only
+ * pins defined by mask.
+ *
+ * @param *port Port object context.
+ * 				Configured during this functions process.
+ * @param name Port name.
+ * @param mask Port pin mask.
+ * @param direction Port pin direction.
+ * HAL_LL_GPIO_DIGITAL_INPUT
+ * HAL_LL_GPIO_DIGITAL_OUTPUT
+ *
+ * @return None
+ */
+void hal_ll_gpio_configure_port(hal_ll_gpio_port_t *port, hal_ll_port_name_t name, hal_ll_gpio_mask_t mask, hal_ll_gpio_direction_t direction);
+
+/**
+ * @brief Read port input value.
+ *
+ * Checks port data input register value and
+ * returns it.
+ *
+ * @param *port Port object context.
+ * 				Configured during hal_ll_gpio_configure_port.
+ *
+ * @return hal_ll_port_size_t Port input data register value.
+ */
+hal_ll_port_size_t hal_ll_gpio_read_port_input(hal_ll_gpio_port_t *port);
+
+/**
+ * @brief Read port output value.
+ *
+ * Checks port data output register value and
+ * returns it.
+ *
+ * @param *port Port object context.
+ * 				Configured during hal_ll_gpio_configure_port.
+ * @return hal_ll_port_size_t Port output data register value.
+ */
+hal_ll_port_size_t hal_ll_gpio_read_port_output(hal_ll_gpio_port_t *port);
+
+/**
+ * @brief Set port state.
+ *
+ * Sets port output state.
+ * Will take into consideration only
+ * port pins defined by mask in
+ * port object context.
+ *
+ * @param *port Port object context.
+ * 				Configured during hal_ll_gpio_configure_port.
+ *
+ * @return None
+ */
+void hal_ll_gpio_write_port_output(hal_ll_gpio_port_t *port, hal_ll_port_size_t value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_GPIO_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/include/gpio/hal_ll_gpio_constants.h b/targets/avr_8bit/mikroe/avr/include/gpio/hal_ll_gpio_constants.h
new file mode 100644
index 000000000..63b58d0e7
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/gpio/hal_ll_gpio_constants.h
@@ -0,0 +1,60 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_gpio_constants.h
+ * @brief GPIO HAL LL macros.
+ */
+
+#ifndef _HAL_LL_GPIO_CONSTANTS_H_
+#define _HAL_LL_GPIO_CONSTANTS_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#define GPIO_CFG_DIGITAL_INPUT   0
+#define GPIO_CFG_DIGITAL_OUTPUT  1
+#define GPIO_CFG_ANALOG_INPUT    2
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // _HAL_LL_GPIO_CONSTANTS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/include/gpio/hal_ll_gpio_port.h b/targets/avr_8bit/mikroe/avr/include/gpio/hal_ll_gpio_port.h
new file mode 100644
index 000000000..67c9a08e7
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/gpio/hal_ll_gpio_port.h
@@ -0,0 +1,148 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_gpio.h
+ * @brief This file contains all the functions prototypes for the GPIO library.
+ */
+
+#ifndef _HAL_LL_GPIO_PORT_H_
+#define _HAL_LL_GPIO_PORT_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_ll_target.h"
+#include "hal_ll_gpio_constants.h"
+
+/**
+ *  GPIO module registers access structure
+ */
+typedef struct {
+    hal_ll_base_addr_t port_reg_addr;
+    hal_ll_base_addr_t ddr_reg_addr;
+    hal_ll_base_addr_t pin_reg_addr;
+} hal_ll_gpio_base_handle_t;
+
+/**
+ *  Handle and mask types.
+ */
+typedef handle_t hal_ll_gpio_base_t;
+
+/**
+ *  Enum used for pin direction selection.
+ */
+typedef enum {
+    HAL_LL_GPIO_DIGITAL_INPUT = 0,
+    HAL_LL_GPIO_DIGITAL_OUTPUT = 1
+} hal_ll_gpio_direction_t;
+
+/**
+ *  Enum used for pin direction selection.
+ */
+typedef struct hal_ll_gpio_t {
+    hal_ll_gpio_base_t base;
+    hal_ll_gpio_mask_t mask;
+};
+
+/**
+ *  Pin and port data types.
+ */
+typedef struct hal_ll_gpio_t hal_ll_gpio_pin_t;
+typedef struct hal_ll_gpio_t hal_ll_gpio_port_t;
+
+/**
+  * @brief  Get pins port index within a list of available ports
+  * @param  name - desired pin
+  * @return uint8_t value from 0 to PORT_COUNT-1
+  */
+uint8_t hal_ll_gpio_port_index(hal_ll_pin_name_t name);
+
+/**
+  * @brief  Get pin mask of provided pin within proprietery port
+  * @param  name - desired pin
+  * @return uint8_t
+  */
+uint8_t hal_ll_gpio_port_pin_mask(hal_ll_pin_name_t name);
+
+/**
+  * @brief  Get address of port register offsets map
+  * @param  name - desired port
+  * @return uint16_t address of first regsiter
+  */
+uint16_t hal_ll_gpio_port_base_map(hal_ll_port_name_t name);
+
+/**
+  * @brief  Set pin as analog input
+  * @param  port - port base address acquired from hal_gpio_ll_port_base
+  * @param  pin_mask - pin mask acquired from hal_gpio_ll_pin_mask
+  * @return none
+  */
+void hal_ll_gpio_port_analog_input(uint16_t *port, uint8_t pin_mask);
+
+/**
+  * @brief  Set port as analog input
+  * @param  port - port base address acquired from hal_gpio_ll_port_base
+  * @param  name - port index value
+  * @return none
+  */
+void hal_ll_gpio_port_digital_configure_port(hal_ll_gpio_port_t *port, uint8_t name, bool is_input);
+
+/**
+  * @brief  Set pin as digital input
+  * @param  port - port base address acquired from hal_gpio_ll_port_base
+  * @param  pin_mask - pin mask acquired from hal_gpio_ll_pin_mask
+  * @return none
+  */
+void hal_ll_gpio_port_digital_input(uint16_t *port, uint8_t pin_mask);
+
+/**
+  * @brief  Set pin as digital output
+  * @param  port - port base address acquired from hal_gpio_ll_port_base
+  * @param  pin_mask - pin mask acquired from hal_gpio_ll_pin_mask
+  * @return none
+  */
+void hal_ll_gpio_port_digital_output(uint16_t *port, uint8_t pin);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_GPIO_PORT_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/include/hal_ll/CMakeLists.txt b/targets/avr_8bit/mikroe/avr/include/hal_ll/CMakeLists.txt
new file mode 100644
index 000000000..9acf1ce88
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/hal_ll/CMakeLists.txt
@@ -0,0 +1,24 @@
+add_library(lib_hal_ll INTERFACE)
+
+add_library(MikroSDK.HalLowLevel  ALIAS lib_hal_ll)
+
+target_link_libraries(lib_hal_ll  INTERFACE
+    MikroSDK.HalLowLevel.ADC
+    MikroSDK.HalLowLevel.GPIO
+    MikroSDK.HalLowLevel.I2C.Master
+    MikroSDK.HalLowLevel.SPI.Master
+    MikroSDK.HalLowLevel.TIM
+    MikroSDK.HalLowLevel.UART
+    # MikroSDK.HalLowLevel.OneWire TODO
+)
+
+mikrosdk_install(MikroSDK.HalLowLevel)
+
+install(
+    FILES
+        ../../include/hal_ll_target.h
+        ../../include/hal_ll_pin_names.h
+        ../../include/hal_ll_target_names.h
+    DESTINATION
+        ${CMAKE_INSTALL_PREFIX}/include/hal_ll_port
+)
diff --git a/targets/avr_8bit/mikroe/avr/include/hal_ll_pin_names.h b/targets/avr_8bit/mikroe/avr/include/hal_ll_pin_names.h
new file mode 100644
index 000000000..afa0d9007
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/hal_ll_pin_names.h
@@ -0,0 +1,444 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_pin_names.h
+ * @brief Header file containing symbolic pin name definitions.
+ */
+
+#ifndef _HAL_LL_PIN_NAMES_H_
+#define _HAL_LL_PIN_NAMES_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "mcu_definitions.h"
+#include "hal_ll_target_names.h"
+
+#define GPIO_FEATURE_8BIT_PORT
+
+#ifdef __PORT_A_CN
+#define GPIO_FEATURE_GROUP_1
+#endif
+#ifdef __PORT_B_CN
+#define GPIO_FEATURE_GROUP_2
+#endif
+#ifdef __PORT_C_CN
+#define GPIO_FEATURE_GROUP_3
+#endif
+#ifdef __PORT_D_CN
+#define GPIO_FEATURE_GROUP_4
+#endif
+#ifdef __PORT_E_CN
+#define GPIO_FEATURE_GROUP_5
+#endif
+#ifdef __PORT_F_CN
+#define GPIO_FEATURE_GROUP_6
+#endif
+#ifdef __PORT_G_CN
+#define GPIO_FEATURE_GROUP_7
+#endif
+#ifdef __PORT_H_CN
+#define GPIO_FEATURE_GROUP_8
+#endif
+#ifdef __PORT_J_CN
+#define GPIO_FEATURE_GROUP_9
+#endif
+#ifdef __PORT_K_CN
+#define GPIO_FEATURE_GROUP_10
+#endif
+#ifdef __PORT_L_CN
+#define GPIO_FEATURE_GROUP_11
+#endif
+#ifdef __PORT_R_CN
+#define GPIO_FEATURE_GROUP_12
+#endif
+
+#ifdef __PA0_CN
+#define PA0  (0x00)
+#endif
+#ifdef __PA1_CN
+#define PA1  (0x01)
+#endif
+#ifdef __PA2_CN
+#define PA2  (0x02)
+#endif
+#ifdef __PA3_CN
+#define PA3  (0x03)
+#endif
+#ifdef __PA4_CN
+#define PA4  (0x04)
+#endif
+#ifdef __PA5_CN
+#define PA5  (0x05)
+#endif
+#ifdef __PA6_CN
+#define PA6  (0x06)
+#endif
+#ifdef __PA7_CN
+#define PA7  (0x07)
+#endif
+
+#ifdef __PB0_CN
+#define PB0  (0x08)
+#endif
+#ifdef __PB1_CN
+#define PB1  (0x09)
+#endif
+#ifdef __PB2_CN
+#define PB2  (0x0A)
+#endif
+#ifdef __PB3_CN
+#define PB3  (0x0B)
+#endif
+#ifdef __PB4_CN
+#define PB4  (0x0C)
+#endif
+#ifdef __PB5_CN
+#define PB5  (0x0D)
+#endif
+#ifdef __PB6_CN
+#define PB6  (0x0E)
+#endif
+#ifdef __PB7_CN
+#define PB7  (0x0F)
+#endif
+
+#ifdef __PC0_CN
+#define PC0  (0x10)
+#endif
+#ifdef __PC1_CN
+#define PC1  (0x11)
+#endif
+#ifdef __PC2_CN
+#define PC2  (0x12)
+#endif
+#ifdef __PC3_CN
+#define PC3  (0x13)
+#endif
+#ifdef __PC4_CN
+#define PC4  (0x14)
+#endif
+#ifdef __PC5_CN
+#define PC5  (0x15)
+#endif
+#ifdef __PC6_CN
+#define PC6  (0x16)
+#endif
+#ifdef __PC7_CN
+#define PC7  (0x17)
+#endif
+
+#ifdef __PD0_CN
+#define PD0  (0x18)
+#endif
+#ifdef __PD1_CN
+#define PD1  (0x19)
+#endif
+#ifdef __PD2_CN
+#define PD2  (0x1A)
+#endif
+#ifdef __PD3_CN
+#define PD3  (0x1B)
+#endif
+#ifdef __PD4_CN
+#define PD4  (0x1C)
+#endif
+#ifdef __PD5_CN
+#define PD5  (0x1D)
+#endif
+#ifdef __PD6_CN
+#define PD6  (0x1E)
+#endif
+#ifdef __PD7_CN
+#define PD7  (0x1F)
+#endif
+
+#ifdef __PE0_CN
+#define PE0  (0x20)
+#endif
+#ifdef __PE1_CN
+#define PE1  (0x21)
+#endif
+#ifdef __PE2_CN
+#define PE2  (0x22)
+#endif
+#ifdef __PE3_CN
+#define PE3  (0x23)
+#endif
+#ifdef __PE4_CN
+#define PE4  (0x24)
+#endif
+#ifdef __PE5_CN
+#define PE5  (0x25)
+#endif
+#ifdef __PE6_CN
+#define PE6  (0x26)
+#endif
+#ifdef __PE7_CN
+#define PE7  (0x27)
+#endif
+
+#ifdef __PF0_CN
+#define PF0  (0x28)
+#endif
+#ifdef __PF1_CN
+#define PF1  (0x29)
+#endif
+#ifdef __PF2_CN
+#define PF2  (0x2A)
+#endif
+#ifdef __PF3_CN
+#define PF3  (0x2B)
+#endif
+#ifdef __PF4_CN
+#define PF4  (0x2C)
+#endif
+#ifdef __PF5_CN
+#define PF5  (0x2D)
+#endif
+#ifdef __PF6_CN
+#define PF6  (0x2E)
+#endif
+#ifdef __PF7_CN
+#define PF7  (0x2F)
+#endif
+
+#ifdef __PG0_CN
+#define PG0  (0x30)
+#endif
+#ifdef __PG1_CN
+#define PG1  (0x31)
+#endif
+#ifdef __PG2_CN
+#define PG2  (0x32)
+#endif
+#ifdef __PG3_CN
+#define PG3  (0x33)
+#endif
+#ifdef __PG4_CN
+#define PG4  (0x34)
+#endif
+#ifdef __PG5_CN
+#define PG5  (0x35)
+#endif
+#ifdef __PG6_CN
+#define PG6  (0x36)
+#endif
+#ifdef __PG7_CN
+#define PG7  (0x37)
+#endif
+
+#ifdef __PH0_CN
+#define PH0  (0x38)
+#endif
+#ifdef __PH1_CN
+#define PH1  (0x39)
+#endif
+#ifdef __PH2_CN
+#define PH2  (0x3A)
+#endif
+#ifdef __PH3_CN
+#define PH3  (0x3B)
+#endif
+#ifdef __PH4_CN
+#define PH4  (0x3C)
+#endif
+#ifdef __PH5_CN
+#define PH5  (0x3D)
+#endif
+#ifdef __PH6_CN
+#define PH6  (0x3E)
+#endif
+#ifdef __PH7_CN
+#define PH7  (0x3F)
+#endif
+
+#ifdef __PJ0_CN
+#define PJ0  (0x40)
+#endif
+#ifdef __PJ1_CN
+#define PJ1  (0x41)
+#endif
+#ifdef __PJ2_CN
+#define PJ2  (0x42)
+#endif
+#ifdef __PJ3_CN
+#define PJ3  (0x43)
+#endif
+#ifdef __PJ4_CN
+#define PJ4  (0x44)
+#endif
+#ifdef __PJ5_CN
+#define PJ5  (0x45)
+#endif
+#ifdef __PJ6_CN
+#define PJ6  (0x46)
+#endif
+#ifdef __PJ7_CN
+#define PJ7  (0x47)
+#endif
+
+#ifdef __PK0_CN
+#define PK0  (0x48)
+#endif
+#ifdef __PK1_CN
+#define PK1  (0x49)
+#endif
+#ifdef __PK2_CN
+#define PK2  (0x4A)
+#endif
+#ifdef __PK3_CN
+#define PK3  (0x4B)
+#endif
+#ifdef __PK4_CN
+#define PK4  (0x4C)
+#endif
+#ifdef __PK5_CN
+#define PK5  (0x4D)
+#endif
+#ifdef __PK6_CN
+#define PK6  (0x4E)
+#endif
+#ifdef __PK7_CN
+#define PK7  (0x4F)
+#endif
+
+#ifdef __PL0_CN
+#define PL0  (0x50)
+#endif
+#ifdef __PL1_CN
+#define PL1  (0x51)
+#endif
+#ifdef __PL2_CN
+#define PL2  (0x52)
+#endif
+#ifdef __PL3_CN
+#define PL3  (0x53)
+#endif
+#ifdef __PL4_CN
+#define PL4  (0x54)
+#endif
+#ifdef __PL5_CN
+#define PL5  (0x55)
+#endif
+#ifdef __PL6_CN
+#define PL6  (0x56)
+#endif
+#ifdef __PL7_CN
+#define PL7  (0x57)
+#endif
+
+#ifdef __PR0_CN
+#define PR0  (0x58)
+#endif
+#ifdef __PR1_CN
+#define PR1  (0x59)
+#endif
+#ifdef __PR2_CN
+#define PR2  (0x5A)
+#endif
+#ifdef __PR3_CN
+#define PR3  (0x5B)
+#endif
+#ifdef __PR4_CN
+#define PR4  (0x5C)
+#endif
+#ifdef __PR5_CN
+#define PR5  (0x5D)
+#endif
+#ifdef __PR6_CN
+#define PR6  (0x5E)
+#endif
+#ifdef __PR7_CN
+#define PR7  (0x5F)
+#endif
+
+#define PIN_0 (0x00)
+#define PIN_1 (0x01)
+#define PIN_2 (0x02)
+#define PIN_3 (0x03)
+#define PIN_4 (0x04)
+#define PIN_5 (0x05)
+#define PIN_6 (0x06)
+#define PIN_7 (0x07)
+
+#ifdef __PORT_A_CN
+#define PORT_A (0x00)
+#endif
+#ifdef __PORT_B_CN
+#define PORT_B (0x01)
+#endif
+#ifdef __PORT_C_CN
+#define PORT_C (0x02)
+#endif
+#ifdef __PORT_D_CN
+#define PORT_D (0x03)
+#endif
+#ifdef __PORT_E_CN
+#define PORT_E (0x04)
+#endif
+#ifdef __PORT_F_CN
+#define PORT_F (0x05)
+#endif
+#ifdef __PORT_G_CN
+#define PORT_G (0x06)
+#endif
+#ifdef __PORT_H_CN
+#define PORT_H (0x07)
+#endif
+#ifdef __PORT_J_CN
+#define PORT_J (0x08)
+#endif
+#ifdef __PORT_K_CN
+#define PORT_K (0x09)
+#endif
+#ifdef __PORT_L_CN
+#define PORT_L (0x0A)
+#endif
+#ifdef __PORT_R_CN
+#define PORT_R (0x0B)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_PIN_NAMES_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/include/hal_ll_target.h b/targets/avr_8bit/mikroe/avr/include/hal_ll_target.h
new file mode 100644
index 000000000..5d4b49228
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/hal_ll_target.h
@@ -0,0 +1,65 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_target.h
+ * @brief Header file containing symbolic pin name definitions.
+ */
+
+#ifndef _HAL_LL_TARGET_H_
+#define _HAL_LL_TARGET_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_ll_pin_names.h"
+#include "hal_ll_bit_control.h"
+#include "common_macros.h"
+
+#define HAL_LL_MODULE_ERROR (hal_ll_base_addr_t)(0xFFFFFFFF)
+#define HAL_LL_CHANNEL_ERROR (hal_ll_base_addr_t)(0xFFFFFFFF)
+#define HAL_LL_PIN_NC (hal_ll_pin_name_t)(0xFFFFFFFF)
+#define HAL_LL_PORT_NC (hal_ll_port_name_t)(0xFFFFFFFF)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_TARGET_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/include/hal_ll_target_names.h b/targets/avr_8bit/mikroe/avr/include/hal_ll_target_names.h
new file mode 100644
index 000000000..d969845dd
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/hal_ll_target_names.h
@@ -0,0 +1,72 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file hal_ll_target_names.h
+ * @brief Header file containing symbolic pin name definitions.
+ */
+
+#ifndef _HAL_LL_TARGET_NAMES_H_
+#define _HAL_LL_TARGET_NAMES_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+typedef uintptr_t handle_t;
+typedef uint8_t hal_ll_gpio_mask_t;
+typedef uint8_t hal_ll_pin_name_t;
+typedef uint8_t hal_ll_port_name_t;
+typedef uint8_t hal_ll_port_size_t;
+typedef uint16_t hal_ll_base_addr_t;
+typedef uint8_t hal_ll_channel_t;
+
+typedef int32_t hal_ll_err_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_TARGET_NAMES_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/include/i2c/hal_ll_i2c_master.h b/targets/avr_8bit/mikroe/avr/include/i2c/hal_ll_i2c_master.h
new file mode 100644
index 000000000..9a600b95d
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/i2c/hal_ll_i2c_master.h
@@ -0,0 +1,241 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_i2c_master.h
+ * @brief API for I2C master HAL LOW LEVEL layer.
+ */
+
+#ifndef _HAL_LL_I2C_MASTER_H_
+#define _HAL_LL_I2C_MASTER_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_ll_target.h"
+
+/**
+ * @brief I2C master low level pins config structure.
+ *
+ * The context structure for storing low level pin configuration
+ * for both SCL and SDA pins.
+ *
+ */
+typedef struct
+{
+    hal_ll_pin_name_t pin_scl;
+    hal_ll_pin_name_t pin_sda;
+} hal_ll_i2c_pins_t;
+
+/**
+ * @brief I2C master low level handle.
+ *
+ * The context for storing low level object handler.
+ * User is not to change these values or unexpected behaviour
+ * may occur.
+ */
+typedef struct
+{
+    handle_t *hal_ll_i2c_master_handle;
+    handle_t *hal_drv_i2c_master_handle;
+    bool init_ll_state;
+} hal_ll_i2c_master_handle_register_t;
+
+/**
+ * @brief  Registers handler for future use.
+ *
+ * Registers low level and hal level handlers
+ * for use with appropriate functions.
+ *
+ * @param[in] scl I2C SCL pin.
+ * @param[in] sda I2C SDA pin.
+ * @param[in] *handle_map HAL layer local handle map.
+ * @param[in] *hal_module_id HAL layer module number.
+
+ * @return hal_ll_err_t Module specific error.
+ *
+ * Returns one of pre-defined values.
+ * Take into consideration that this is hardware specific.
+ */
+hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id );
+
+/**
+ * @brief  Configures specified module.
+ *
+ * Performs module configuration on the hardware
+ * level. Enables module specific clock gate and
+ * sets adequate alternate function values.
+ *
+ * @param[in]  *handle HAL context object handle.
+ *
+ * @return  hal_ll_err_t Module specific error.
+ *
+ * Returns one of pre-defined values.
+ * Take into consideration that this is hardware specific.
+ */
+hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle );
+
+/**
+ * @brief  Sets I2C slave address.
+ *
+ * Registers I2C slave address for specified
+ * object.
+ *
+ * @param[in] *handle HAL context object handle.
+ * @param[in] addr I2C slave address.
+ *
+ * @return void None.
+ */
+void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr );
+
+/**
+ * @brief  Sets I2C module speed.
+ *
+ * Sets specified speed for module.
+ * Take into consideration that the module
+ * will be re-initialized on the hardware level.
+ *
+ * @param[in] *handle HAL context object handle.
+ * @param[in] speed Desired speed value.
+ *
+ * @return hal_ll_err_t Module specific error.
+ *
+ * Returns value of speed the module was
+ * initialized to, or module specific error if
+ * initialization failed.
+ * When using from low level directly,
+ * speed can be set to any desired value,
+ * but take into consideration that not all values
+ * will work, as this is chip specific.
+ * Speed value is declared in kbit/s.
+ */
+hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed );
+
+/**
+ * @brief  Sets I2C timeout value.
+ *
+ * Registers I2C timeout value in number of retries.
+ * Module shall retry any given operation
+ * `timeout` number of times before aborting operation.
+ *
+ * @param[in] *handle HAL context object handle.
+ * @param[in] timeout I2C timeout value.
+ *
+ * @return void None.
+ */
+void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout );
+
+/**
+ * @brief Executes low level data read on I2C bus.
+ *
+ * Function shall generate a START signal,
+ * followed by lenReadData number of reads
+ * on the bus. Ends with a STOP signal.
+ *
+ * @param handle I2C handle.
+ * @param *readDatabuf Data buffer where read data
+ *                     shall be placed.
+ * @param lenReadData Number of bytes to read.
+ *
+ * @return hal_ll_err_t Module specific error.
+ *
+ * Returns one of pre-defined values.
+ * Take into consideration that this is hardware specific.
+ */
+hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data );
+
+/**
+ * @brief Executes low level data write on I2C bus.
+ *
+ * Function shall generate a START signal,
+ * followed by lenWriteData number of writes
+ * on the bus. Ends with a STOP signal.
+ *
+ * @param handle I2C handle.
+ * @param *WriteDatabuf Data buffer where data to
+ *                      be written is located.
+ * @param lenWriteData Number of bytes to send.
+ *
+ * @return hal_ll_err_t Module specific error.
+ *
+ * Returns one of pre-defined values.
+ * Take into consideration that this is hardware specific.
+ */
+hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data );
+
+/**
+  * @brief  Perform a low level write followed by a low level read on the I2C bus.
+  *
+  * Initializes I2C module on hardware level, if not initialized beforehand
+  * and continues to perform a write operation followed by a
+  * read operation on the bus.
+  * The operation consists of a start signal followed by lenWriteData number
+  * of write operations, a restart signal followed by lenReadData number
+  * of read operations finishing with a stop signal.
+  *
+  * @param handle I2C handle.
+  * @param[in]  *writeDatabuf - Pointer to write data buffer.
+  * @param[in]  lenWriteData - Number of data to be written.
+  * @param[in]  *readDatabuf - Pointer to read data buffer.
+  * @param[in]  lenReadData - Number of data to be read.
+  * @return hal_ll_err_t Module specific values.
+  *
+  * Returns one of pre-defined values.
+  * Take into consideration that this is hardware specific.
+  */
+hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data );
+
+/**
+ * @brief  Closes I2C master HAL and HAL_LOW_LEVEL context object.
+ *
+ * De-allocates hardware resources for specific driver object and
+ * de-initializes the module on a hardware level.
+ *
+ * @param[in] *handle HAL context object handle.
+ *
+ * @return void None.
+ */
+void hal_ll_i2c_master_close( handle_t *handle );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_I2C_MASTER_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/include/i2c/hal_ll_i2c_pin_map.h b/targets/avr_8bit/mikroe/avr/include/i2c/hal_ll_i2c_pin_map.h
new file mode 100644
index 000000000..eb67ac806
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/i2c/hal_ll_i2c_pin_map.h
@@ -0,0 +1,162 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*
+
+  This file is part of mikroSDK.
+
+  Copyright (c) 2022, MikroElektonika - www.mikroe.com
+
+  All rights reserved.
+
+-------------------------------------------------------------------------- */
+/*!
+ * @file  hal_ll_i2c_pin_map.h
+ * @brief I2C HAL LOW LEVEL PIN MAPS.
+ */
+
+#ifndef _HAL_LL_I2C_PIN_MAP_H_
+#define _HAL_LL_I2C_PIN_MAP_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_ll_pin_names.h"
+
+/*!< @brief Helper macro for getting adequate module index number */
+#define hal_ll_i2c_module_num(_module_num) (_module_num - 1)
+
+/*!< @brief Macro defining `weak` attribute */
+#define __weak __attribute__((weak))
+
+/*!< @brief Pin function structure */
+typedef struct {
+    hal_ll_pin_name_t pin;
+    hal_ll_base_addr_t base;
+    uint8_t module_index;
+} hal_ll_i2c_pin_map_t;
+
+/*!< @brief I2C SCL pins */
+__weak static const hal_ll_i2c_pin_map_t hal_ll_i2c_scl_map[] = {
+    //------------ BEGIN SCL
+    #ifdef TWI0_SCL_PD0
+    {PD0, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_0)},
+    #endif
+    #ifdef TWI0_SCL_PC0
+    {PC0, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_0)},
+    #endif
+    #ifdef TWI0_SCL_PC5
+    {PC5, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_0)},
+    #endif
+    #ifdef TWI0_SCL0_PC0
+    {PC0, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_0)},
+    #endif
+    #ifdef TWI1_SCL1_PE6
+    {PE6, HAL_LL_I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_1)},
+    #endif
+    #ifdef TWI1_SCL_PE1
+    {PE1, HAL_LL_I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_1)},
+    #endif
+    #ifdef TWIC_SCL_PC1
+    {PC1, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_C)},
+    #endif
+    #ifdef TWID_SCL_PD1
+    {PD1, HAL_LL_I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_D)},
+    #endif
+    #ifdef TWIE_SCL_PE1
+    {PE1, HAL_LL_I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_E)},
+    #endif
+    #ifdef TWIF_SCL_PF1
+    {PF1, HAL_LL_I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_F)},
+    #endif
+    #ifdef TWIC_SCL_PD1
+    {PD1, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_C)},
+    #endif
+
+    { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR }
+    //------------ END SCL
+};
+
+/*!< @brief I2C SDA pins */
+__weak static const hal_ll_i2c_pin_map_t hal_ll_i2c_sda_map[] = {
+    //------------ BEGIN SDA
+    #ifdef TWI0_SDA_PD1
+    {PD1, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_0)},
+    #endif
+    #ifdef TWI0_SDA_PC1
+    {PC1, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_0)},
+    #endif
+    #ifdef TWI0_SDA_PC4
+    {PC4, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_0)},
+    #endif
+    #ifdef TWI0_SDA0_PC1
+    {PC1, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_0)},
+    #endif
+    #ifdef TWI1_SDA1_PE5
+    {PE5, HAL_LL_I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_1)},
+    #endif
+    #ifdef TWI1_SDA_PE0
+    {PE0, HAL_LL_I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_1)},
+    #endif
+    #ifdef TWIC_SDA_PC0
+    {PC0, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_C)},
+    #endif
+    #ifdef TWID_SDA_PD0
+    {PD0, HAL_LL_I2C1_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_D)},
+    #endif
+    #ifdef TWIE_SDA_PE0
+    {PE0, HAL_LL_I2C2_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_E)},
+    #endif
+    #ifdef TWIF_SDA_PF0
+    {PF0, HAL_LL_I2C3_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_F)},
+    #endif
+    #ifdef TWIC_SDA_PD0
+    {PD0, HAL_LL_I2C0_BASE_ADDRESS, hal_ll_i2c_module_num(TWI_MODULE_C)},
+    #endif
+
+    { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR }
+    //------------ END SDA
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_I2C_PIN_MAP_H_
+// ---------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/include/one_wire/hal_ll_one_wire.h b/targets/avr_8bit/mikroe/avr/include/one_wire/hal_ll_one_wire.h
new file mode 100644
index 000000000..1bcdc73ab
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/one_wire/hal_ll_one_wire.h
@@ -0,0 +1,230 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_one_wire.h
+ * @brief API for One Wire HAL LOW LEVEL layer.
+ */
+
+#ifndef _HAL_LL_ONE_WIRE_H_
+#define _HAL_LL_ONE_WIRE_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_ll_gpio.h"
+
+/**
+ * @brief Structure for storing One Wire device address.
+ * @details Unique One Wire address used for device addressing.
+ */
+typedef struct {
+    uint8_t address[8]; /*!< One Wire address buffer. */
+} hal_ll_one_wire_rom_address_t;
+
+/**
+ * @brief One Wire HAL Low Level context structure.
+ * @details The context structure for storing driver internal state. The contents of the
+ * context structure are used by the module and must not be altered. Reading or
+ * writing data directly from a control structure by user should be avoided.
+ */
+typedef struct {
+    hal_ll_pin_name_t data_pin; // One Wire data pin.
+    volatile uint16_t tris; // Register for altering GPIO pin direction.
+    volatile uint16_t lat; // Register for GPIO port bit set/reset.
+    volatile uint16_t port; // Register for reading current GPIO pin state.
+} hal_ll_one_wire_local_t;
+
+/**
+ * @brief One Wire HAL Low Level initialization configuration structure.
+ *
+ * @details
+ * - data_pin value - to be configured as desired.
+ * - state value    - NOTE must not be altered (it is supposed to be set automatically in Low Level Layer).
+ */
+typedef struct {
+    hal_ll_pin_name_t data_pin; /*!< One Wire pin - user is to configure it as desired. */
+    bool state; /*!< State of a pin. NOTE must not be altered. */
+} hal_ll_one_wire_t;
+
+/**
+ * @details Enum containing predefined module return values.
+ */
+typedef enum {
+    HAL_LL_ONE_WIRE_SUCCESS = 0, /*!< Success. */
+    HAL_LL_ONE_WIRE_ERROR = (-1) /*!< Error. */
+} hal_ll_one_wire_err_t;
+
+/**
+ * @brief Opens One Wire HAL Low Level object.
+ * @details Opens One Wire HAL Low Level object on selected pin.
+ * Enables appropriate PORT clock, configures pin to have digital output functionality,
+ * makes sure that HIGH voltage state is applied on pin before any One Wire actions.
+ * @param[in,out] *obj One Wire HAL Low Level object.
+ * See #hal_ll_one_wire_t structure definition for detailed explanation.
+ * @return None.
+ * @pre Make sure that \p LowLevel structure has been adequately
+ * populated beforehand.
+ * @note It is recommended to check return value for error.
+ */
+void hal_ll_one_wire_open( hal_ll_one_wire_t *obj );
+
+/**
+ * @brief Reset One Wire bus.
+ * @details Host shall send reset sequence and devices shall go into reset state.
+ * @param[in,out] *handle One Wire HAL Low Level object.
+ * See #hal_one_wire_t structure definition for detailed explanation.
+ * @return The function can return one of the values defined by
+ * #hal_ll_one_wire_err_t, which is size dependant on the architecture.
+ * @pre Before calling this function,
+ * the user is expected to call #hal_ll_one_wire_open function.
+ */
+hal_ll_err_t hal_ll_one_wire_reset( hal_ll_one_wire_t *obj );
+
+/**
+ * @brief Reads device's ROM information.
+ * @details Allows the host to read eight-bit family code,
+ * 48-bit serial number, and eight-bit CRC.
+ *
+ * @important THIS FUNCTION IS TO BE ISSUED ONLY IF WE ARE DEALING WITH
+ * ONE DEVICE ONLY. THIS FUNCTION AUTOMATICALLY RESETS ONE WIRE BUS.
+ * @param[in] *obj One Wire HAL Low Level object.
+ * See #hal_one_wire_t structure definition for detailed explanation.
+ * @param[out] *device_rom_address Buffer for One Wire device ROM information.
+ * @return The function can return one of the values defined by
+ * #hal_ll_one_wire_err_t, which is size dependant on the architecture.
+ */
+hal_ll_err_t hal_ll_one_wire_read_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address );
+
+/**
+ * @brief Access device's level functions without transmitting ROM information.
+ * @details Allows the host to access device functions without
+ * providing the 64-bit ROM identification number.
+ *
+ * @important THIS FUNCTION IS TO BE ISSUED ONLY IF WE ARE DEALING WITH
+ * ONE DEVICE ONLY. THIS FUNCTION AUTOMATICALLY RESETS ONE WIRE BUS.
+ * @param[in] *obj One Wire HAL Low Level object.
+ * See #hal_one_wire_t structure definition for detailed explanation.
+ * @return The function can return one of the values defined by
+ * #hal_ll_one_wire_err_t, which is size dependant on the architecture.
+ */
+hal_ll_err_t hal_ll_one_wire_skip_rom( hal_ll_one_wire_t *obj );
+
+/**
+ * @brief Selects a specific One Wire capable device on bus.
+ * @details Select a One Wire device with specific ID.
+ *
+ * @param[in] *obj One Wire HAL Low Level object.
+ * See #hal_ll_one_wire_t structure definition for detailed explanation.
+ * @param[in] device_rom_address Buffer for One Wire device ROM information.
+ * @return The function can return one of the values defined by
+ * #hal_ll_one_wire_err_t, which is size dependant on the architecture.
+ * @pre Before calling this function,
+ * the user is expected to call #hal_one_wire_open function.
+ */
+hal_ll_err_t hal_ll_one_wire_match_rom( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *device_rom_address );
+
+/**
+ * @brief Search One Wire capable device on bus.
+ * @details Search and list 1st device that is One Wire capable.
+ *
+ * @param[in] *obj One Wire HAL Low Level object.
+ * See #hal_ll_one_wire_t structure definition for detailed explanation.
+ * @param[out] *one_wire_device_list Buffer for One Wire device ROM information.
+ * @return The function can return one of the values defined by
+ * #hal_ll_one_wire_err_t, which is size dependant on the architecture.
+ * @pre Before calling this function,
+ * the user is expected to call #hal_ll_one_wire_open function.
+ */
+hal_ll_err_t hal_ll_one_wire_search_first_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list );
+
+/**
+ * @brief Search One Wire capable devices on bus.
+ * @details Search devices that is One Wire capable.
+ *
+ * @param[in] *obj One Wire HAL Low Level object.
+ * See #hal_ll_one_wire_t structure definition for detailed explanation.
+ * @param[out] *one_wire_device_list Buffer for One Wire device ROM information.
+ * @return The function can return one of the values defined by
+ * #hal_ll_one_wire_err_t, which is size dependant on the architecture.
+ * @pre Before calling this function,
+ * the user is expected to call #hal_ll_one_wire_open function.
+ */
+hal_ll_err_t hal_ll_one_wire_search_next_device( hal_ll_one_wire_t *obj, hal_ll_one_wire_rom_address_t *one_wire_device_list );
+
+/**
+ * @brief Writes byte to One Wire bus.
+ * @details Writes byte to One Wire bus.
+ * @param[in] *write_data_buffer Data transmit buffer.
+ * @param[in] write_data_length Number of bytes to write from data transmit buffer.
+ * @return None.
+ * @pre Before calling this function,
+ * the user is expected to call #hal_ll_one_wire_open function.
+ */
+void hal_ll_one_wire_write_byte( uint8_t *write_data_buffer, size_t write_data_length );
+
+/**
+ * @brief Reads byte from One Wire bus.
+ * @details Reads byte from One Wire bus.
+ * @param[out] *read_data_buffer Data receive buffer.
+ * @param[in] read_data_length Number of bytes to be read.
+ * @return None.
+ * @pre Before calling this function,
+ * the user is expected to call #hal_ll_one_wire_open function.
+ */
+void hal_ll_one_wire_read_byte( uint8_t *read_data_buffer, size_t read_data_length );
+
+/**
+ * @brief Reconfigures One Wire pin settings.
+ * @details Enables appropriate PORT clock, configures pin to have digital output functionality,
+ * makes sure that HIGH voltage state is applied on pin before any One Wire actions.
+ * @param[in] *obj One Wire HAL Low Level object.
+ * See #hal_ll_one_wire_t structure definition for detailed explanation.
+ * @return None.
+ * @pre Before calling this function,
+ * the user is expected to call #hal_one_wire_open function.
+ */
+void hal_ll_one_wire_reconfigure( hal_ll_one_wire_t *obj );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_ONE_WIRE_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/include/spi_master/hal_ll_spi_master.h b/targets/avr_8bit/mikroe/avr/include/spi_master/hal_ll_spi_master.h
new file mode 100644
index 000000000..1cd8e0435
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/spi_master/hal_ll_spi_master.h
@@ -0,0 +1,216 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_spi_master.h
+ * @brief SPI MASTER HAL LOW LEVEL FUNCTION PROTOTYPES.
+ */
+
+#ifndef _HAL_LL_SPI_MASTER_H_
+#define _HAL_LL_SPI_MASTER_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include <stdint.h>
+#include "hal_ll_target.h"
+#include "hal_ll_gpio.h"
+
+/**
+ * @brief SPI configuration pins structure.
+ */
+typedef struct {
+    hal_ll_pin_name_t sck;
+    hal_ll_pin_name_t miso;
+    hal_ll_pin_name_t mosi;
+    hal_ll_pin_name_t ss; /* SPI protocol will initiate communication
+                             cycle by pulling low Slave Select (SS) pin
+                             (applicable for non-ATXmega MCUs). */
+} hal_ll_spi_master_pins_t;
+
+/**
+ * @brief Enum containing predefined module mode values.
+ *
+ * Enum values:
+ *
+ * HAL_LL_SPI_MASTER_MODE_0 -- CPOL = 0, CPHA = 0
+ * HAL_LL_SPI_MASTER_MODE_1 -- CPOL = 0, CPHA = 1
+ * HAL_LL_SPI_MASTER_MODE_2 -- CPOL = 1, CPHA = 0
+ * HAL_LL_SPI_MASTER_MODE_3 -- CPOL = 1, CPHA = 1
+ */
+typedef enum {
+    HAL_LL_SPI_MASTER_MODE_0 = 0,
+    HAL_LL_SPI_MASTER_MODE_1,
+    HAL_LL_SPI_MASTER_MODE_2,
+    HAL_LL_SPI_MASTER_MODE_3,
+
+    HAL_LL_SPI_MASTER_MODE_DEFAULT = HAL_LL_SPI_MASTER_MODE_0
+} hal_ll_spi_master_mode_t;
+
+/**
+ * @brief SPI master HAL low lever handle register.
+ */
+typedef struct {
+    handle_t *hal_ll_spi_master_handle;
+    handle_t *hal_drv_spi_master_handle;
+    bool init_ll_state;
+} hal_ll_spi_master_handle_register_t;
+
+/**
+ * @brief  Registers handler for future use.
+ *
+ * Registers low level and hal level handlers
+ * for use with appropriate functions.
+ *
+ * @param[in] *handle Low Level HAL context object handle.
+ * @param[in] sck SPI sck pin.
+ * @param[in] miso SPI miso pin.
+ * @param[in] mosi SPI mosi pin.
+ * @param[in] *handle_map HAL layer local handle map.
+ * @param[in] *hal_module_id HAL layer module number.
+
+ * @return hal_ll_err_t Module specific error.
+ *
+ * Returns one of pre-defined error values.
+ * Take into consideration that this is hardware specific.
+ */
+hal_ll_err_t hal_ll_spi_master_register_handle( hal_ll_pin_name_t sck, hal_ll_pin_name_t miso,
+                                                hal_ll_pin_name_t mosi,
+                                                hal_ll_spi_master_handle_register_t *handle_map,
+                                                uint8_t *hal_module_id );
+
+/**
+ * @brief Sets SPI Master settings and does initialization of a SPI module.
+ * @param[in] *handle Low Level HAL context object handle.
+ */
+hal_ll_err_t hal_ll_module_configure_spi( handle_t *handle );
+
+/**
+ * @brief Sets SPI Master configuration dummy data.
+ * @param[in] *handle Low Level HAL context object handle.
+ * @param[in] dummy_data User-defined dummy data.
+ */
+void hal_ll_spi_master_set_default_write_data( handle_t *handle, uint8_t dummy_data );
+
+/**
+ * @brief Sets SPI Master configuration dummy data.
+ * @param[in] *handle Low Level HAL context object handle.
+ * @param[in] speed User-defined SPI Master baud rate value.
+ */
+uint32_t hal_ll_spi_master_set_speed( handle_t *handle, uint32_t speed );
+
+/**
+ * @brief Sets SPI Master configuration dummy data.
+ * @param[in] *handle Low Level HAL context object handle.
+ * @param[in] mode User-defined SPI Master mode.
+ */
+hal_ll_err_t hal_ll_spi_master_set_mode( handle_t *handle, hal_ll_spi_master_mode_t mode );
+
+
+/**
+ * @brief Executes low level data write on SPI bus.
+ *
+ * Function shall generate a START signal,
+ * followed by write_data_buffer number of writes
+ * on the bus.
+ *
+ * @param[in] *handle Low Level HAL context object handle.
+ * @param[in] *write_data_buffer Data buffer where data to be written is located.
+ * @param[in] length_data Number of bytes to send.
+ *
+ * @return hal_ll_err_t Module specific error.
+ *
+ * Returns one of pre-defined values.
+ * Take into consideration that this is hardware specific.
+ */
+hal_ll_err_t hal_ll_spi_master_write( handle_t *handle, uint8_t *write_data_buffer, size_t length_data );
+
+/**
+ * @brief Executes low level data read on SPI bus.
+ *
+ * @param[in] handle Low Level HAL context object handle.
+ * @param[in] *read_data_buffer Data buffer where read data shall be placed.
+ * @param[in] length_data Number of bytes to read.
+ *
+ * @return hal_ll_err_t Module specific error.
+ *
+ * Returns one of pre-defined values.
+ * Take into consideration that this is hardware specific.
+ */
+hal_ll_err_t hal_ll_spi_master_read( handle_t *handle, uint8_t *read_data_buffer, size_t length_data );
+
+/**
+  * @brief  Perform a low level write followed by a low level read on the SPI bus.
+  *
+  * Initializes SPI Master module on hardware level, if not initialized beforehand
+  * and continues to perform a write operation followed by a
+  * read operation on the bus.
+  *
+  * @param[in]  *handle - Low Level HAL context object handle.
+  * @param[in]  *write_data_buffer - Pointer to write data buffer.
+  * @param[in]  length_write_data - Number of data to be written.
+  * @param[in]  *read_data_buffer - Pointer to read data buffer.
+  * @param[in]  length_read_data - Number of data to be read.
+  * @return hal_ll_err_t Module specific values.
+  *
+  * Returns one of pre-defined values.
+  * Take into consideration that this is hardware specific.
+  */
+hal_ll_err_t hal_ll_spi_master_write_then_read( handle_t *handle, uint8_t *write_data_buffer,
+                                                size_t length_write_data, uint8_t *read_data_buffer,
+                                                size_t length_read_data );
+
+/**
+ * @brief  Closes SPI Master HAL and HAL_LOW_LEVEL context object.
+ *
+ * De-allocates hardware resources for specific driver object and
+ * de-initializes the module on a hardware level.
+ *
+ * @param[in] *handle Low Level HAL context object handle.
+ *
+ * @return void None.
+ */
+void hal_ll_spi_master_close( handle_t *handle );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_SPI_MASTER_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/include/spi_master/hal_ll_spi_master_pin_map.h b/targets/avr_8bit/mikroe/avr/include/spi_master/hal_ll_spi_master_pin_map.h
new file mode 100644
index 000000000..a9243d3c1
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/spi_master/hal_ll_spi_master_pin_map.h
@@ -0,0 +1,231 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*
+
+  This file is part of mikroSDK.
+
+  Copyright (c) 2022, MikroElektonika - www.mikroe.com
+
+  All rights reserved.
+
+-------------------------------------------------------------------------- */
+/*!
+ * @file  hal_ll_spi_master_pin_map.h
+ * @brief SPI MASTER HAL LOW LEVEL PIN MAPS.
+ */
+
+#ifndef _HAL_LL_SPI_MASTER_PIN_MAP_H_
+#define _HAL_LL_SPI_MASTER_PIN_MAP_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_ll_pin_names.h"
+
+/*!< @brief Helper macro for getting adequate module index number */
+#define hal_ll_spi_master_module_num(_module_num) (_module_num - 1)
+
+/*!< @brief Macro defining `weak` attribute */
+#define __weak __attribute__((weak))
+
+/*!< @brief SPI Master pin map structure. */
+typedef struct {
+    hal_ll_pin_name_t pin;
+    uint8_t module_index;
+} hal_ll_spi_master_pin_map_t;
+
+/*!< @brief SPI MASTER SCK pins */
+__weak static const hal_ll_spi_master_pin_map_t _spi_sck_map[] = {
+    //------------ BEGIN SCK
+    #ifdef SPI0_SCK_PB1
+    {PB1, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI0_SCK_PB7
+    {PB7, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI0_SCK_PB5
+    {PB5, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI1_SCK_PD7
+    {PD7, hal_ll_spi_master_module_num(SPI_MODULE_1)},
+    #endif
+    #ifdef SPI1_SCK_PC1
+    {PC1, hal_ll_spi_master_module_num(SPI_MODULE_1)},
+    #endif
+    #ifdef SPI0_SCK_PC7
+    {PC7, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI2_SCK_PE7
+    {PE7, hal_ll_spi_master_module_num(SPI_MODULE_2)},
+    #endif
+    #ifdef SPI3_SCK_PF7
+    {PF7, hal_ll_spi_master_module_num(SPI_MODULE_3)},
+    #endif
+    #ifdef SPI0_SCK_PC5
+    {PC5, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI1_SCK_PD5
+    {PD5, hal_ll_spi_master_module_num(SPI_MODULE_1)},
+    #endif
+    #ifdef SPI2_SCK_PE5
+    {PE5, hal_ll_spi_master_module_num(SPI_MODULE_2)},
+    #endif
+
+    { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR }
+    //------------ END SCK
+};
+
+/*!< @brief SPI MASTER MISO pins */
+__weak static const hal_ll_spi_master_pin_map_t _spi_miso_map[] = {
+    //------------ BEGIN MISO
+    #ifdef SPI0_MISO_PB3
+    {PB3, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI0_MISO_PB6
+    {PB6, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI0_MISO_PB4
+    {PB4, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI1_MISO_PE2
+    {PE2, hal_ll_spi_master_module_num(SPI_MODULE_1)},
+    #endif
+    #ifdef SPI1_MISO_PC0
+    {PC0, hal_ll_spi_master_module_num(SPI_MODULE_1)},
+    #endif
+    #ifdef SPI0_MISO_PC6
+    {PC6, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI1_MISO_PD6
+    {PD6, hal_ll_spi_master_module_num(SPI_MODULE_1)},
+    #endif
+    #ifdef SPI2_MISO_PE6
+    {PE6, hal_ll_spi_master_module_num(SPI_MODULE_2)},
+    #endif
+    #ifdef SPI3_MISO_PF6
+    {PF6, hal_ll_spi_master_module_num(SPI_MODULE_3)},
+    #endif
+
+    { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR }
+    //------------ END MISO
+};
+
+/*!< @brief SPI MASTER MOSI pins */
+__weak static const hal_ll_spi_master_pin_map_t _spi_mosi_map[] = {
+    //------------ BEGIN MOSI
+    #ifdef SPI0_MOSI_PB2
+    {PB2, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI0_MOSI_PB5
+    {PB5, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI0_MOSI_PB3
+    {PB3, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI1_MOSI_PE3
+    {PE3, hal_ll_spi_master_module_num(SPI_MODULE_1)},
+    #endif
+    #ifdef SPI0_MOSI_PC5
+    {PC5, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI1_MOSI_PD5
+    {PD5, hal_ll_spi_master_module_num(SPI_MODULE_1)},
+    #endif
+    #ifdef SPI2_MOSI_PE5
+    {PE5, hal_ll_spi_master_module_num(SPI_MODULE_2)},
+    #endif
+    #ifdef SPI3_MOSI_PF5
+    {PF5, hal_ll_spi_master_module_num(SPI_MODULE_3)},
+    #endif
+    #ifdef SPI0_MOSI_PC7
+    {PC7, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI1_MOSI_PD7
+    {PD7, hal_ll_spi_master_module_num(SPI_MODULE_1)},
+    #endif
+    #ifdef SPI2_MOSI_PE7
+    {PE7, hal_ll_spi_master_module_num(SPI_MODULE_2)},
+    #endif
+
+    { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR }
+    //------------ END MOSI
+};
+
+/*!< @brief SPI MASTER SS pins */
+__weak static const hal_ll_spi_master_pin_map_t _spi_ss_map[] = {
+    //------------ BEGIN SS
+    #ifdef SPI0_SS_PB0
+    {PB0, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI0_SS_PB4
+    {PB4, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI0_SS_PB2
+    {PB2, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI1_SS_PD6
+    {PD6, hal_ll_spi_master_module_num(SPI_MODULE_1)},
+    #endif
+    #ifdef SPI1_SS_PE2
+    {PE2, hal_ll_spi_master_module_num(SPI_MODULE_1)},
+    #endif
+    #ifdef SPI0_SS_PC4
+    {PC4, hal_ll_spi_master_module_num(SPI_MODULE_0)},
+    #endif
+    #ifdef SPI1_SS_PD4
+    {PD4, hal_ll_spi_master_module_num(SPI_MODULE_1)},
+    #endif
+    #ifdef SPI2_SS_PE4
+    {PE4, hal_ll_spi_master_module_num(SPI_MODULE_2)},
+    #endif
+    #ifdef SPI3_SS_PF4
+    {PF4, hal_ll_spi_master_module_num(SPI_MODULE_3)},
+    #endif
+
+    { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR }
+    //------------ END SS
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_SPI_MASTER_PIN_MAP_H_
+// ---------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/include/tim/hal_ll_tim.h b/targets/avr_8bit/mikroe/avr/include/tim/hal_ll_tim.h
new file mode 100644
index 000000000..92a123f31
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/tim/hal_ll_tim.h
@@ -0,0 +1,182 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_tim.h
+ * @brief Brief file description.
+ */
+
+#ifndef _HAL_LL_TIM_H_
+#define _HAL_LL_TIM_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_ll_target.h"
+
+/**
+ * @brief TIM low level handle.
+ *
+ * The context for storing low level object handler.
+ * User is not to change these values or unexpected behaviour
+ * may occur.
+ */
+typedef struct {
+    handle_t *hal_ll_tim_handle;
+    handle_t *hal_drv_tim_handle;
+    bool init_ll_state;
+} hal_ll_tim_handle_register_t;
+
+/**
+ * @brief Registers handler for future use.
+ *
+ * Registers low level and hal level handlers
+ * for use with appropriate functions.
+ *
+ * @param[in] pin TIM pin.
+ * @param[in] *handle_map HAL layer local handle map.
+ * @param[in] *hal_module_id HAL layer module number.
+ *
+ * @return hal_ll_err_t Module specific error.
+ *
+ * Returns one of pre-defined error values.
+ * Take into consideration that this is hardware specific.
+ */
+hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map,
+                                         uint8_t *hal_module_id );
+
+/**
+ * @brief Configures specified module.
+ *
+ * Performs module configuration on the hardware
+ * level. Enables module specific clock gate and
+ * sets adequate alternate function values.
+ *
+ * @param[in] *handle HAL context object handle.
+ *
+ * @return  hal_ll_err_t Module specific error.
+ *
+ * Returns one of pre-defined values.
+ * Take into consideration that this is hardware specific.
+ */
+hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle );
+
+/**
+ * @brief Enables counter for TIM module.
+ *
+ * Initializes TIM module on hardware level, if not already initialized and
+ * starts TIM module.
+ *
+ * @param[in] *handle HAL context object handle.
+ *
+ * @return hal_ll_err_t Module specific error.
+ *
+ * Returns one of pre-defined error values.
+ * Take into consideration that this is hardware specific.
+ */
+hal_ll_err_t hal_ll_tim_start( handle_t *handle );
+
+/**
+ * @brief Stops counter for TIM module.
+ *
+ * The TIM Module needs to be initialized so that
+ * the stop can be done.
+ *
+ * @param[in] *handle HAL context object handle.
+ *
+ * @return hal_ll_err_t Module specific error.
+ *
+ * Returns one of pre-defined error values.
+ * Take into consideration that this is hardware specific.
+ */
+hal_ll_err_t hal_ll_tim_stop( handle_t *handle );
+
+/**
+ * @brief Set TIM frequency in Hertz.
+ *
+ * This function is used to set the TIM frequency, it
+ * stops TIM module and sets duty_cycle on 0.
+ * Take into consideration that the module
+ * will be re-initialized on the hardware level.
+ *
+ * @param[in] *handle HAL context object handle.
+ * @param[in] freq_hz TIM frequency in hz.
+ *
+ * @return This function returns the frequency value in hz,
+ *         to which the PWM module is set.
+ *
+ * @note If the frequency value is less than allowed,
+ *       the frequency will be set to the lowest possible value for the specified TIM.
+ */
+uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz );
+
+/**
+ * @brief Set TIM duty cycle in percentages.
+ *
+ * The user should enter the duty_ratio in percentages.
+ * The dut_ratio value should be between 0 and 1
+ * (where 0 represents 0% and 1 represents 100%).
+ *
+ * @param[in] *handle HAL context object handle.
+ * @param[in] duty_ratio TIM duty ratio in percentages.
+ *
+ * @return hal_ll_err_t Module specific error.
+ *
+ * @note  Returns one of pre-defined error values.
+ *        Take into consideration that this is hardware specific.
+ */
+hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio );
+
+/**
+ * @brief Closes TIM master HAL and HAL_LOW_LEVEL context object.
+ *
+ * De-allocates hardware resources for specific driver object and
+ * de-initializes the module on a hardware level.
+ *
+ * @param[in] handle TIM handle.
+ *
+ * @return void None.
+ */
+void hal_ll_tim_close( handle_t *handle );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_TIM_H_
diff --git a/targets/avr_8bit/mikroe/avr/include/tim/hal_ll_tim_pin_map.h b/targets/avr_8bit/mikroe/avr/include/tim/hal_ll_tim_pin_map.h
new file mode 100644
index 000000000..8ff816bc8
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/tim/hal_ll_tim_pin_map.h
@@ -0,0 +1,360 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*
+
+  This file is part of mikroSDK.
+
+  Copyright (c) 2022, MikroElektonika - www.mikroe.com
+
+  All rights reserved.
+
+-------------------------------------------------------------------------- */
+/*!
+ * @file  hal_ll_tim_pin_map.h
+ * @brief CCP/TIM HAL LOW LEVEL PIN MAPS.
+ */
+
+#ifndef _HAL_LL_TIM_PIN_MAP_H_
+#define _HAL_LL_TIM_PIN_MAP_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_ll_pin_names.h"
+
+/*!< @brief Helper macro for getting adequate module index number */
+#define hal_ll_tim_module_num(_module_num) (_module_num - 1)
+
+/*!< @brief Macro defining `weak` attribute */
+#define __weak __attribute__((weak))
+
+/*!< @brief Enumeration structure for PWM Channel selection. */
+#define HAL_LL_TIM_CH_A ((uint8_t)0) /* Enable channel A driver for PWM pin. */
+#define HAL_LL_TIM_CH_B ((uint8_t)1) /* Enable channel B driver for PWM pin. */
+#define HAL_LL_TIM_CH_C ((uint8_t)2) /* Enable channel C driver for PWM pin. */
+#define HAL_LL_TIM_CH_D ((uint8_t)3) /* Enable channel D driver for PWM pin. */
+#define HAL_LL_TIM_CH_NONE ((uint8_t)4) /* This field represents standard PWM pin. */
+#define HAL_LL_TIM_CH_DEFAULT (HAL_LL_TIM_CH_NONE) /* Default pin driver. */
+
+/*!< @brief TIM Master pin map structure. */
+typedef struct {
+    hal_ll_pin_name_t pin;
+    uint8_t module_index;
+    uint8_t channel;
+} hal_ll_tim_pin_map_t;
+
+/*!< @brief CCP/TIM pins */
+__weak static const hal_ll_tim_pin_map_t _tim_map[] = {
+    //------------ BEGIN CCP
+    #ifdef TIM2_PB7_CH_A
+    {PB7, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM1_PB6_CH_B
+    {PB6, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM1_PB5_CH_A
+    {PB5, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM0_PB4_CH_A
+    {PB4, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM0_PB4_CH_NONE
+    {PB4, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_DEFAULT},
+    #endif
+    #ifdef TIM1_PB7_CH_C
+    {PB7, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_C},
+    #endif
+    #ifdef TIM2_PB7_CH_NONE
+    {PB7, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_DEFAULT},
+    #endif
+    #ifdef TIM3_PE3_CH_A
+    {PE3, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM3_PE4_CH_B
+    {PE4, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM3_PE5_CH_C
+    {PE5, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_CH_C},
+    #endif
+    #ifdef TIM0_PB7_CH_A
+    {PB7, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM0_PG5_CH_B
+    {PG5, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM2_PB4_CH_A
+    {PB4, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM2_PH6_CH_B
+    {PH6, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM4_PH3_CH_A
+    {PH3, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM4_PH4_CH_B
+    {PH4, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM4_PH5_CH_C
+    {PH5, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_CH_C},
+    #endif
+    #ifdef TIM5_PL3_CH_A
+    {PL3, hal_ll_tim_module_num(TIM_MODULE_5), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM5_PL4_CH_B
+    {PL4, hal_ll_tim_module_num(TIM_MODULE_5), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM5_PL5_CH_C
+    {PL5, hal_ll_tim_module_num(TIM_MODULE_5), HAL_LL_TIM_CH_C},
+    #endif
+    #ifdef TIM0_PB3_CH_A
+    {PB3, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM0_PB4_CH_B
+    {PB4, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM1_PD4_CH_B
+    {PD4, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM1_PD5_CH_A
+    {PD5, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM2_PD6_CH_B
+    {PD6, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM2_PD7_CH_A
+    {PD7, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM3_PB6_CH_A
+    {PB6, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM3_PB7_CH_B
+    {PB7, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM0_PB3_CH_NONE
+    {PB3, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_DEFAULT},
+    #endif
+    #ifdef TIM2_PD7_CH_NONE
+    {PD7, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_DEFAULT},
+    #endif
+    #ifdef TIM0_PD5_CH_B
+    {PD5, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM0_PD6_CH_A
+    {PD6, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM1_PB1_CH_A
+    {PB1, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM1_PB2_CH_B
+    {PB2, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM2_PB3_CH_A
+    {PB3, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM2_PD3_CH_B
+    {PD3, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM0_PD0_CH_B
+    {PD0, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM3_PC6_CH_A
+    {PC6, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM4_PB6_CH_B
+    {PB6, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM4_PC7_CH_A
+    {PC7, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM4_PD7_CH_D
+    {PD7, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_CH_D},
+    #endif
+    #ifdef TIM4_PB7_CH_B
+    {PB7, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM4_PC4_CH_A
+    {PC4, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM3_PD0_CH_A
+    {PD0, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM3_PD2_CH_B
+    {PD2, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM4_PD1_CH_A
+    {PD1, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM4_PD2_CH_B
+    {PD2, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM0_PC0_CH_A
+    {PC0, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM0_PC1_CH_B
+    {PC1, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM0_PC2_CH_C
+    {PC2, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_C},
+    #endif
+    #ifdef TIM0_PC3_CH_D
+    {PC3, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_D},
+    #endif
+    #ifdef TIM0_PC4_CH_A
+    {PC4, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM0_PC5_CH_B
+    {PC5, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM0_PC6_CH_C
+    {PC6, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_C},
+    #endif
+    #ifdef TIM0_PC7_CH_D
+    {PC7, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_D},
+    #endif
+    #ifdef TIM1_PC4_CH_A
+    {PC4, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM1_PC5_CH_B
+    {PC5, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM1_PD0_CH_A
+    {PD0, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM1_PD1_CH_B
+    {PD1, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM1_PD2_CH_C
+    {PD2, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_C},
+    #endif
+    #ifdef TIM1_PD3_CH_D
+    {PD3, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_D},
+    #endif
+    #ifdef TIM2_PE0_CH_A
+    {PE0, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM2_PE1_CH_B
+    {PE1, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM2_PE2_CH_C
+    {PE2, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_C},
+    #endif
+    #ifdef TIM2_PE3_CH_D
+    {PE3, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_D},
+    #endif
+    #ifdef TIM3_PF0_CH_A
+    {PF0, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM3_PF1_CH_B
+    {PF1, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM3_PF2_CH_C
+    {PF2, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_CH_C},
+    #endif
+    #ifdef TIM3_PF3_CH_D
+    {PF3, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_CH_D},
+    #endif
+    #ifdef TIM5_PD4_CH_A
+    {PD4, hal_ll_tim_module_num(TIM_MODULE_5), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM5_PD5_CH_B
+    {PD5, hal_ll_tim_module_num(TIM_MODULE_5), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM6_PE4_CH_A
+    {PE4, hal_ll_tim_module_num(TIM_MODULE_6), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM6_PE5_CH_B
+    {PE5, hal_ll_tim_module_num(TIM_MODULE_6), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM7_PF4_CH_A
+    {PF4, hal_ll_tim_module_num(TIM_MODULE_7), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM7_PF5_CH_B
+    {PF5, hal_ll_tim_module_num(TIM_MODULE_7), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM4_PC5_CH_B
+    {PC5, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM1_PD4_CH_A
+    {PD4, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM1_PD5_CH_B
+    {PD5, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM1_PD6_CH_C
+    {PD6, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_C},
+    #endif
+    #ifdef TIM1_PD7_CH_D
+    {PD7, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_D},
+    #endif
+    #ifdef TIM2_PE4_CH_A
+    {PE4, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_A},
+    #endif
+    #ifdef TIM2_PE5_CH_B
+    {PE5, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_B},
+    #endif
+    #ifdef TIM2_PE6_CH_C
+    {PE6, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_C},
+    #endif
+    #ifdef TIM2_PE7_CH_D
+    {PE7, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_D},
+    #endif
+    #ifdef TIM0_PC4_CH_A_ALT
+    {PC4, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_A_ALT},
+    #endif
+    #ifdef TIM0_PC5_CH_B_ALT
+    {PC5, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_B_ALT},
+    #endif
+    #ifdef TIM0_PC6_CH_C_ALT
+    {PC6, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_C_ALT},
+    #endif
+    #ifdef TIM0_PC7_CH_D_ALT
+    {PC7, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_D_ALT},
+    #endif
+
+    { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR }
+    //------------ END CCP
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_TIM_PIN_MAP_H_
+// ---------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/include/uart/hal_ll_uart.h b/targets/avr_8bit/mikroe/avr/include/uart/hal_ll_uart.h
new file mode 100644
index 000000000..6a79bafd8
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/uart/hal_ll_uart.h
@@ -0,0 +1,305 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_uart.h
+ * @brief API for UART HAL LOW LEVEL layer.
+ */
+
+#ifndef _HAL_LL_UART_H_
+#define _HAL_LL_UART_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_ll_target.h"
+
+/**
+ * @brief Interrupt request type enum.
+ */
+typedef enum {
+    HAL_LL_UART_IRQ_RX, /**< RX INT   */
+    HAL_LL_UART_IRQ_TX  /**< TX INT   */
+} hal_ll_uart_irq_t;
+
+/**
+ * @brief Pointer to interrupt handler function.
+ */
+typedef void ( *hal_ll_uart_isr_t )( handle_t handle, hal_ll_uart_irq_t event );
+
+/**
+ * @brief Predefined enum values for parity selection.
+ */
+typedef enum {
+    HAL_LL_UART_PARITY_NONE = 0,
+    HAL_LL_UART_PARITY_EVEN,
+    HAL_LL_UART_PARITY_ODD,
+
+    HAL_LL_UART_PARITY_DEFAULT = HAL_LL_UART_PARITY_NONE
+} hal_ll_uart_parity_t;
+
+/**
+ * @brief Predefined enum values for stop bit selection.
+ * @note: AVR microcontrollers do not utilize half stop and one and a half stop bits.
+ */
+typedef enum {
+    HAL_LL_UART_STOP_BITS_HALF = 0,
+    HAL_LL_UART_STOP_BITS_ONE,
+    HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF,
+    HAL_LL_UART_STOP_BITS_TWO,
+
+    HAL_LL_UART_STOP_BITS_DEFAULT = HAL_LL_UART_STOP_BITS_ONE
+} hal_ll_uart_stop_bits_t;
+
+/**
+ * @brief Predefined enum values for data bit selection.
+ */
+typedef enum {
+    HAL_LL_UART_DATA_BITS_7 = 0,
+    HAL_LL_UART_DATA_BITS_8,
+    HAL_LL_UART_DATA_BITS_9,
+
+    HAL_LL_UART_DATA_BITS_DEFAULT = HAL_LL_UART_DATA_BITS_8
+} hal_ll_uart_data_bits_t;
+
+/**
+ * @brief UART low level pin config structure.
+ *
+ * The context structure for storing low level pin configuration.
+ */
+typedef struct {
+    hal_ll_pin_name_t pin_name;
+    hal_ll_pin_name_t pir_num;
+} hal_ll_pin_pir_t;
+
+/**
+ * @brief UART low level pins config structure.
+ *
+ * The context structure for storing low level pin configuration
+ * for both TX and RX pins.
+ *
+ */
+typedef struct {
+    hal_ll_pin_pir_t tx_pin;
+    hal_ll_pin_pir_t rx_pin;
+} hal_ll_uart_pins_t;
+
+/**
+ * @brief UART low level handle.
+ *
+ * The context for storing low level object handler.
+ * User is not to change these values or unexpected behaviour
+ * may occur.
+ */
+typedef struct {
+    handle_t *hal_ll_uart_handle;
+    handle_t *hal_drv_uart_handle;
+    bool init_ll_state;
+} hal_ll_uart_handle_register_t;
+
+/**
+ * @brief Registers handler for future use.
+ *
+ * Registers low level and hal level handlers
+ * for use with appropriate functions.
+ *
+ * @param[in] tx_pin UART TX pin.
+ * @param[in] rx_pin UART RX pin.
+ * @param[in] *handle_map HAL layer local handle map.
+ * @param[in] *hal_module_id HAL layer module number.
+
+ * @return hal_ll_err_t Module specific error.
+ *
+ * Returns one of pre-defined values.
+ * Take into consideration that this is hardware specific.
+ */
+hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id );
+
+/**
+ * @brief Configures specified module.
+ *
+ * Performs module configuration on the hardware
+ * level. Enables module specific clock gate and
+ * sets adequate alternate function values.
+ *
+ * @param[in] *handle HAL context object handle.
+ *
+ * @return hal_ll_err_t Module specific error.
+ *
+ * Returns one of pre-defined values.
+ * Take into consideration that this is hardware specific.
+ */
+hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle );
+
+/**
+ * @brief Registers interrupt handlers for future use.
+ *
+ * Registers low level interrupt handlers
+ * for use with appropriate functions.
+ *
+ * @param[in] *handle HAL context object handle.
+ * @param[in] handler Predefined pointer function.
+ * @param[in] obj HAL context handle address.
+
+ * @return None.
+ */
+void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj );
+
+/**
+ * @brief Sets desired baud rate.
+ *
+ * Initializes module with specified baud rate value.
+ * Take into consideration that if the difference
+ * between desired baud rate and actual baud
+ * rate the hw was initialized to is greater than
+ * 1%, baud rate shall not be set.
+ * If this occurs, return value shall be
+ * the error percentage.
+ *
+ * @param[in] *handle HAL context object handle.
+ * @param[in] baud Desired baud rate value in Bits/s.
+ *
+ * @return Actual baud rate value the hw module was initialized to,
+ *              or module specific error value if init failed.
+ */
+hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud );
+
+/**
+ * @brief Sets desired parity.
+ *
+ * Initializes module with specified parity value.
+ *
+ * @param[in] *handle HAL context object handle.
+ * @param[in] parity One of pre-defined values.
+ *
+ * @return Re-init module state. If neccessary.
+ */
+hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity );
+
+/**
+ * @brief Sets desired stop bits.
+ *
+ * Initializes module with specified stop bits value.
+ *
+ * @param[in] *handle HAL context object handle.
+ * @param[in] stop_bit One of pre-defined values.
+ *
+ * @return Re-init module state. If neccessary.
+ */
+hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit );
+
+/**
+ * @brief Sets desired data bits.
+ *
+ * Initializes module with specified data bits value.
+ *
+ * @param[in] *handle HAL context object handle.
+ * @param[in] data_bit One of pre-defined values.
+ *
+ * @return Re-init module state. If neccessary.
+ */
+hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit );
+
+/**
+ * @brief Enables module specific interrupt.
+ *
+ * Enables module specific interrupt and registers
+ * interrupt on hardware level and enables it.
+ *
+ * @param[in] *handle HAL context object handle.
+ * @param[in] irq Chip interrupt IRQ value.
+ *
+ * @return void None.
+ */
+void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq );
+
+/**
+ * @brief Disables module specific interrupt.
+ *
+ * Disables module specific interrupt.
+ *
+ * @param[in] *handle HAL context object handle.
+ * @param[in] irq Chip interrupt IRQ value.
+ *
+ * @return void None.
+ */
+void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq );
+
+/**
+ * @brief Performs read operation.
+ *
+ * Reads one byte on a hardware level.
+ *
+ * @param[in] *handle HAL context object handle.
+ *
+ * @return uint16_t Data read from hw register.
+ */
+uint16_t hal_ll_uart_read( handle_t *handle );
+
+/**
+ * @brief Performs write operation.
+ *
+ * Accesses hardware data registers and
+ * writes data directly to it.
+ *
+ * @param[in] *handle HAL context object handle.
+ * @param[in] wr_data Data to be written.
+ *
+ * @return void None.
+ */
+void hal_ll_uart_write( handle_t *handle, uint8_t wr_data);
+
+/**
+ * @brief Closes UART HAL and HAL_LOW_LEVEL context object.
+ *
+ * De-allocates hardware resources for specific driver object and
+ * de-initializes the module on a hardware level.
+ *
+ * @param[in] *handle HAL context object handle.
+ *
+ * @return void None.
+ */
+void hal_ll_uart_close( handle_t *handle );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_UART_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/include/uart/hal_ll_uart_pin_map.h b/targets/avr_8bit/mikroe/avr/include/uart/hal_ll_uart_pin_map.h
new file mode 100644
index 000000000..c7f2cb1f2
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/include/uart/hal_ll_uart_pin_map.h
@@ -0,0 +1,216 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*
+
+  This file is part of mikroSDK.
+
+  Copyright (c) 2022, MikroElektonika - www.mikroe.com
+
+  All rights reserved.
+
+-------------------------------------------------------------------------- */
+/*!
+ * @file  hal_ll_uart_pin_map.h
+ * @brief UART HAL LOW LEVEL PIN MAPS.
+ */
+
+#ifndef _HAL_LL_UART_PIN_MAP_H_
+#define _HAL_LL_UART_PIN_MAP_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "hal_ll_pin_names.h"
+
+/*!< @brief Helper macro for getting adequate module index number */
+#define hal_ll_uart_module_num(_module_num) (_module_num - 1)
+
+/*!< @brief Macro defining `weak` attribute */
+#define __weak __attribute__((weak))
+
+/*!< @brief Pin structure */
+typedef struct {
+    hal_ll_pin_name_t pin;
+    uint8_t module_index;
+    bool alternate;
+} hal_ll_uart_pin_map_t;
+
+/*!< @brief UART TX pins */
+__weak static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = {
+    //------------ BEGIN TX
+    #ifdef USART0_TXD_PE1
+    {PE1, hal_ll_uart_module_num(UART_MODULE_0), false},
+    #endif
+    #ifdef USART1_TXD_PD3
+    {PD3, hal_ll_uart_module_num(UART_MODULE_1), false},
+    #endif
+    #ifdef USART2_TXD_PH1
+    {PH1, hal_ll_uart_module_num(UART_MODULE_2), false},
+    #endif
+    #ifdef USART3_TXD_PJ1
+    {PJ1, hal_ll_uart_module_num(UART_MODULE_3), false},
+    #endif
+    #ifdef USART0_TXD_PD1
+    {PD1, hal_ll_uart_module_num(UART_MODULE_0), false},
+    #endif
+    #ifdef USART_TXD_PD1
+    {PD1, hal_ll_uart_module_num(UART_MODULE_0), false},
+    #endif
+    #ifdef USART2_TXD_PE3
+    {PE3, hal_ll_uart_module_num(UART_MODULE_2), false},
+    #endif
+    #ifdef USART1_TXD_PB3
+    {PB3, hal_ll_uart_module_num(UART_MODULE_1), false},
+    #endif
+    #ifdef USARTC0_TXD_PC3
+    {PC3, hal_ll_uart_module_num(UART_MODULE_C0), false},
+    #endif
+    #ifdef USARTC0_TXD_PC7_ALT
+    {PC7, hal_ll_uart_module_num(UART_MODULE_C0), true},
+    #endif
+    #ifdef USARTC1_TXD_PC7
+    {PC7, hal_ll_uart_module_num(UART_MODULE_C1), false},
+    #endif
+    #ifdef USARTD0_TXD_PD3
+    {PD3, hal_ll_uart_module_num(UART_MODULE_D0), false},
+    #endif
+    #ifdef USARTD1_TXD_PD7
+    {PD7, hal_ll_uart_module_num(UART_MODULE_D1), false},
+    #endif
+    #ifdef USARTE0_TXD_PE3
+    {PE3, hal_ll_uart_module_num(UART_MODULE_E0), false},
+    #endif
+    #ifdef USARTE1_TXD_PE7
+    {PE7, hal_ll_uart_module_num(UART_MODULE_E1), false},
+    #endif
+    #ifdef USARTF0_TXD_PF3
+    {PF3, hal_ll_uart_module_num(UART_MODULE_F0), false},
+    #endif
+    #ifdef USARTF1_TXD_PF7
+    {PF7, hal_ll_uart_module_num(UART_MODULE_F1), false},
+    #endif
+    #ifdef USARTD0_TXD_PD7_ALT
+    {PD7, hal_ll_uart_module_num(UART_MODULE_D0), true},
+    #endif
+    #ifdef USARTE0_TXD_PE7_ALT
+    {PE7, hal_ll_uart_module_num(UART_MODULE_E0), true},
+    #endif
+    #ifdef USARTF0_TXD_PF7_ALT
+    {PF7, hal_ll_uart_module_num(UART_MODULE_F0), true},
+    #endif
+
+    { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC }
+    //------------ END TX
+};
+
+/*!< @brief UART RX pins */
+__weak static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = {
+    //------------ BEGIN RX
+    #ifdef USART0_RXD_PE0
+    {PE0, hal_ll_uart_module_num(UART_MODULE_0), false},
+    #endif
+    #ifdef USART1_RXD_PD2
+    {PD2, hal_ll_uart_module_num(UART_MODULE_1), false},
+    #endif
+    #ifdef USART2_RXD_PH0
+    {PH0, hal_ll_uart_module_num(UART_MODULE_2), false},
+    #endif
+    #ifdef USART3_RXD_PJ0
+    {PJ0, hal_ll_uart_module_num(UART_MODULE_3), false},
+    #endif
+    #ifdef USART0_RXD_PD0
+    {PD0, hal_ll_uart_module_num(UART_MODULE_0), false},
+    #endif
+    #ifdef USART_RXD_PD0
+    {PD0, hal_ll_uart_module_num(UART_MODULE_0), false},
+    #endif
+    #ifdef USART2_RXD_PE2
+    {PE2, hal_ll_uart_module_num(UART_MODULE_2), false},
+    #endif
+    #ifdef USART1_RXD_PB4
+    {PB4, hal_ll_uart_module_num(UART_MODULE_1), false},
+    #endif
+    #ifdef USARTC0_RXD_PC2
+    {PC2, hal_ll_uart_module_num(UART_MODULE_C0), false},
+    #endif
+    #ifdef USARTC0_RXD_PC6_ALT
+    {PC6, hal_ll_uart_module_num(UART_MODULE_C0), true},
+    #endif
+    #ifdef USARTC1_RXD_PC6
+    {PC6, hal_ll_uart_module_num(UART_MODULE_C1), false},
+    #endif
+    #ifdef USARTD0_RXD_PD2
+    {PD2, hal_ll_uart_module_num(UART_MODULE_D0), false},
+    #endif
+    #ifdef USARTD1_RXD_PD6
+    {PD6, hal_ll_uart_module_num(UART_MODULE_D1), false},
+    #endif
+    #ifdef USARTE0_RXD_PE2
+    {PE2, hal_ll_uart_module_num(UART_MODULE_E0), false},
+    #endif
+    #ifdef USARTE1_RXD_PE6
+    {PE6, hal_ll_uart_module_num(UART_MODULE_E1), false},
+    #endif
+    #ifdef USARTF0_RXD_PF2
+    {PF2, hal_ll_uart_module_num(UART_MODULE_F0), false},
+    #endif
+    #ifdef USARTF1_RXD_PF6
+    {PF6, hal_ll_uart_module_num(UART_MODULE_F1), false},
+    #endif
+    #ifdef USARTD0_RXD_PD6_ALT
+    {PD6, hal_ll_uart_module_num(UART_MODULE_D0), true},
+    #endif
+    #ifdef USARTE0_RXD_PE6_ALT
+    {PE6, hal_ll_uart_module_num(UART_MODULE_E0), true},
+    #endif
+    #ifdef USARTF0_RXD_PF6_ALT
+    {PF6, hal_ll_uart_module_num(UART_MODULE_F0), true},
+    #endif
+
+    { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC }
+    //------------ END RX
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_UART_PIN_MAP_H_
+// ---------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/src/adc/CMakeLists.txt b/targets/avr_8bit/mikroe/avr/src/adc/CMakeLists.txt
new file mode 100644
index 000000000..13da486c1
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/adc/CMakeLists.txt
@@ -0,0 +1,72 @@
+set(hal_ll_def_list "")
+
+if((${CORE_NAME} MATCHES "GT64K") OR (${CORE_NAME} MATCHES "LTE64K"))
+    list(APPEND hal_ll_def_list "__avr_8_bit__")
+else()
+    list(APPEND hal_ll_def_list "__family_not_supported__")
+endif()
+
+list(APPEND hal_ll_def_list ${MCU_NAME})
+
+if (${MCU_NAME} MATCHES "^ATXMEGA(.+)$")
+    set(adc_subimplementation "implementation_2/hal_ll_adc.c")
+elseif (${MCU_NAME} MATCHES "^AT([^X])(.+)$")
+    set(adc_subimplementation "implementation_1/hal_ll_adc.c")
+else()
+    message(FATAL_ERROR "MCU not supported")
+endif()
+
+mikrosdk_add_library(lib_hal_ll_adc MikroSDK.HalLowLevel.ADC
+    ${adc_subimplementation}
+    ../../include/hal_ll_target.h
+# BEGIN ADC
+    ../../include/adc/hal_ll_adc.h
+    ../../include/adc/${adc_pin_map}/hal_ll_analog_in_map.h
+# END ADC
+)
+
+list(APPEND hal_ll_def_list "HAL_LL_ADC_RESOLUTION_CMAKE=HAL_LL_ADC_RESOLUTION_10_BIT")
+
+string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH)
+MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3")
+MATH(EXPR BEGIN_INDEX_5TH "${MEMAKE_MCU_NAME_LENGTH}-5")
+MATH(EXPR BEGIN_INDEX_4TH "${MEMAKE_MCU_NAME_LENGTH}-4")
+string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3)
+string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_5TH} 1 MCU_NAME_5TH_CHAR)
+string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_4TH} 1 MCU_NAME_4TH_CHAR)
+string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_5TH} 5 MCU_NAME_LAST5_CHARS)
+
+list(APPEND hal_ll_def_list "MACRO_USAGE_ADC")
+
+target_compile_definitions(lib_hal_ll_adc PUBLIC
+    ${hal_ll_def_list}
+)
+
+target_link_libraries(lib_hal_ll_adc PUBLIC
+    MikroC.Core
+    MikroSDK.HalLowLevelCore
+    MikroSDK.HalLowLevelCommon
+)
+string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER)
+target_include_directories(lib_hal_ll_adc
+    PRIVATE
+        ../../include
+        ../../include/gpio
+        ../../include/adc
+    INTERFACE
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include>
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio>
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc>
+        $<INSTALL_INTERFACE:include/hal_ll_port>
+        $<INSTALL_INTERFACE:include/${MCU_NAME_LOWER}>
+)
+
+mikrosdk_install(MikroSDK.HalLowLevel.ADC)
+
+install(
+    FILES
+        ../../include/adc/hal_ll_adc.h
+        ../../include/adc/hal_ll_analog_in_map.h
+    DESTINATION
+        ${CMAKE_INSTALL_PREFIX}/include/hal_ll_port
+)
diff --git a/targets/avr_8bit/mikroe/avr/src/adc/implementation_1/hal_ll_adc.c b/targets/avr_8bit/mikroe/avr/src/adc/implementation_1/hal_ll_adc.c
new file mode 100644
index 000000000..aff8c8115
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/adc/implementation_1/hal_ll_adc.c
@@ -0,0 +1,411 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_adc.c
+ * @brief Low level HAL ADC source file.
+ */
+
+#include "hal_ll_adc.h"
+#include "hal_ll_gpio.h"
+#include "hal_ll_analog_in_map.h"
+
+// ------------------------------------------------------------- PRIVATE MACROS
+/*!< @brief Helper macro for getting hal_ll_module_state address */
+#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle)
+/*!< @brief Helper macro for getting module specific control register structure base address // first register address */
+#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle
+/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */
+#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\
+                                            (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base
+#define hal_ll_adc_get_base_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_get_handle)->hal_ll_adc_handle))->base
+/*!< @brief Helper macro for getting module specific control register structure */
+#define hal_ll_adc_get_base_struct(_handle) ((const hal_ll_adc_base_handle_t *)_handle)
+
+/*!< @brief Macros defining register bit location */
+#define HAL_LL_ADC_ADCSRA_ADSC_BIT     (6)
+#define HAL_LL_ADC_ADCSRA_ADEN         (0x80)
+#define HAL_LL_ADC_ADCSRA_ADPS         (0x7)
+
+/*!< @brief Macros defining register specific bit masks */
+#define HAL_LL_ADC_ADMUX_MASK          (0xFF)
+
+/*!< @brief Macros defining voltage reference related values */
+#define HAL_LL_ADC_ADMUX_REFS_INTERNAL (0xC0)
+#define HAL_LL_ADC_INTERNAL_VREF_VALUE (2.56)
+
+// -------------------------------------------------------------- PRIVATE TYPES
+/*!< @brief Local handle list */
+static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false };
+
+/*!< @brief ADC register structure. */
+typedef struct {
+    uint8_t adcl;
+    uint8_t adch;
+    uint8_t adcsra;
+    uint8_t admux;
+} hal_ll_adc_base_handle_t;
+
+/**
+ * @brief ADC low level specific structure.
+ *
+ * User is not to change these values or unexpected behaviour
+ * may occur.
+ */
+typedef struct
+{
+    const hal_ll_adc_base_handle_t *base;
+    hal_ll_pin_name_t module_index;
+    hal_ll_pin_name_t pin;
+    hal_ll_adc_voltage_reference_t vref_input;
+    float vref_value;
+    uint16_t resolution;
+    uint8_t channel;
+} hal_ll_adc_hw_specifics_map_t;
+
+/**
+ *  Return values
+ */
+typedef enum {
+    HAL_LL_ADC_SUCCESS = 0,
+    HAL_LL_ADC_WRONG_PIN,
+
+    HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100,
+    HAL_LL_ADC_UNSUPPORTED_VREF,
+    HAL_LL_ADC_WRONG_CHANNEL,
+    HAL_LL_ADC_ERROR = (-1)
+} hal_ll_adc_err_t;
+
+// ------------------------------------------------------------------ CONSTANTS
+/*!< @brief ADC modules register array */
+static const hal_ll_adc_base_handle_t hal_ll_adc_regs[ ADC_MODULE_COUNT + 1 ] = {
+    #ifdef ADC_MODULE_0
+    { HAL_LL_ADC0_ADCL_REG_ADDRESS, HAL_LL_ADC0_ADCH_REG_ADDRESS, HAL_LL_ADC0_ADCSRA_REG_ADDRESS, HAL_LL_ADC0_ADMUX_REG_ADDRESS },
+    #endif
+
+    { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR }
+};
+
+static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[ADC_MODULE_COUNT + 1] = {
+    #ifdef ADC_MODULE_0
+    { &hal_ll_adc_regs[ hal_ll_adc_module_num( ADC_MODULE_0 )], hal_ll_adc_module_num(ADC_MODULE_0), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_10_BIT, 0xFF },
+    #endif
+
+    { &hal_ll_adc_regs[ hal_ll_adc_module_num( ADC_MODULE_COUNT )], HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_10_BIT, 0xFF }
+};
+
+// ------------------------------------------------------------------ VARIABLES
+/*!< @brief Global handle variables used in functions */
+static volatile hal_ll_adc_handle_register_t *low_level_handle;
+static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local;
+
+// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS
+/**
+  * @brief  Initialize ADC module.
+  * @param  *map - ADC module local map.
+  * @return None
+  */
+static void hal_ll_adc_init(hal_ll_adc_hw_specifics_map_t *map);
+
+/**
+  * @brief  Check if pins are adequate.
+  *
+  * Checks analog pin the user has passed with pre-defined
+  * pins in ADC pin map.
+  *
+  * @param[in]  pin - ADC pre-defined pin name.
+  * @param[in]  *index  Pointer with ADC pin map index value.
+  * @param[in]  *handle_map  ADC low level handle pointer.
+  * @return hal_ll_pin_name_t Module index based on pins.
+  *
+  * Returns pre-defined module index from pin maps, if pin
+  * is adequate.
+  */
+static hal_ll_pin_name_t hal_ll_adc_check_pins(hal_ll_pin_name_t pin, uint8_t *index, hal_ll_adc_handle_register_t *handle_map);
+
+/**
+  * @brief  Maps new-found module specific values.
+  *
+  * Maps pin name, register address and channel.
+  *
+  * @param[in]  module_index ADC HW module index -- 0,1,2...
+  * @param[in]  *index  Pointer with ADC pin map index value
+  *
+  * @return  None
+  */
+static void hal_ll_adc_map_pin(uint8_t module_index, uint8_t *index);
+
+/**
+  * @brief  Get local hardware specific map.
+  *
+  * Checks handle value and returns address of adequate
+  * hal_ll_adc_hw_specifics_map array index.
+  *
+  * @param[in]  handle - Object specific context handler.
+  * @return hal_ll_adc_hw_specifics_map_t Map address.
+  *
+  * Returns pre-defined map index address based on handle value,
+  * if handle is adequate.
+  */
+static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle);
+
+/**
+  * @brief  Initialize ADC module.
+  * @param  *base - ADC module base address.
+  * @return None
+  */
+static void _hal_ll_adc_hw_init(hal_ll_adc_hw_specifics_map_t *map);
+
+// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS
+hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) {
+    uint8_t pin_check_result;
+    uint8_t index;
+
+    if ( HAL_LL_PIN_NC == (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) ) {
+        return HAL_LL_ADC_WRONG_PIN;
+    };
+
+    switch ( resolution )
+    {
+        case HAL_LL_ADC_RESOLUTION_10_BIT:
+            hal_ll_adc_hw_specifics_map[pin_check_result].resolution = HAL_LL_ADC_RESOLUTION_10_BIT;
+            break;
+
+        default:
+            return HAL_LL_ADC_UNSUPPORTED_RESOLUTION;
+    }
+
+    switch ( vref_input )
+    {
+        case HAL_LL_ADC_VREF_INTERNAL:
+            hal_ll_adc_hw_specifics_map[pin_check_result].vref_input = HAL_LL_ADC_VREF_INTERNAL;
+            break;
+        case HAL_LL_ADC_VREF_EXTERNAL:
+            hal_ll_adc_hw_specifics_map[pin_check_result].vref_input = HAL_LL_ADC_VREF_EXTERNAL;
+            break;
+        case HAL_LL_ADC_VREF_DEFAULT:
+            hal_ll_adc_hw_specifics_map[pin_check_result].vref_input = HAL_LL_ADC_VREF_DEFAULT;
+            break;
+        default:
+            return HAL_LL_ADC_UNSUPPORTED_VREF;
+    }
+
+    if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin )
+    {
+        hal_ll_adc_map_pin( pin_check_result, &index );
+
+        handle_map[pin_check_result]->init_ll_state = false;
+    }
+
+    *hal_module_id = pin_check_result;
+
+    hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base;
+
+    handle_map[pin_check_result]->hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle;
+
+    return HAL_LL_ADC_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_module_configure_adc(handle_t *handle) {
+    hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address);
+    uint8_t pin_check_result;
+    uint8_t index;
+
+    if ( HAL_LL_PIN_NC == (pin_check_result = hal_ll_adc_check_pins( hal_ll_adc_hw_specifics_map_local->pin, &index, (void *)0 ) ) )
+    {
+        return HAL_LL_ADC_WRONG_PIN;
+    };
+
+    hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local );
+
+    hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base;
+    hal_ll_module_state[pin_check_result].init_ll_state = true;
+
+    return HAL_LL_ADC_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) {
+    low_level_handle = hal_ll_adc_get_handle;
+    hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address);
+
+    low_level_handle->init_ll_state = false;
+
+    switch ( resolution ) {
+        case HAL_LL_ADC_RESOLUTION_10_BIT:
+            hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_10_BIT;
+            break;
+
+        default:
+            return HAL_LL_ADC_UNSUPPORTED_RESOLUTION;
+    }
+
+    hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local );
+
+    low_level_handle->init_ll_state = true;
+
+    return HAL_LL_ADC_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) {
+    low_level_handle = hal_ll_adc_get_handle;
+
+    low_level_handle->init_ll_state = false;
+
+    switch( vref_input ) {
+        case HAL_LL_ADC_VREF_INTERNAL:
+            hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_INTERNAL;
+            break;
+        case HAL_LL_ADC_VREF_EXTERNAL:
+            hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_EXTERNAL;
+            break;
+        case HAL_LL_ADC_VREF_DEFAULT:
+            hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT;
+            break;
+        default:
+            return HAL_LL_ADC_UNSUPPORTED_VREF;
+    }
+
+    hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local );
+
+    low_level_handle->init_ll_state = true;
+
+    return HAL_LL_ADC_SUCCESS;
+}
+
+void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) {
+    low_level_handle = hal_ll_adc_get_handle;
+    hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address);
+
+    if( HAL_LL_ADC_VREF_INTERNAL == hal_ll_adc_hw_specifics_map_local->vref_input ) {
+        hal_ll_adc_hw_specifics_map_local->vref_value = HAL_LL_ADC_INTERNAL_VREF_VALUE;
+    } else {
+        hal_ll_adc_hw_specifics_map_local->vref_value = vref_value;
+    }
+}
+
+hal_ll_err_t hal_ll_adc_read(handle_t *handle, uint16_t *readDatabuf) {
+    const hal_ll_adc_base_handle_t *base = hal_ll_adc_get_base_handle;
+
+    uint16_t volatile adcl_var = 0, adch_var = 0;
+
+    set_reg_bit( base->adcsra, HAL_LL_ADC_ADCSRA_ADSC_BIT ); // ADSC - ADC Start Conversion bit
+    while( check_reg_bit( base->adcsra, HAL_LL_ADC_ADCSRA_ADSC_BIT )); // Wait for conversion to end
+
+    // Documentation: "ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion."
+    adcl_var = read_reg( base->adcl );
+    adch_var = ( read_reg( base->adch )) << 8;
+    *readDatabuf = ( adch_var | adcl_var );
+
+    return HAL_LL_ADC_SUCCESS;
+}
+
+void hal_ll_adc_close(handle_t *handle) {
+    hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address);
+    low_level_handle = hal_ll_adc_get_handle;
+
+    if( HAL_LL_MODULE_ERROR != hal_ll_adc_hw_specifics_map_local->base->adcl ) {
+
+        hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT;
+        hal_ll_adc_hw_specifics_map_local->vref_value = 0;
+        hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_10_BIT;
+
+        low_level_handle->hal_ll_adc_handle = NULL;
+        low_level_handle->hal_drv_adc_handle = NULL;
+
+        low_level_handle->init_ll_state = false;
+
+        hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC;
+    }
+}
+
+// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS
+
+static hal_ll_pin_name_t hal_ll_adc_check_pins(hal_ll_pin_name_t pin, uint8_t *index, hal_ll_adc_handle_register_t *handle_map) {
+    uint8_t pin_index = 0;
+    static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) );
+
+    if ( HAL_LL_PIN_NC == pin ) {
+        return HAL_LL_PIN_NC;
+    }
+
+    for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) {
+        if ( _adc_map[pin_index].pin == pin ) {
+            *index = pin_index;
+            return _adc_map[ pin_index ].module_index;
+        }
+    }
+
+    return HAL_LL_PIN_NC;
+}
+
+static void hal_ll_adc_map_pin(uint8_t module_index, uint8_t *index) {
+    // Map new pins
+    hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[*index ].pin;
+    hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ *index ].channel;
+}
+
+static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) {
+    uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t));
+    static uint8_t hal_ll_module_error = hal_ll_module_count;
+
+    while ( hal_ll_module_count-- ) {
+        if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) {
+            return &hal_ll_adc_hw_specifics_map[hal_ll_module_count];
+        }
+    }
+
+    return &hal_ll_adc_hw_specifics_map[hal_ll_module_error];
+}
+
+static void _hal_ll_adc_hw_init( hal_ll_adc_hw_specifics_map_t *map ) {
+    const hal_ll_adc_base_handle_t *base = hal_ll_adc_get_base_struct(map->base);
+
+    clear_reg_bits( base->admux, HAL_LL_ADC_ADMUX_MASK );
+    write_reg( base->adcsra, HAL_LL_ADC_ADCSRA_ADEN | HAL_LL_ADC_ADCSRA_ADPS );
+}
+
+static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) {
+    const hal_ll_adc_base_handle_t *base = hal_ll_adc_get_base_struct(map->base);
+
+    _hal_ll_adc_hw_init( map );
+    if( HAL_LL_ADC_VREF_INTERNAL == map->vref_input )
+        set_reg_bits( base->admux, HAL_LL_ADC_ADMUX_REFS_INTERNAL );
+    set_reg_bits( base->admux, map->channel );
+}
+
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/src/adc/implementation_2/hal_ll_adc.c b/targets/avr_8bit/mikroe/avr/src/adc/implementation_2/hal_ll_adc.c
new file mode 100644
index 000000000..f61755b74
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/adc/implementation_2/hal_ll_adc.c
@@ -0,0 +1,623 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_adc.c
+ * @brief Low level HAL ADC source file.
+ */
+
+#include "hal_ll_adc.h"
+#include "hal_ll_gpio.h"
+#include "hal_ll_analog_in_map.h"
+
+// ------------------------------------------------------------- PRIVATE MACROS
+/*!< @brief Helper macro for getting hal_ll_module_state address */
+#define hal_ll_adc_get_module_state_address ((hal_ll_adc_handle_register_t *)*handle)
+/*!< @brief Helper macro for getting module specific control register structure base address // first register address */
+#define hal_ll_adc_get_handle (hal_ll_adc_handle_register_t *)hal_ll_adc_get_module_state_address->hal_ll_adc_handle
+/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */
+#define hal_ll_adc_get_base_from_hal_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_handle_register_t *)\
+                                            (((hal_ll_adc_handle_register_t *)(handle))->hal_ll_adc_handle))->hal_ll_adc_handle)->base
+#define hal_ll_adc_get_base_handle ((hal_ll_adc_hw_specifics_map_t *)((hal_ll_adc_get_handle)->hal_ll_adc_handle))->base
+/*!< @brief Helper macro for getting module specific control register structure */
+#define hal_ll_adc_get_base_struct(_handle) ((const hal_ll_adc_base_handle_t *)_handle)
+
+/*!< @brief Macros defining channel specific setting values. */
+#define HAL_LL_ADC_CH_CTRL_SINGLEENDED    (0x01)
+#define HAL_LL_ADC_CH_MUXCTRL_SHIFT       (3)
+#define HAL_LL_ADC_CH_CTRL_START          (7)
+#define HAL_LL_ADC_CH_INTFLAGS_IF         (0)
+#define HAL_LL_ADC_CH_0                   (0)
+#define HAL_LL_ADC_CH_1                   (1)
+#define HAL_LL_ADC_CH_2                   (2)
+#define HAL_LL_ADC_CH_3                   (3)
+
+/*!< @brief Macros defining control register values. */
+#define HAL_LL_ADC_CTRLA_ENABLE           (0x01)
+#define HAL_LL_ADC_CTRLB_RESOLUTION_12BIT (0x00)
+#define HAL_LL_ADC_CTRLB_RESOLUTION_8BIT  (0x04)
+
+/*!< @brief Macros defining voltage reference setting values. */
+#define HAL_LL_ADC_REFCTRL_INTVCC         (0x10)
+#define HAL_LL_ADC_REFCTRL_AREFA          (0x20)
+#define HAL_LL_ADC_REFCTRL_AREFB_D        (0x30)
+
+/*!< @brief Macros defining ADC prescaler values. */
+#define HAL_LL_ADC_PRESCALER_4            (0)
+#define HAL_LL_ADC_PRESCALER_8            (1)
+#define HAL_LL_ADC_PRESCALER_16           (2)
+#define HAL_LL_ADC_PRESCALER_32           (3)
+#define HAL_LL_ADC_PRESCALER_64           (4)
+#define HAL_LL_ADC_PRESCALER_128          (5)
+#define HAL_LL_ADC_PRESCALER_256          (6)
+#define HAL_LL_ADC_PRESCALER_512          (7)
+
+// -------------------------------------------------------------- PRIVATE TYPES
+/*!< @brief Local handle list */
+static hal_ll_adc_handle_register_t hal_ll_module_state[ADC_MODULE_COUNT] = { (handle_t *) NULL, (handle_t *) NULL, false };
+
+/*!< @brief ADC register structure. */
+typedef struct {
+    uint16_t ctrla;
+    uint16_t ctrlb;
+    uint16_t refctrl;
+    uint16_t evctrl;
+    uint16_t prescaler;
+} adc_regs_t;
+
+/*!< @brief ADC channel register structure. */
+typedef struct {
+    uint16_t ch_ctrl;
+    uint16_t ch_muxctrl;
+    uint16_t ch_intctrl;
+    uint16_t ch_intflags;
+    uint16_t ch_resl;
+    uint16_t ch_resh;
+} chn_regs_t;
+
+/*!< @brief ADC and channel specific register structure. */
+typedef struct {
+    adc_regs_t adc_regs;
+//  NOTE: XMEGA A and XMEGA AU have 4 ADC channels.
+//  In order to use channels other than CH0, replace [1] with [4].
+    chn_regs_t chn_regs[1];
+} hal_ll_adc_base_handle_t;
+
+/*!< @brief ADC hw specific structure. */
+typedef struct {
+    const hal_ll_adc_base_handle_t *base;
+    hal_ll_pin_name_t module_index;
+    hal_ll_pin_name_t pin;
+    hal_ll_adc_voltage_reference_t vref_input;
+    float vref_value;
+    uint16_t resolution;
+    uint8_t channel;
+} hal_ll_adc_hw_specifics_map_t;
+
+/*!< @brief ADC return values. */
+typedef enum {
+    HAL_LL_ADC_SUCCESS = 0,
+    HAL_LL_ADC_WRONG_PIN,
+
+    HAL_LL_ADC_UNSUPPORTED_RESOLUTION = 1100,
+    HAL_LL_ADC_UNSUPPORTED_VREF,
+    HAL_LL_ADC_WRONG_CHANNEL,
+    HAL_LL_ADC_ERROR = (-1)
+} hal_ll_adc_err_t;
+
+// ------------------------------------------------------------------ CONSTANTS
+/*
+ * In order to use ADC channels CH1, CH2 or CH3, `hal_ll_adc_regs` elements must be appended with adequate registers:
+ * HAL_LL_ADCx_CHnCTRL_REG_ADDRESS, HAL_LL_ADCx_CHnMUXCTRL_REG_ADDRESS, HAL_LL_ADCx_CHnINTCTRL_REG_ADDRESS, HAL_LL_ADCx_CHnINTFLAGS_REG_ADDRESS,
+ * where n = {1, 2, 3} is the number of ADC channel.
+ */
+/*!< @brief ADC modules register array */
+static const hal_ll_adc_base_handle_t hal_ll_adc_regs[ ADC_MODULE_COUNT + 1 ] = {
+    #ifdef ADC_MODULE_0
+    { HAL_LL_ADC0_CTRLA_REG_ADDRESS, HAL_LL_ADC0_CTRLB_REG_ADDRESS, HAL_LL_ADC0_REFCTRL_REG_ADDRESS, HAL_LL_ADC0_EVCTRL_REG_ADDRESS,
+      HAL_LL_ADC0_PRESCALER_REG_ADDRESS, HAL_LL_ADC0_CH0CTRL_REG_ADDRESS, HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS, HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS,
+      HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS, HAL_LL_ADC0_CH0RESL_REG_ADDRESS, HAL_LL_ADC0_CH0RESH_REG_ADDRESS },
+    #endif
+    #ifdef ADC_MODULE_1
+    { HAL_LL_ADC1_CTRLA_REG_ADDRESS, HAL_LL_ADC1_CTRLB_REG_ADDRESS, HAL_LL_ADC1_REFCTRL_REG_ADDRESS, HAL_LL_ADC1_EVCTRL_REG_ADDRESS,
+      HAL_LL_ADC1_PRESCALER_REG_ADDRESS, HAL_LL_ADC1_CH0CTRL_REG_ADDRESS, HAL_LL_ADC1_CH0MUXCTRL_REG_ADDRESS, HAL_LL_ADC1_CH0INTCTRL_REG_ADDRESS,
+      HAL_LL_ADC1_CH0INTFLAGS_REG_ADDRESS, HAL_LL_ADC1_CH0RESL_REG_ADDRESS, HAL_LL_ADC1_CH0RESH_REG_ADDRESS },
+    #endif
+
+    { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR,
+      HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR }
+};
+
+static hal_ll_adc_hw_specifics_map_t hal_ll_adc_hw_specifics_map[ ADC_MODULE_COUNT + 1 ] = {
+    #ifdef ADC_MODULE_0
+    { &hal_ll_adc_regs[ hal_ll_adc_module_num( ADC_MODULE_0 )], hal_ll_adc_module_num( ADC_MODULE_0 ), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF },
+    #endif
+    #ifdef ADC_MODULE_1
+    { &hal_ll_adc_regs[ hal_ll_adc_module_num( ADC_MODULE_1 )], hal_ll_adc_module_num( ADC_MODULE_1 ), HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF },
+    #endif
+
+    { &hal_ll_adc_regs[ hal_ll_adc_module_num( ADC_MODULE_COUNT )], HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_ADC_VREF_DEFAULT, 0, HAL_LL_ADC_RESOLUTION_12_BIT, 0xFF }
+};
+
+// ------------------------------------------------------------------ VARIABLES
+/*!< @brief Global handle variables used in functions */
+static volatile hal_ll_adc_handle_register_t *low_level_handle;
+static volatile hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local;
+
+// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS
+/**
+  * @brief  Initialize ADC module.
+  * @param  *map - ADC module local map.
+  * @return None
+  */
+static void hal_ll_adc_init(hal_ll_adc_hw_specifics_map_t *map);
+
+/**
+  * @brief  Check if pins are adequate.
+  *
+  * Checks analog pin the user has passed with pre-defined
+  * pins in ADC pin map.
+  *
+  * @param[in]  pin - ADC pre-defined pin name.
+  * @param[in] *index Array with ADC pin map index values.
+  * @param[in] *handle_map Structure with info about available ADC modules.
+  * @return hal_ll_pin_name_t Module index based on pins.
+  *
+  * Returns pre-defined module index from pin maps, if pin
+  * is adequate.
+  */
+static hal_ll_pin_name_t hal_ll_adc_check_pins(hal_ll_pin_name_t pin, uint8_t *index, hal_ll_adc_handle_register_t *handle_map);
+
+/**
+  * @brief  Maps new-found module specific values.
+  *
+  * Maps pin name, register address and channel.
+  *
+  * @param[in]  module_index ADC HW module index -- 0,1,2...
+  * @param[in]  *index  Pointer with ADC pin map index value
+  *
+  * @return  None
+  */
+static void hal_ll_adc_map_pin(uint8_t module_index, uint8_t *index);
+
+/**
+  * @brief  Get local hardware specific map.
+  *
+  * Checks handle value and returns address of adequate
+  * hal_ll_adc_hw_specifics_map array index.
+  *
+  * @param[in]  handle - Object specific context handler.
+  * @return hal_ll_adc_hw_specifics_map_t Map address.
+  *
+  * Returns pre-defined map index address based on handle value,
+  * if handle is adequate.
+  */
+static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle);
+
+/**
+  * @brief  Set voltage reference source.
+  *
+  * Checks external vref pins and
+  * sets voltage reference source.
+  *
+  * @param[in] *map - ADC module local map.
+  * @param[in] index - ADC module map index value.
+  * @param[in] vref_input - ADC reference voltage source.
+  * @return  hal_ll_err_t Module specific error.
+  *
+  * Returns pre-defined map index address based on handle value,
+  * if handle is adequate.
+  */
+static hal_ll_err_t hal_ll_adc_check_vref_input(hal_ll_adc_hw_specifics_map_t *map, uint8_t index, hal_ll_adc_voltage_reference_t vref_input);
+
+/**
+  * @brief  Set voltage reference.
+  *         NOTE: XMEGA microcontrollers have 2 pins for external voltage reference.
+  *               Pin PB0 (PD0 for XMEGA E family) is set as default vref pin.
+  *               In case that pin is used as analog input, vref is switched to PA0.
+  *               If selected microcontroller doesn't have PA0, function `hal_ll_adc_register_handle`
+  *               will return `HAL_LL_ADC_UNSUPPORTED_VREF` error.
+  * @param  *map - ADC module local map.
+  * @return None
+  */
+static void hal_ll_adc_set_vref_bare_metal(hal_ll_adc_hw_specifics_map_t *map);
+
+/**
+  * @brief  Set resolution.
+  * @param  *map - ADC module local map.
+  * @return None
+  */
+static void hal_ll_adc_set_resolution_bare_metal(hal_ll_adc_hw_specifics_map_t *map);
+
+/**
+  * @brief  Initialize ADC module.
+  * @param  *map - ADC module local.
+  * @return None
+  */
+static void hal_ll_adc_hw_init(hal_ll_adc_hw_specifics_map_t *map);
+
+// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS
+hal_ll_err_t hal_ll_adc_register_handle(hal_ll_pin_name_t pin, hal_ll_adc_voltage_reference_t vref_input, hal_ll_adc_resolution_t resolution, hal_ll_adc_handle_register_t *handle_map, uint8_t *hal_module_id) {
+    uint8_t pin_check_result;
+    uint8_t index;
+
+    if ( HAL_LL_PIN_NC == (pin_check_result = hal_ll_adc_check_pins( pin, &index, handle_map )) ) {
+        return HAL_LL_ADC_WRONG_PIN;
+    };
+
+    switch ( resolution ) {
+        case HAL_LL_ADC_RESOLUTION_8_BIT:
+            hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_8_BIT;
+            break;
+        case HAL_LL_ADC_RESOLUTION_12_BIT:
+            hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT;
+            break;
+
+        default:
+            return HAL_LL_ADC_UNSUPPORTED_RESOLUTION;
+    }
+
+    if ( hal_ll_adc_hw_specifics_map[pin_check_result].pin != pin )
+    {
+        hal_ll_adc_map_pin( pin_check_result, &index );
+
+        handle_map[pin_check_result]->init_ll_state = false;
+    }
+
+    if ( HAL_LL_ADC_UNSUPPORTED_VREF == hal_ll_adc_check_vref_input( hal_ll_adc_hw_specifics_map, pin_check_result, vref_input )) {
+        return HAL_LL_ADC_UNSUPPORTED_VREF;
+    }
+
+    *hal_module_id = pin_check_result;
+
+    hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base;
+
+    handle_map[pin_check_result]->hal_ll_adc_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_adc_handle;
+
+    return HAL_LL_ADC_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_module_configure_adc(handle_t *handle) {
+    hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address);
+    uint8_t pin_check_result;
+    uint8_t index;
+
+    if ( HAL_LL_PIN_NC == (pin_check_result = hal_ll_adc_check_pins( hal_ll_adc_hw_specifics_map_local->pin, &index, (void *)0 ) ) )
+    {
+        return HAL_LL_ADC_WRONG_PIN;
+    };
+
+    hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local );
+
+    hal_ll_module_state[pin_check_result].hal_ll_adc_handle = (handle_t *)&hal_ll_adc_hw_specifics_map[pin_check_result].base;
+    hal_ll_module_state[pin_check_result].init_ll_state = true;
+
+    return HAL_LL_ADC_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_adc_set_resolution(handle_t *handle, hal_ll_adc_resolution_t resolution) {
+    low_level_handle = hal_ll_adc_get_handle;
+    hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address);
+
+    low_level_handle->init_ll_state = false;
+
+    switch ( resolution ) {
+        case HAL_LL_ADC_RESOLUTION_8_BIT:
+            hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_8_BIT;
+            break;
+        case HAL_LL_ADC_RESOLUTION_12_BIT:
+            hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT;
+            break;
+
+        default:
+            return HAL_LL_ADC_UNSUPPORTED_RESOLUTION;
+    }
+
+    hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local );
+
+    low_level_handle->init_ll_state = true;
+
+    return HAL_LL_ADC_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_adc_set_vref_input(handle_t *handle, hal_ll_adc_voltage_reference_t vref_input) {
+    low_level_handle = hal_ll_adc_get_handle;
+
+    low_level_handle->init_ll_state = false;
+
+    if ( HAL_LL_ADC_UNSUPPORTED_VREF == hal_ll_adc_check_vref_input( hal_ll_adc_hw_specifics_map_local, hal_ll_adc_hw_specifics_map_local->module_index, vref_input )) {
+        return HAL_LL_ADC_UNSUPPORTED_VREF;
+    }
+
+    hal_ll_adc_init( hal_ll_adc_hw_specifics_map_local );
+
+    low_level_handle->init_ll_state = true;
+
+    return HAL_LL_ADC_SUCCESS;
+}
+
+void hal_ll_adc_set_vref_value(handle_t *handle, float vref_value) {
+    low_level_handle = hal_ll_adc_get_handle;
+    hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address);
+
+    if( HAL_LL_ADC_VREF_INTERNAL == hal_ll_adc_hw_specifics_map_local->vref_input ) {
+        hal_ll_adc_hw_specifics_map_local->vref_value = (float) ( vref_value / 1.6 );
+    } else {
+        hal_ll_adc_hw_specifics_map_local->vref_value = vref_value;
+    }
+}
+
+hal_ll_err_t hal_ll_adc_read(handle_t *handle, uint16_t *readDatabuf) {
+    hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_adc_get_module_state_address );
+    const hal_ll_adc_base_handle_t *base = hal_ll_adc_get_base_handle;
+    volatile uint16_t resl, resh, analog_input;
+
+    analog_input = hal_ll_adc_hw_specifics_map_local->channel;
+
+    write_reg( base->chn_regs[HAL_LL_ADC_CH_0].ch_ctrl, HAL_LL_ADC_CH_CTRL_SINGLEENDED ); // Single-ended mode
+
+    write_reg( base->chn_regs[HAL_LL_ADC_CH_0].ch_muxctrl, analog_input << HAL_LL_ADC_CH_MUXCTRL_SHIFT ); // Analog input select
+
+    clear_reg( base->chn_regs[HAL_LL_ADC_CH_0].ch_intctrl ); // Disable interrupt mode
+
+    set_reg_bit( base->chn_regs[HAL_LL_ADC_CH_0].ch_ctrl, HAL_LL_ADC_CH_CTRL_START ); // Start conversion
+
+    while( !( check_reg_bit( base->chn_regs[HAL_LL_ADC_CH_0].ch_intflags, HAL_LL_ADC_CH_INTFLAGS_IF ))); // Wait until IF flag is 1
+
+    set_reg_bit( base->chn_regs[HAL_LL_ADC_CH_0].ch_intflags, HAL_LL_ADC_CH_INTFLAGS_IF ); // Clear IF flag by writing 1
+
+    resl = read_reg( base->chn_regs[HAL_LL_ADC_CH_0].ch_resl );
+    resh = read_reg( base->chn_regs[HAL_LL_ADC_CH_0].ch_resh );
+
+    *readDatabuf = resl | ( resh << 8 );
+
+    /*
+     * From documentation:
+     * "The approximate value corresponding to ground is around 200.
+     *  This value corresponds to the digital result of ∆V (0.05 * 4095).
+     *  ∆V exists to allow zero-crossing detection."
+     *
+     * This formula is used to map converted values from range [200-4095] to [0-4095] with 12 bit resolution.
+     * (x - in_min) * (out_max - out_min) / (in_max - in_min) + out_min
+     *        x - converted value
+     *   in_min - 200
+     *   in_max - 4095
+     *  out_min - 0
+     *  out_max - 4095
+     *
+     * Uncomment the code below if you want to avoid zero-crossing.
+     */
+    //BEGIN
+    /*
+    volatile uint16_t res, out_max;
+    float mul, lower_limit;
+    if( HAL_LL_ADC_RESOLUTION_12_BIT == hal_ll_adc_hw_specifics_map_local->resolution ) {
+        out_max = 4095;
+    } else if ( HAL_LL_ADC_RESOLUTION_8_BIT == hal_ll_adc_hw_specifics_map_local->resolution ) {
+        out_max = 255;
+    }
+
+    res = resl | ( resh << 8 );
+    lower_limit = (float)( 0.05 * out_max );
+    mul = (float)( out_max / ( out_max - lower_limit ));
+    if( res >= lower_limit ) {
+        *readDatabuf = (( resl | ( resh << 8 )) - lower_limit ) * mul;
+    } else {
+        *readDatabuf = 0;
+    }
+    */
+    //END
+
+    return HAL_LL_ADC_SUCCESS;
+}
+
+void hal_ll_adc_close(handle_t *handle) {
+    hal_ll_adc_hw_specifics_map_t *hal_ll_adc_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_adc_get_module_state_address);
+    low_level_handle = hal_ll_adc_get_handle;
+
+    if( HAL_LL_MODULE_ERROR != hal_ll_adc_hw_specifics_map_local->base->adc_regs.ctrla ||
+        HAL_LL_MODULE_ERROR != hal_ll_adc_hw_specifics_map_local->base->chn_regs[HAL_LL_ADC_CH_0].ch_ctrl ) {
+
+        hal_ll_adc_hw_specifics_map_local->vref_input = HAL_LL_ADC_VREF_DEFAULT;
+        hal_ll_adc_hw_specifics_map_local->vref_value = 0;
+        hal_ll_adc_hw_specifics_map_local->resolution = HAL_LL_ADC_RESOLUTION_12_BIT;
+
+        low_level_handle->hal_ll_adc_handle = NULL;
+        low_level_handle->hal_drv_adc_handle = NULL;
+
+        low_level_handle->init_ll_state = false;
+
+        hal_ll_adc_hw_specifics_map_local->pin = HAL_LL_PIN_NC;
+    }
+}
+
+// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS
+
+static hal_ll_pin_name_t hal_ll_adc_check_pins(hal_ll_pin_name_t pin, uint8_t *index, hal_ll_adc_handle_register_t *handle_map) {
+    uint8_t pin_index = 0;
+    static const uint16_t adc_map_size = ( sizeof( _adc_map ) / sizeof( hal_ll_adc_pin_map_t ) );
+
+    if ( HAL_LL_PIN_NC == pin ) {
+        return HAL_LL_PIN_NC;
+    }
+
+    for ( pin_index = 0; pin_index < adc_map_size; pin_index++ ) {
+        if ( _adc_map[pin_index].pin == pin ) {
+            *index = pin_index;
+            return _adc_map[ pin_index ].module_index;
+        }
+    }
+
+    return HAL_LL_PIN_NC;
+}
+
+static void hal_ll_adc_map_pin(uint8_t module_index, uint8_t *index) {
+    // Map new pins
+    hal_ll_adc_hw_specifics_map[module_index].pin = _adc_map[*index ].pin;
+    hal_ll_adc_hw_specifics_map[module_index].channel = _adc_map[ *index ].channel;
+    hal_ll_adc_hw_specifics_map[module_index].module_index = _adc_map[ *index ].module_index;
+}
+
+static hal_ll_adc_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle) {
+    uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_adc_handle_register_t));
+    static uint8_t hal_ll_module_error = hal_ll_module_count;
+
+    while ( hal_ll_module_count-- ) {
+        if (hal_ll_adc_get_base_from_hal_handle == hal_ll_adc_hw_specifics_map[hal_ll_module_count].base) {
+            return &hal_ll_adc_hw_specifics_map[hal_ll_module_count];
+        }
+    }
+
+    return &hal_ll_adc_hw_specifics_map[hal_ll_module_error];
+}
+
+static void hal_ll_adc_set_resolution_bare_metal(hal_ll_adc_hw_specifics_map_t *map) {
+    const hal_ll_adc_base_handle_t *base = hal_ll_adc_get_base_struct(map->base);
+
+    /*
+     * CTRLB_RESOLUTION[2:1]
+     * 00 -> 12-bit, right adjusted
+     * 01 -> reserved
+     * 10 -> 8-bit, right adjusted
+     * 11 -> 12-bit, left adjusted
+     */
+    if( HAL_LL_ADC_RESOLUTION_12_BIT == map->resolution ) {
+        write_reg( base->adc_regs.ctrlb, HAL_LL_ADC_CTRLB_RESOLUTION_12BIT );
+    } else if( HAL_LL_ADC_RESOLUTION_8_BIT == map->resolution ) {
+        write_reg( base->adc_regs.ctrlb, HAL_LL_ADC_CTRLB_RESOLUTION_8BIT );
+    }
+}
+
+static hal_ll_err_t hal_ll_adc_check_vref_input(hal_ll_adc_hw_specifics_map_t *map, uint8_t index, hal_ll_adc_voltage_reference_t vref_input) {
+    const hal_ll_adc_base_handle_t *base = hal_ll_adc_get_base_struct(map->base);
+
+    switch ( vref_input )
+    {
+        case HAL_LL_ADC_VREF_INTERNAL:
+            hal_ll_adc_hw_specifics_map[index].vref_input = HAL_LL_ADC_VREF_INTERNAL;
+            break;
+        case HAL_LL_ADC_VREF_EXTERNAL:
+            #ifdef PB0
+            // Check if PB0 is being used as analog input pin.
+            if( PB0 == hal_ll_adc_hw_specifics_map[index].pin ) {
+                #ifndef PA0
+                return HAL_LL_ADC_UNSUPPORTED_VREF;
+                #else
+                hal_ll_adc_hw_specifics_map[index].vref_input = HAL_LL_ADC_VREF_EXTERNAL;
+                #endif
+            } else {
+                hal_ll_adc_hw_specifics_map[index].vref_input = HAL_LL_ADC_VREF_EXTERNAL;
+            }
+            #elif defined (PD0)
+            // Check if PD0 is being used as analog input pin.
+            if( PD0 == hal_ll_adc_hw_specifics_map[index].pin ) {
+                #ifndef PA0
+                return HAL_LL_ADC_UNSUPPORTED_VREF;
+                #else
+                hal_ll_adc_hw_specifics_map[index].vref_input = HAL_LL_ADC_VREF_EXTERNAL;
+                #endif
+            } else {
+                hal_ll_adc_hw_specifics_map[index].vref_input = HAL_LL_ADC_VREF_EXTERNAL;
+            }
+            #else
+                return HAL_LL_ADC_UNSUPPORTED_VREF;
+            #endif
+            break;
+        case HAL_LL_ADC_VREF_DEFAULT:
+            hal_ll_adc_hw_specifics_map[index].vref_input = HAL_LL_ADC_VREF_DEFAULT;
+            break;
+
+        default:
+            return HAL_LL_ADC_UNSUPPORTED_VREF;
+    }
+}
+
+static void hal_ll_adc_set_vref_bare_metal(hal_ll_adc_hw_specifics_map_t *map) {
+    const hal_ll_adc_base_handle_t *base = hal_ll_adc_get_base_struct(map->base);
+
+    /*
+     * REFCTRL_REFSEL[6:4]:
+     * 001 -> Internal Vcc/1.6V
+     * 010 -> External reference on PORTA
+     * 011 -> External reference on PORTB (PORTD on XMEGA E chips)
+     * 100 -> Internal Vcc/2V (not supported on XMEGA A)
+     */
+    if( HAL_LL_ADC_VREF_INTERNAL == map->vref_input ) {
+        write_reg( base->adc_regs.refctrl, HAL_LL_ADC_REFCTRL_INTVCC ); // Vcc/1.6V
+    } else if( HAL_LL_ADC_VREF_EXTERNAL == map->vref_input ) {
+         #ifdef PB0
+        // Check if PB0 is being used as analog input pin.
+        if( PB0 != map->pin ) {
+            write_reg( base->adc_regs.refctrl, HAL_LL_ADC_REFCTRL_AREFB_D ); // PB0
+        } else {
+            #ifdef PA0
+            write_reg( base->adc_regs.refctrl, HAL_LL_ADC_REFCTRL_AREFA ); // PA0
+            #endif
+        }
+        #elif defined (PD0)
+        // Check if PD0 is being used as analog input pin.
+        if( PD0 != map->pin ) {
+            write_reg( base->adc_regs.refctrl, HAL_LL_ADC_REFCTRL_AREFB_D ); // PD0
+        } else {
+            #ifdef PA0
+            write_reg( base->adc_regs.refctrl, HAL_LL_ADC_REFCTRL_AREFA ); // PA0
+            #endif
+        }
+        #endif
+    }
+}
+
+static void hal_ll_adc_hw_init(hal_ll_adc_hw_specifics_map_t *map) {
+    const hal_ll_adc_base_handle_t *base = hal_ll_adc_get_base_struct(map->base);
+
+    write_reg( base->adc_regs.prescaler, HAL_LL_ADC_PRESCALER_8);
+
+    hal_ll_adc_set_resolution_bare_metal( map );
+
+    hal_ll_adc_set_vref_bare_metal( map );
+}
+
+static void hal_ll_adc_init(hal_ll_adc_hw_specifics_map_t *map) {
+    const hal_ll_adc_base_handle_t *base = hal_ll_adc_get_base_struct(map->base);
+
+    hal_ll_adc_hw_init( map );
+
+    write_reg( base->adc_regs.ctrla, HAL_LL_ADC_CTRLA_ENABLE ); // ADC enable
+}
+
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/src/gpio/CMakeLists.txt b/targets/avr_8bit/mikroe/avr/src/gpio/CMakeLists.txt
new file mode 100644
index 000000000..0c9f4aff9
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/gpio/CMakeLists.txt
@@ -0,0 +1,72 @@
+set(hal_ll_def_list "")
+if((${CORE_NAME} MATCHES "GT64K") OR (${CORE_NAME} MATCHES "LTE64K"))
+    list(APPEND hal_ll_def_list "__avr_8_bit__")
+else()
+    list(APPEND hal_ll_def_list "__family_not_supported__")
+endif()
+
+list(APPEND hal_ll_def_list ${MCU_NAME})
+
+string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH)
+MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3")
+string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3)
+MATH(EXPR BEGIN_INDEX_4TH "${MEMAKE_MCU_NAME_LENGTH}-4")
+string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_4TH} 1 MCU_ON_4)
+MATH(EXPR BEGIN_INDEX_4TH "${MEMAKE_MCU_NAME_LENGTH}-5")
+string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_4TH} 1 MCU_ON_5)
+MATH(EXPR BEGIN_INDEX_5TH "${MEMAKE_MCU_NAME_LENGTH}-5")
+string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX_5TH} 5 MCU_NAME_LAST_5)
+
+## BEGIN GPIO
+if ((${MCU_NAME} MATCHES "AT"))
+    set(gpio_implementation "implementation_1")
+    set(gpio_subimplementation "subimplementation_1")
+else()
+    list(APPEND hal_ll_def_list "__hal_ll_gpio_not_supported__")
+endif()
+
+list(APPEND hal_ll_def_list "MACRO_USAGE_GPIO")
+
+mikrosdk_add_library(lib_hal_ll_gpio MikroSDK.HalLowLevel.GPIO
+    ${gpio_implementation}/hal_ll_gpio.c
+    ${gpio_implementation}/${gpio_subimplementation}/hal_ll_gpio_port.c
+    ../../include/hal_ll_target.h
+    ../../include/gpio/hal_ll_gpio.h
+    ../../include/gpio/hal_ll_gpio_port.h
+    ../../include/gpio/hal_ll_gpio_constants.h
+)
+
+target_compile_definitions(lib_hal_ll_gpio PUBLIC
+    ${hal_ll_def_list}
+)
+
+target_link_libraries(lib_hal_ll_gpio PUBLIC
+    MikroC.Core
+    MikroSDK.HalLowLevelCore
+    MikroSDK.HalLowLevelCommon
+)
+
+string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER)
+target_include_directories(lib_hal_ll_gpio
+    PRIVATE
+        ../../include
+        ../../include/gpio
+        ../../include/adc
+    INTERFACE
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include>
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio>
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include/adc>
+        $<INSTALL_INTERFACE:include/hal_ll_port>
+        $<INSTALL_INTERFACE:include/${MCU_NAME_LOWER}>
+)
+
+mikrosdk_install(MikroSDK.HalLowLevel.GPIO)
+
+install(
+    FILES
+        ../../include/gpio/hal_ll_gpio.h
+        ../../include/gpio/hal_ll_gpio_constants.h
+        ../../include/gpio/hal_ll_gpio_port.h
+    DESTINATION
+        ${CMAKE_INSTALL_PREFIX}/include/hal_ll_port
+)
diff --git a/targets/avr_8bit/mikroe/avr/src/gpio/implementation_1/hal_ll_gpio.c b/targets/avr_8bit/mikroe/avr/src/gpio/implementation_1/hal_ll_gpio.c
new file mode 100644
index 000000000..f6090e9e0
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/gpio/implementation_1/hal_ll_gpio.c
@@ -0,0 +1,185 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file hal_ll_port_gpio.c
+ * @brief Low level HAL GPIO source file.
+ */
+
+#include "hal_ll_gpio_port.h"
+
+/*******************************************************************************
+ *
+ */
+void hal_ll_gpio_configure_pin(hal_ll_gpio_pin_t *pin, hal_ll_pin_name_t name, hal_ll_gpio_direction_t direction) {
+    // Get pin base.
+    pin->base = (hal_ll_gpio_base_t)hal_ll_gpio_port_base_map( hal_ll_gpio_port_index ( name ) );
+
+    // Get pin mask.
+    pin->mask = hal_ll_gpio_port_pin_mask( name );
+
+    if ( HAL_LL_GPIO_DIGITAL_INPUT == direction ) {
+        hal_ll_gpio_port_digital_input( pin->base, name );
+    } else if ( HAL_LL_GPIO_DIGITAL_OUTPUT == direction ) {
+        hal_ll_gpio_port_digital_output( pin->base, name );
+    } else {
+        hal_ll_gpio_port_analog_input( pin->base, name );
+    }
+}
+
+/*******************************************************************************
+ *
+ */
+uint8_t hal_ll_gpio_read_pin_input(hal_ll_gpio_pin_t *pin) {
+    hal_ll_gpio_base_handle_t *port_ptr = (hal_ll_gpio_base_handle_t *)pin->base;
+
+    /**
+    * @brief A "NOP" instruction is included because of the fact
+    * a single signal transition on the pin will be delayed between
+    * ½ and 1½ system clock period depending upon the time of assertion.
+    */
+    asm {nop};
+    return ( ( *(uint8_t *)port_ptr->pin_reg_addr ) & pin->mask ) ? 0x01: 0x00;
+}
+
+/*******************************************************************************
+ *
+ */
+uint8_t hal_ll_gpio_read_pin_output(hal_ll_gpio_pin_t *pin) {
+    hal_ll_gpio_base_handle_t *port_ptr = (hal_ll_gpio_base_handle_t *)pin->base;
+
+    /**
+    * @brief A "NOP" instruction is included because of the fact
+    * a single signal transition on the pin will be delayed between
+    * ½ and 1½ system clock period depending upon the time of assertion.
+    */
+    asm {nop};
+    return ( ( *(uint8_t *)port_ptr->port_reg_addr ) & pin->mask ) ? 0x01: 0x00;
+}
+
+/*******************************************************************************
+ *
+ */
+void hal_ll_gpio_write_pin_output(hal_ll_gpio_pin_t *pin, uint8_t value) {
+    hal_ll_gpio_base_handle_t *port_ptr = (hal_ll_gpio_base_handle_t*)pin->base;
+
+    if (value) {
+        *(uint8_t *)port_ptr->port_reg_addr |= pin->mask;
+    } else {
+        *(uint8_t *)port_ptr->port_reg_addr &= ~pin->mask;
+    }
+}
+
+/*******************************************************************************
+ *
+ */
+void hal_ll_gpio_toggle_pin_output(hal_ll_gpio_pin_t *pin) {
+    uint8_t value = hal_ll_gpio_read_pin_output( pin );
+    hal_ll_gpio_write_pin_output( pin, !value );
+}
+
+/*******************************************************************************
+ *
+ */
+void hal_ll_gpio_set_pin_output(hal_ll_gpio_pin_t *pin) {
+    hal_ll_gpio_base_handle_t *port_ptr = (hal_ll_gpio_base_handle_t*)pin->base;
+
+    *(uint8_t *)port_ptr->port_reg_addr |= pin->mask;
+}
+
+/*******************************************************************************
+ *
+ */
+void hal_ll_gpio_clear_pin_output(hal_ll_gpio_pin_t *pin) {
+    hal_ll_gpio_base_handle_t *port_ptr = (hal_ll_gpio_base_handle_t*)pin->base;
+
+    *(uint8_t *)port_ptr->port_reg_addr &= ( ~( pin->mask ) );
+}
+
+/*******************************************************************************
+ *
+ */
+void hal_ll_gpio_configure_port(hal_ll_gpio_port_t *port, hal_ll_port_name_t name, hal_ll_gpio_mask_t mask, hal_ll_gpio_direction_t direction) {
+    if( PORT_COUNT <= name ) {
+        port->base = NULL;
+        port->mask = HAL_LL_PIN_NC;
+    } else {
+        // Get port base.
+        port->base = (hal_ll_gpio_base_t)hal_ll_gpio_port_base_map( name );
+
+        // Get mask of desired pin/s.
+        port->mask = mask;
+    }
+
+    // Check if digital input functionality is needed.
+    if ( HAL_LL_GPIO_DIGITAL_INPUT == direction ) {
+        hal_ll_gpio_port_digital_configure_port(port, name, true);
+    // Otherwise, digital output functionality is needed.
+    } else {
+        hal_ll_gpio_port_digital_configure_port(port, name, false);
+    }
+}
+
+/*******************************************************************************
+ *
+ */
+hal_ll_port_size_t hal_ll_gpio_read_port_input(hal_ll_gpio_port_t *port) {
+    hal_ll_gpio_base_handle_t *port_ptr = (hal_ll_gpio_base_handle_t*)port->base;
+
+    return  ( *( uint8_t *)port_ptr->pin_reg_addr ) & port->mask;
+}
+
+/*******************************************************************************
+ *
+ */
+hal_ll_port_size_t hal_ll_gpio_read_port_output(hal_ll_gpio_port_t *port) {
+    hal_ll_gpio_base_handle_t *port_ptr = (hal_ll_gpio_base_handle_t*)port->base;
+
+    return  ( *( uint8_t *)port_ptr->port_reg_addr ) & port->mask;
+}
+/*******************************************************************************
+ *
+ */
+void hal_ll_gpio_write_port_output(hal_ll_gpio_port_t *port, hal_ll_port_size_t value) {
+    // Get appropriate PORT, DDR and PIN register.
+    hal_ll_gpio_base_handle_t *port_ptr = (hal_ll_gpio_base_handle_t *)port->base;
+
+    // Write user-defined value on port.
+    *(uint8_t *)port_ptr->port_reg_addr = value & port->mask;
+}
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/src/gpio/implementation_1/subimplementation_1/hal_ll_gpio_port.c b/targets/avr_8bit/mikroe/avr/src/gpio/implementation_1/subimplementation_1/hal_ll_gpio_port.c
new file mode 100644
index 000000000..8ea2767a3
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/gpio/implementation_1/subimplementation_1/hal_ll_gpio_port.c
@@ -0,0 +1,285 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file hal_ll_port_gpio.c
+ * @brief Low level HAL GPIO ported source file.
+ */
+
+#include "hal_ll_gpio_port.h"
+#include "hal_ll_analog_in_map.h"
+
+// ------------------------------------------------------------- PRIVATE MACROS
+
+// -------------------------------------------------------------- PRIVATE TYPES
+
+/**
+ *  Defines used in source
+ */
+
+/*!< @brief GPIO PORT null-pointer constants (for non-existant ports) */
+#ifndef __PORT_A_CN
+    #define __PORT_A_CN
+    #define PORTA_REG_ADDRESS NULL
+    #define DDRA_REG_ADDRESS NULL
+    #define PINA_REG_ADDRESS NULL
+#endif
+#ifndef __PORT_B_CN
+    #define __PORT_B_CN
+    #define PORTB_REG_ADDRESS NULL
+    #define DDRB_REG_ADDRESS NULL
+    #define PINB_REG_ADDRESS NULL
+#endif
+#ifndef __PORT_C_CN
+    #define __PORT_C_CN
+    #define PORTC_REG_ADDRESS NULL
+    #define DDRC_REG_ADDRESS NULL
+    #define PINC_REG_ADDRESS NULL
+#endif
+#ifndef __PORT_D_CN
+    #define __PORT_D_CN
+    #define PORTD_REG_ADDRESS NULL
+    #define DDRD_REG_ADDRESS NULL
+    #define PIND_REG_ADDRESS NULL
+#endif
+#ifndef __PORT_E_CN
+    #define __PORT_E_CN
+    #define PORTE_REG_ADDRESS NULL
+    #define DDRE_REG_ADDRESS NULL
+    #define PINE_REG_ADDRESS NULL
+#endif
+#ifndef __PORT_F_CN
+    #define __PORT_F_CN
+    #define PORTF_REG_ADDRESS NULL
+    #define DDRF_REG_ADDRESS NULL
+    #define PINF_REG_ADDRESS NULL
+#endif
+#ifndef __PORT_G_CN
+    #define __PORT_G_CN
+    #define PORTG_REG_ADDRESS NULL
+    #define DDRG_REG_ADDRESS NULL
+    #define PING_REG_ADDRESS NULL
+#endif
+#ifndef __PORT_H_CN
+    #define __PORT_H_CN
+    #define PORTH_REG_ADDRESS NULL
+    #define DDRH_REG_ADDRESS NULL
+    #define PINH_REG_ADDRESS NULL
+#endif
+#ifndef __PORT_J_CN
+    #define __PORT_J_CN
+    #define PORTJ_REG_ADDRESS NULL
+    #define DDRJ_REG_ADDRESS NULL
+    #define PINJ_REG_ADDRESS NULL
+#endif
+#ifndef __PORT_K_CN
+    #define __PORT_K_CN
+    #define PORTK_REG_ADDRESS NULL
+    #define DDRK_REG_ADDRESS NULL
+    #define PINK_REG_ADDRESS NULL
+#endif
+#ifndef __PORT_L_CN
+    #define __PORT_L_CN
+    #define PORTL_REG_ADDRESS NULL
+    #define DDRL_REG_ADDRESS NULL
+    #define PINL_REG_ADDRESS NULL
+#endif
+#ifndef __PORT_R_CN
+    #define __PORT_R_CN
+    #define PORTR_REG_ADDRESS NULL
+    #define DDRR_REG_ADDRESS NULL
+    #define PINR_REG_ADDRESS NULL
+#endif
+
+/*!< @brief GPIO PORT array */
+static hal_ll_gpio_base_handle_t _hal_ll_gpio_port_addresses[] = {
+    #ifdef __PORT_A_CN
+    { PORTA_REG_ADDRESS, DDRA_REG_ADDRESS, PINA_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_B_CN
+    { PORTB_REG_ADDRESS, DDRB_REG_ADDRESS, PINB_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_C_CN
+    { PORTC_REG_ADDRESS, DDRC_REG_ADDRESS, PINC_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_D_CN
+    { PORTD_REG_ADDRESS, DDRD_REG_ADDRESS, PIND_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_E_CN
+    { PORTE_REG_ADDRESS, DDRE_REG_ADDRESS, PINE_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_F_CN
+    { PORTF_REG_ADDRESS, DDRF_REG_ADDRESS, PINF_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_G_CN
+    { PORTG_REG_ADDRESS, DDRG_REG_ADDRESS, PING_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_H_CN
+    { PORTH_REG_ADDRESS, DDRH_REG_ADDRESS, PINH_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_J_CN
+    { PORTJ_REG_ADDRESS, DDRJ_REG_ADDRESS, PINJ_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_K_CN
+    { PORTK_REG_ADDRESS, DDRK_REG_ADDRESS, PINK_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_L_CN
+    { PORTL_REG_ADDRESS, DDRL_REG_ADDRESS, PINL_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_R_CN
+    { PORTR_REG_ADDRESS, DDRR_REG_ADDRESS, PINR_REG_ADDRESS },
+    #endif
+    { HAL_LL_PORT_NC, HAL_LL_PORT_NC, HAL_LL_PORT_NC }
+};
+
+/**
+  * @brief  Configure port pins
+  * @param  port     - port base address
+  *         pin_mask - desired pin
+  *         config   - pin settings
+  * @return none
+  */
+static void hal_ll_gpio_port_config(uint16_t *name, uint8_t pin_mask, uint8_t config);
+
+/**
+  * @brief  Get pin index within a port
+  * @param  name - desired pin
+  * @return uint8_t value from 0 to PORT_SIZE-1
+  */
+static uint8_t hal_ll_gpio_port_pin_index(hal_ll_pin_name_t name) {
+    return ( uint8_t )name % PORT_SIZE;
+}
+
+/**
+  * @brief  Get pins port index within a list of available ports
+  * @param  name - desired pin
+  * @return uint8_t value from 0 to PORT_COUNT-1
+  */
+uint8_t hal_ll_gpio_port_index(hal_ll_pin_name_t name) {
+    return ( uint8_t )name / PORT_SIZE;
+}
+
+/**
+  * @brief  Get pin mask of provided pin within proprietary port
+  * @param  name - desired pin
+  * @return uint8_t
+  */
+uint8_t hal_ll_gpio_port_pin_mask(hal_ll_pin_name_t name) {
+    return ( 0x01 << ( hal_ll_gpio_port_pin_index(name) ) );
+}
+
+/**
+  * @brief  Get map address of port register offsets
+  * @param  name - desired port
+  * @return uint16_t address of first register
+  */
+uint16_t hal_ll_gpio_port_base_map(hal_ll_port_name_t name) {
+    return (hal_ll_gpio_base_t)&_hal_ll_gpio_port_addresses[ hal_ll_gpio_port_pin_index( name ) ];
+}
+
+/**
+  * @brief  Set pin as analog input
+  * @param  port - port base address acquired from hal_gpio_ll_port_base
+  * @param  pin_mask - pin mask acquired from hal_gpio_ll_pin_mask
+  * @return none
+  */
+void hal_ll_gpio_port_analog_input(uint16_t *port, uint8_t pin_mask) {
+    hal_ll_gpio_port_config( port, pin_mask, GPIO_CFG_ANALOG_INPUT );
+}
+
+/**
+  * @brief  Set pin as digital input
+  * @param  port - port base address acquired from hal_gpio_ll_port_base
+  * @param  pin_mask - pin mask acquired from hal_gpio_ll_pin_mask
+  * @return none
+  */
+void hal_ll_gpio_port_digital_input(uint16_t *port, uint8_t pin_mask) {
+    hal_ll_gpio_port_config( port, pin_mask, GPIO_CFG_DIGITAL_INPUT );
+}
+
+void hal_ll_gpio_port_digital_configure_port(hal_ll_gpio_port_t *port, uint8_t name, bool is_input) {
+    // Get appropriate PORT, DDR and PIN register.
+    hal_ll_gpio_base_handle_t *port_ptr = (hal_ll_gpio_base_handle_t *)port->base;
+
+    if (is_input) {
+        *(uint8_t *)port_ptr->ddr_reg_addr &= ~(port->mask);
+    } else {
+        *(uint8_t *)port_ptr->ddr_reg_addr |= port->mask;
+    }
+}
+
+/**
+  * @brief  Set pin as digital output
+  * @param  port - port base address acquired from hal_gpio_ll_port_base
+  * @param  pin_mask - pin mask acquired from hal_gpio_ll_pin_mask
+  * @return none
+  */
+void hal_ll_gpio_port_digital_output(uint16_t *port, uint8_t pin) {
+    hal_ll_gpio_port_config( port, pin, GPIO_CFG_DIGITAL_OUTPUT );
+}
+
+/**
+  * @brief  Configure single port pins
+  * @param  port     - port base address
+  *         pin_mask - desired pin
+  *         config   - pin settings
+  * @return none
+  */
+static void hal_ll_gpio_port_config(uint16_t *port, uint8_t pin, uint8_t config) {
+    // Get appropriate PORT, DDR and PIN register.
+    hal_ll_gpio_base_handle_t *port_ptr = (hal_ll_gpio_base_handle_t *)port;
+
+    // Get pin mask.
+    hal_ll_pin_name_t mask = hal_ll_gpio_port_pin_mask( pin & 0xF );
+
+    if ( GPIO_CFG_DIGITAL_INPUT == config ) {
+        *(uint8_t *)port_ptr->ddr_reg_addr &= ~(mask);
+    }
+    if ( GPIO_CFG_DIGITAL_OUTPUT == config ) {
+        *(uint8_t *)port_ptr->ddr_reg_addr |= mask;
+    }
+    if ( GPIO_CFG_ANALOG_INPUT == config ) {
+        // Clear PORT value (we are making sure pull-up will be disabled for the analog logic)...
+        *(uint8_t *)port_ptr->port_reg_addr &= ~(mask);
+
+        // Set input logic.
+        *(uint8_t *)port_ptr->ddr_reg_addr &= ~(mask);
+    }
+}
+
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/src/hal_ll/CMakeLists.txt b/targets/avr_8bit/mikroe/avr/src/hal_ll/CMakeLists.txt
new file mode 100644
index 000000000..a5ae03fdd
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/hal_ll/CMakeLists.txt
@@ -0,0 +1,21 @@
+add_library(lib_hal_ll INTERFACE)
+add_library(MikroSDK.HalLowLevel ALIAS lib_hal_ll)
+
+set(module_list "")
+set(module_list_supported "")
+set_module_support(module_list module_list_supported ${MCU_NAME} "hal_ll_layer")
+
+target_link_libraries(lib_hal_ll INTERFACE
+    ${module_list}
+)
+
+mikrosdk_install(MikroSDK.HalLowLevel)
+
+install(
+    FILES
+        ../../include/hal_ll_target.h
+        ../../include/hal_ll_pin_names.h
+        ../../include/hal_ll_target_names.h
+    DESTINATION
+        ${CMAKE_INSTALL_PREFIX}/include/hal_ll_port
+)
diff --git a/targets/avr_8bit/mikroe/avr/src/i2c/CMakeLists.txt b/targets/avr_8bit/mikroe/avr/src/i2c/CMakeLists.txt
new file mode 100644
index 000000000..50ddc7f3a
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/i2c/CMakeLists.txt
@@ -0,0 +1,75 @@
+set(hal_ll_def_list "")
+if((${CORE_NAME} MATCHES "GT64K") OR (${CORE_NAME} MATCHES "LTE64K"))
+    list(APPEND hal_ll_def_list "__avr_8_bit__")
+else()
+    list(APPEND hal_ll_def_list "__family_not_supported__")
+endif()
+
+list(APPEND hal_ll_def_list ${MCU_NAME})
+
+string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH)
+MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3")
+string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3)
+
+if ((${MCU_NAME} MATCHES "^ATMEGA(16|32|64)9[AP]?0?[AP]?$") OR (${MCU_NAME} MATCHES "^ATMEGA(16|32|64)[MU][12]$") OR (${MCU_NAME} MATCHES "^ATMEGA(32|64)5[0]?(PA|A|P)?$"))
+    set(i2c_implementation "implementation_3/hal_ll_i2c_master.c")
+elseif (${MCU_NAME} MATCHES "^ATXMEGA(.+)$")
+    set(i2c_implementation "implementation_2/hal_ll_i2c_master.c")
+elseif (${MCU_NAME} MATCHES "^AT([^X])(.+)$")
+    set(i2c_implementation "implementation_1/hal_ll_i2c_master.c")
+else()
+    message(FATAL_ERROR "MCU not supported")
+endif()
+
+list(APPEND hal_ll_def_list "MACRO_USAGE_I2C")
+
+if (NOT DEFINED _MSDK_TFT_TP_)
+    list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__")
+else()
+    if (${_MSDK_TFT_TP_} MATCHES "__TP_TSC2003__")
+        list(APPEND hal_ll_def_list "__TFT_RESISTIVE_TSC2003__")
+    else()
+        list(APPEND hal_ll_def_list "__TFT_NON_TSC2003__")
+    endif()
+endif()
+
+mikrosdk_add_library(lib_hal_ll_i2c_master MikroSDK.HalLowLevel.I2C.Master
+    ${i2c_implementation}
+
+    ../../include/hal_ll_target.h
+    ../../include/i2c/hal_ll_i2c_master.h
+    ../../include/i2c/hal_ll_i2c_pin_map.h
+)
+
+target_compile_definitions(lib_hal_ll_i2c_master PUBLIC
+    ${hal_ll_def_list}
+)
+
+target_link_libraries(lib_hal_ll_i2c_master PUBLIC
+    MikroC.Core
+    MikroSDK.HalLowLevelCore
+    MikroSDK.HalLowLevelCommon
+)
+string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER)
+target_include_directories(lib_hal_ll_i2c_master
+    PRIVATE
+        ../../include
+        ../../include/gpio
+        ../../include/i2c
+    INTERFACE
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include>
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio>
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include/i2c>
+        $<INSTALL_INTERFACE:include/hal_ll_port>
+        $<INSTALL_INTERFACE:include/${MCU_NAME_LOWER}>
+)
+
+mikrosdk_install(MikroSDK.HalLowLevel.I2C.Master)
+
+install(
+    FILES
+        ../../include/i2c/hal_ll_i2c_master.h
+        ../../include/i2c/hal_ll_i2c_pin_map.h
+    DESTINATION
+        ${CMAKE_INSTALL_PREFIX}/include/hal_ll_port
+)
diff --git a/targets/avr_8bit/mikroe/avr/src/i2c/implementation_1/hal_ll_i2c_master.c b/targets/avr_8bit/mikroe/avr/src/i2c/implementation_1/hal_ll_i2c_master.c
new file mode 100644
index 000000000..93c028085
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/i2c/implementation_1/hal_ll_i2c_master.c
@@ -0,0 +1,688 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_i2c_master.c
+ * @brief I2C master HAL LOW LEVEL layer implementation.
+ */
+
+#include "hal_ll_gpio.h"
+#include "hal_ll_i2c_master.h"
+#include "hal_ll_i2c_pin_map.h"
+
+/*!< @brief Local handle list */
+static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false };
+
+// ------------------------------------------------------------- PRIVATE MACROS
+/*!< @brief Helper macro for getting hal_ll_module_state address */
+#define hal_ll_i2c_get_module_state_address (( hal_ll_i2c_master_handle_register_t *)*handle)
+/*!< @brief Helper macro for getting module specific control register structure base address // first register address */
+#define hal_ll_i2c_get_handle  (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle
+/*!< @brief Helper macro for getting module specific control register structure */
+#define hal_ll_i2c_get_base_struct(_handle) ((const hal_ll_i2c_base_handle_t *)_handle)
+/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */
+#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\
+                                            (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base
+
+/*!< @brief Default pass count value upon reset */
+#define HAL_LL_I2C_DEFAULT_PASS_COUNT   (10000)
+
+/*!< @brief Default I2C bit-rate if no speed is set */
+#define HAL_LL_I2C_MASTER_SPEED_100K    (100000UL)
+#define HAL_LL_I2C_MASTER_SPEED_400K    (400000UL)
+
+/*!< @brief Macros defining register bit location */
+#define HAL_LL_I2C_TWCR_TWINT_BIT       (7)
+
+/*!< @brief Macros defining register specific bit masks */
+#define HAL_LL_I2C_TWSR_STATUS_MASK     (0xF8)
+#define HAL_LL_I2C_TWSR_PRESCALER_MASK  (0x03)
+
+/*!< @brief Macros defining control register values */
+#define HAL_LL_I2C_TWCR_START           (0xA4)
+#define HAL_LL_I2C_TWCR_STOP            (0x94)
+#define HAL_LL_I2C_TWCR_TWINT_CLEAR     (0x84)
+#define HAL_LL_I2C_TWCR_SEND_ACK        (0xC4)
+
+/*!< @brief Macros defining status codes for master transmitter and receiver mode */
+#define HAL_LL_I2C_TWSR_DATA_T_ACK      (0x28)
+#define HAL_LL_I2C_TWSR_DATA_R_ACK      (0x50)
+#define HAL_LL_I2C_TWSR_SADDR_W_ACK     (0x18)
+#define HAL_LL_I2C_TWSR_SADDR_R_ACK     (0x40)
+#define HAL_LL_I2C_TWSR_START           (0x08)
+#define HAL_LL_I2C_TWSR_ARB_LOST        (0x38)
+#define HAL_LL_I2C_TWSR_REPEATED_START  (0x10)
+
+// -------------------------------------------------------------- PRIVATE TYPES
+/*!< @brief I2C register structure */
+typedef struct
+{
+    uint16_t twbr;
+    uint16_t twsr;
+    uint16_t twar;
+    uint16_t twdr;
+    uint16_t twcr;
+} hal_ll_i2c_base_handle_t;
+
+/*!< @brief I2C hw specific structure */
+typedef struct
+{
+    const hal_ll_i2c_base_handle_t *base;
+    uint8_t module_index;
+    hal_ll_i2c_pins_t pins;
+    uint32_t speed;
+    uint8_t address;
+    uint16_t timeout;
+} hal_ll_i2c_hw_specifics_map_t;
+
+/*!< @brief I2C hw specific error values */
+typedef enum
+{
+    HAL_LL_I2C_MASTER_SUCCESS = 0,
+    HAL_LL_I2C_MASTER_WRONG_PINS,
+    HAL_LL_I2C_MASTER_MODULE_ERROR,
+
+    HAL_LL_I2C_MASTER_ERROR = (-1)
+} hal_ll_i2c_master_err_t;
+
+/*!< @brief I2C end mode selection values */
+typedef enum
+{
+    HAL_LL_I2C_MASTER_END_MODE_RESTART = 0,
+    HAL_LL_I2C_MASTER_END_MODE_STOP,
+    HAL_LL_I2C_MASTER_WRITE_THEN_READ
+} hal_ll_i2c_master_end_mode_t;
+
+/*!< @brief I2C timeout error values */
+typedef enum
+{
+    HAL_LL_I2C_MASTER_TIMEOUT_START = 1300,
+    HAL_LL_I2C_MASTER_TIMEOUT_STOP,
+    HAL_LL_I2C_MASTER_TIMEOUT_WRITE,
+    HAL_LL_I2C_MASTER_TIMEOUT_READ,
+    HAL_LL_I2C_MASTER_ARBITRATION_LOST,
+    HAL_LL_I2C_MASTER_TIMEOUT_INIT
+} hal_ll_i2c_master_timeout_t;
+
+/**
+ * @brief Enum containing predefined module standard speed values.
+ *
+ * Enum values:
+ * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K
+ * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K
+ */
+typedef enum
+{
+    HAL_LL_I2C_MASTER_SPEED_STANDARD = 0,
+    HAL_LL_I2C_MASTER_SPEED_FULL
+} hal_ll_i2c_master_speed_t;
+
+// ------------------------------------------------------------------ CONSTANTS
+/*!< @brief I2C modules register array */
+static const hal_ll_i2c_base_handle_t hal_ll_i2c_regs[ I2C_MODULE_COUNT + 1 ] = {
+    #if defined (I2C_MODULE_0) && !defined (I2C_MODULE_1)
+    { HAL_LL_TWI_TWBR_REG_ADDRESS, HAL_LL_TWI_TWSR_REG_ADDRESS, HAL_LL_TWI_TWAR_REG_ADDRESS, HAL_LL_TWI_TWDR_REG_ADDRESS, HAL_LL_TWI_TWCR_REG_ADDRESS},
+    #endif
+    #if defined (I2C_MODULE_0) && defined (I2C_MODULE_1)
+    { HAL_LL_TWI0_TWBR0_REG_ADDRESS, HAL_LL_TWI0_TWSR0_REG_ADDRESS, HAL_LL_TWI0_TWAR0_REG_ADDRESS, HAL_LL_TWI0_TWDR0_REG_ADDRESS, HAL_LL_TWI0_TWCR0_REG_ADDRESS},
+    #endif
+    #ifdef I2C_MODULE_1
+    { HAL_LL_TWI1_TWBR1_REG_ADDRESS, HAL_LL_TWI1_TWSR1_REG_ADDRESS, HAL_LL_TWI1_TWAR1_REG_ADDRESS, HAL_LL_TWI1_TWDR1_REG_ADDRESS, HAL_LL_TWI1_TWCR1_REG_ADDRESS},
+    #endif
+
+    { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR }
+};
+
+// ------------------------------------------------------------------ VARIABLES
+/*!< @brief I2C hardware specific info */
+static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[ I2C_MODULE_COUNT + 1 ] = {
+    #ifdef I2C_MODULE_0
+    { &hal_ll_i2c_regs[ hal_ll_i2c_module_num( I2C_MODULE_0 )], hal_ll_i2c_module_num(I2C_MODULE_0), {HAL_LL_PIN_NC,HAL_LL_PIN_NC}, HAL_LL_I2C_MASTER_SPEED_100K, 0, HAL_LL_I2C_DEFAULT_PASS_COUNT },
+    #endif
+    #ifdef I2C_MODULE_1
+    { &hal_ll_i2c_regs[ hal_ll_i2c_module_num( I2C_MODULE_1 )], hal_ll_i2c_module_num(I2C_MODULE_1), {HAL_LL_PIN_NC,HAL_LL_PIN_NC}, HAL_LL_I2C_MASTER_SPEED_100K, 0, HAL_LL_I2C_DEFAULT_PASS_COUNT },
+    #endif
+
+    { &hal_ll_i2c_regs[ hal_ll_i2c_module_num( I2C_MODULE_COUNT )], HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC,HAL_LL_PIN_NC}, 0 , 0, 0}
+};
+
+/*!< @brief Global handle variables used in functions */
+static volatile hal_ll_i2c_master_handle_register_t *low_level_handle;
+static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local;
+
+// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS
+/**
+  * @brief  Check if pins are adequate.
+  *
+  * Checks scl and sda pins the user has passed with pre-defined
+  * pins in scl and sda maps. Take into consideration that module
+  * index numbers have to be the same for both pins.
+  *
+  * @param[in]  scl - SCL pre-defined pin name.
+  * @param[in]  sda - SDA pre-defined pin name.
+  * @param[in]  *index_list - Array with SCL and SDA map index values
+  *
+  * @return hal_ll_pin_name_t Module index based on pins.
+  *
+  * Returns pre-defined module index from pin maps, if pins
+  * are adequate.
+  */
+static hal_ll_pin_name_t hal_ll_i2c_master_check_pins(hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pins_t *index_list, hal_ll_i2c_master_handle_register_t *handle_map);
+
+/**
+  * @brief  Get local hardware specific map.
+  *
+  * Checks handle value and returns address of adequate
+  * hal_ll_i2c_hw_specifics_map array index.
+  *
+  * @param[in]  handle - Object specific context handler.
+  *
+  * @return hal_ll_i2c_hw_specifics_map_t Map address.
+  *
+  * Returns pre-defined map index address based on handle value,
+  * if handle is adequate.
+  */
+static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle);
+
+/**
+  * @brief  Get adequate I2C bit-rate value.
+  *
+  * Returns one of pre-defined bit-rate values,
+  * or the closest bit-rate based on bit_rate
+  * value passed to the function.
+  *
+  * @param[in]  bit_rate - I2C bit rate.
+  *
+  * @return uint32_t Adequate bit-rate value.
+  *
+  * Returns adequate value to be latter written into bare metal register address.
+  * Take into consideration that this returns a predefined value.
+  *
+  * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s
+  * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s
+  */
+static uint32_t hal_ll_i2c_get_speed(uint32_t bit_rate);
+
+/**
+ * @brief  Maps new-found module specific values.
+ *
+ * Maps pin names and alternate function values for
+ * I2C SCL and SDA pins.
+ *
+ * @param[in]  module_index I2C HW module index -- 0,1,2...
+ * @param[in]  *index_list  Array with SCL and SDA map index values
+ *
+ * @return  None
+ */
+static void hal_ll_i2c_master_map_pins(uint8_t module_index, hal_ll_i2c_pins_t *index_list);
+
+/**
+  * @brief  Full I2C module initialization procedure.
+  *
+  * Initializes I2C module on hardware level, based on beforehand
+  * set configuration and module handler. Sets adequate pin alternate functions.
+  * Initializes module clock.
+  *
+  * @param[in]  map - Object specific context handler.
+  *
+  * @return hal_ll_err_t Module specific values.
+  *
+  * Returns one of pre-defined values.
+  * Take into consideration that this is hardware specific.
+  */
+static void hal_ll_i2c_init(hal_ll_i2c_hw_specifics_map_t *map);
+
+/**
+  * @brief  Generates start signal on I2C bus.
+  *
+  * Generates a start signal on the I2C bus.
+  *
+  * @param[in]  map - Object specific context handler.
+  *
+  * @return hal_ll_err_t Module specific values.
+  *
+  * Returns one of pre-defined values.
+  * Take into consideration that this is hardware specific.
+  */
+static hal_ll_err_t hal_ll_i2c_master_start(hal_ll_i2c_hw_specifics_map_t *map);
+
+/**
+  * @brief  Perform a read on the I2C bus.
+  *
+  * Initializes I2C module on hardware level, if not initialized beforehand
+  * and continues to perform a read operation on the bus.
+  *
+  * @param[in]  map - Object specific context handler.
+  * @param[in]  read_data_buf - Pointer to data buffer.
+  * @param[in]  len_read_data - Number of data to be read.
+  *
+  * @return hal_ll_err_t Module specific values.
+  *
+  * Returns one of pre-defined values.
+  * Take into consideration that this is hardware specific.
+  */
+static hal_ll_err_t hal_ll_i2c_master_read_bare_metal(hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode);
+
+/**
+  * @brief  Perform a write on the I2C bus.
+  *
+  * Initializes I2C module on hardware level, if not initialized beforehand
+  * and continues to perform a write operation on the bus.
+  *
+  * @param[in]  map - Object specific context handler.
+  * @param[in]  write_data_buf - Pointer to data buffer.
+  * @param[in]  len_write_data - Number of data to be written.
+  *
+  * @return hal_ll_err_t Module specific values.
+  *
+  * Returns one of pre-defined values.
+  * Take into consideration that this is hardware specific.
+  */
+static hal_ll_err_t hal_ll_i2c_master_write_bare_metal(hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode);
+
+// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS
+hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) {
+    hal_ll_i2c_pins_t index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC};
+    uint16_t pin_check_result;
+
+    if ( HAL_LL_PIN_NC == ( pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map ))) {
+        return HAL_LL_I2C_MASTER_WRONG_PINS;
+    };
+
+    if ( ( hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl != scl ) ||
+         ( hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda != sda ) )
+    {
+        // Map new pins
+        hal_ll_i2c_master_map_pins( pin_check_result, &index_list );
+
+        handle_map[pin_check_result]->init_ll_state = false;
+    }
+
+    *hal_module_id = pin_check_result;
+
+    hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base;
+
+    handle_map[pin_check_result]->hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle;
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) {
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address);
+    hal_ll_i2c_pins_t index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC};
+    uint8_t pin_check_result;
+
+    if ( HAL_LL_PIN_NC == ( pin_check_result = hal_ll_i2c_master_check_pins( hal_ll_i2c_hw_specifics_map_local->pins.pin_scl,
+                                                                             hal_ll_i2c_hw_specifics_map_local->pins.pin_sda,
+                                                                             &index_list, (void *)0 )))
+    {
+        return HAL_LL_I2C_MASTER_WRONG_PINS;
+    };
+
+    hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local );
+
+    hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base;
+    hal_ll_module_state[pin_check_result].init_ll_state = true;
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) {
+    low_level_handle = hal_ll_i2c_get_handle;
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address );
+
+    low_level_handle->init_ll_state = false;
+    hal_ll_i2c_hw_specifics_map_local->speed = hal_ll_i2c_get_speed( speed );
+    hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local );
+    low_level_handle->init_ll_state = true;
+
+    return hal_ll_i2c_hw_specifics_map_local->speed;
+}
+
+void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) {
+    low_level_handle = hal_ll_i2c_get_handle;
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address);
+
+    hal_ll_i2c_hw_specifics_map_local->timeout = timeout;
+}
+
+void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr) {
+    low_level_handle = hal_ll_i2c_get_handle;
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address);
+
+    hal_ll_i2c_hw_specifics_map_local->address = addr;
+}
+
+hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) {
+    low_level_handle = hal_ll_i2c_get_handle;
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address);
+
+    return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP );
+}
+
+hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) {
+    low_level_handle = hal_ll_i2c_get_handle;
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address);
+
+    return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP );
+}
+
+hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) {
+    low_level_handle = hal_ll_i2c_get_handle;
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address);
+
+    if( HAL_LL_I2C_MASTER_SUCCESS != hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ )) {
+        return HAL_LL_I2C_MASTER_TIMEOUT_WRITE;
+    }
+
+    /**
+     * @note Wait for drivers to set-up
+     * correctly.
+     **/
+    #ifdef __TFT_RESISTIVE_TSC2003__
+    Delay_22us();
+    #endif
+
+    if( HAL_LL_I2C_MASTER_SUCCESS != hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ )) {
+        return HAL_LL_I2C_MASTER_TIMEOUT_READ;
+    }
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+void hal_ll_i2c_master_close( handle_t *handle ) {
+    low_level_handle = hal_ll_i2c_get_handle;
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address);
+
+    if( NULL != low_level_handle->hal_ll_i2c_master_handle ) {
+        low_level_handle->hal_ll_i2c_master_handle = NULL;
+        low_level_handle->hal_drv_i2c_master_handle = NULL;
+
+        low_level_handle->init_ll_state = false;
+
+        hal_ll_i2c_hw_specifics_map_local->address = 0;
+        hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT;
+        hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K;
+
+        hal_ll_i2c_hw_specifics_map_local->pins.pin_scl = HAL_LL_PIN_NC;
+        hal_ll_i2c_hw_specifics_map_local->pins.pin_sda = HAL_LL_PIN_NC;
+    }
+}
+
+// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS
+static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) {
+    const hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base);
+    uint16_t time_counter = map->timeout;
+
+    if( HAL_LL_I2C_MASTER_END_MODE_STOP == mode ) {
+        hal_ll_i2c_master_start( map );
+        while( HAL_LL_I2C_TWSR_START != ( read_reg( hal_ll_hw_reg->twsr ) & HAL_LL_I2C_TWSR_STATUS_MASK )); // START condition
+    } else if ( HAL_LL_I2C_MASTER_WRITE_THEN_READ == mode ) {
+        while( HAL_LL_I2C_TWSR_REPEATED_START != ( read_reg( hal_ll_hw_reg->twsr ) & HAL_LL_I2C_TWSR_STATUS_MASK )); // REPEATED START condition
+    }
+
+    write_reg( hal_ll_hw_reg->twdr, ( map->address << 1 ) | 1 );
+
+    time_counter = map->timeout;
+    while( !check_reg_bit( hal_ll_hw_reg->twcr, HAL_LL_I2C_TWCR_TWINT_BIT )) { // Wait for TWINT flag
+        if ( map->timeout ) {
+            if ( !time_counter-- )
+                return HAL_LL_I2C_MASTER_TIMEOUT_READ;
+        }
+    }
+
+    write_reg( hal_ll_hw_reg->twcr, HAL_LL_I2C_TWCR_TWINT_CLEAR );
+
+    time_counter = map->timeout;
+    while( !check_reg_bit( hal_ll_hw_reg->twcr, HAL_LL_I2C_TWCR_TWINT_BIT )) { // Wait for TWINT flag
+        if ( map->timeout ) {
+            if ( !time_counter-- )
+                return HAL_LL_I2C_MASTER_TIMEOUT_READ;
+        }
+    }
+
+    if ( HAL_LL_I2C_TWSR_ARB_LOST == ( read_reg( hal_ll_hw_reg->twsr ) & HAL_LL_I2C_TWSR_STATUS_MASK )) {
+        return HAL_LL_I2C_MASTER_ARBITRATION_LOST;
+    }
+    while ( HAL_LL_I2C_TWSR_SADDR_R_ACK != ( read_reg( hal_ll_hw_reg->twsr ) & HAL_LL_I2C_TWSR_STATUS_MASK )); // SLA+R transmitted + ACK
+
+    for( int i = 0; i < len_read_data; i++ ) {
+        if( len_read_data - 1 != i ) {
+            write_reg( hal_ll_hw_reg->twcr, HAL_LL_I2C_TWCR_SEND_ACK );
+            time_counter = map->timeout;
+            while( !check_reg_bit( hal_ll_hw_reg->twcr, HAL_LL_I2C_TWCR_TWINT_BIT )) { // Wait for TWINT flag
+                if ( map->timeout ) {
+                    if ( !time_counter-- )
+                        return HAL_LL_I2C_MASTER_TIMEOUT_READ;
+                }
+            }
+
+            read_data_buf[i] = read_reg( hal_ll_hw_reg->twdr );
+            while( HAL_LL_I2C_TWSR_DATA_R_ACK != ( read_reg( hal_ll_hw_reg->twsr ) & HAL_LL_I2C_TWSR_STATUS_MASK )); // Data byte received, ACK returned
+        }
+
+        if( len_read_data - 1 == i ) {
+            write_reg( hal_ll_hw_reg->twcr, HAL_LL_I2C_TWCR_TWINT_CLEAR );
+            time_counter = map->timeout;
+            while( !check_reg_bit( hal_ll_hw_reg->twcr, HAL_LL_I2C_TWCR_TWINT_BIT )) { // Wait for TWINT flag
+                if ( map->timeout ) {
+                    if ( !time_counter-- )
+                        return HAL_LL_I2C_MASTER_TIMEOUT_READ;
+                }
+            }
+            read_data_buf[i] = read_reg( hal_ll_hw_reg->twdr );
+        }
+    }
+
+    write_reg( hal_ll_hw_reg->twcr, HAL_LL_I2C_TWCR_STOP); // STOP condition
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) {
+    const hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base);
+    uint16_t time_counter = map->timeout;
+
+    hal_ll_i2c_master_start( map );
+
+    while( HAL_LL_I2C_TWSR_START != ( read_reg( hal_ll_hw_reg->twsr ) & HAL_LL_I2C_TWSR_STATUS_MASK )); // START condition
+
+    write_reg( hal_ll_hw_reg->twdr, map->address << 1 );
+    write_reg( hal_ll_hw_reg->twcr, HAL_LL_I2C_TWCR_TWINT_CLEAR );
+
+    while( !check_reg_bit( hal_ll_hw_reg->twcr, HAL_LL_I2C_TWCR_TWINT_BIT )) { // Wait for TWINT flag
+        if ( map->timeout ) {
+            if ( !time_counter-- )
+                return HAL_LL_I2C_MASTER_TIMEOUT_WRITE;
+        }
+    }
+
+    if ( HAL_LL_I2C_TWSR_ARB_LOST == ( read_reg( hal_ll_hw_reg->twsr ) & HAL_LL_I2C_TWSR_STATUS_MASK )) {
+        return HAL_LL_I2C_MASTER_ARBITRATION_LOST;
+    }
+
+    time_counter = map->timeout;
+    while( HAL_LL_I2C_TWSR_SADDR_W_ACK != ( read_reg( hal_ll_hw_reg->twsr ) & HAL_LL_I2C_TWSR_STATUS_MASK )) { // SLA+W transmitted + ACK
+        if ( map->timeout ) {
+            if ( !time_counter-- )
+                return HAL_LL_I2C_MASTER_TIMEOUT_WRITE;
+        }
+    }
+    for( int i = 0; i < len_write_data; i++ ) {
+        write_reg( hal_ll_hw_reg->twdr, write_data_buf[i] );
+        write_reg( hal_ll_hw_reg->twcr, HAL_LL_I2C_TWCR_TWINT_CLEAR );
+
+        time_counter = map->timeout;
+        while( !check_reg_bit( hal_ll_hw_reg->twcr, HAL_LL_I2C_TWCR_TWINT_BIT )) { // Wait for TWINT flag
+            if ( map->timeout ) {
+                if ( !time_counter-- )
+                    return HAL_LL_I2C_MASTER_TIMEOUT_WRITE;
+            }
+        }
+
+        time_counter = map->timeout;
+        while( HAL_LL_I2C_TWSR_DATA_T_ACK != (( read_reg( hal_ll_hw_reg->twsr ) & HAL_LL_I2C_TWSR_STATUS_MASK ))) { // Data byte transmitted + ACK
+            if ( map->timeout ) {
+                if ( !time_counter-- )
+                    return HAL_LL_I2C_MASTER_TIMEOUT_WRITE;
+                }
+        }
+    }
+
+    if( HAL_LL_I2C_MASTER_WRITE_THEN_READ == mode ) {
+        write_reg( hal_ll_hw_reg->twcr, HAL_LL_I2C_TWCR_START );
+    } else {
+        write_reg( hal_ll_hw_reg->twcr, HAL_LL_I2C_TWCR_STOP );
+    }
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) {
+    const hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base );
+    uint16_t time_counter = map->timeout;
+
+    write_reg( hal_ll_hw_reg->twcr, HAL_LL_I2C_TWCR_START );
+
+    while ( !check_reg_bit( hal_ll_hw_reg->twcr, HAL_LL_I2C_TWCR_TWINT_BIT )) {
+        if ( map->timeout ) {
+            if ( !time_counter-- )
+                return HAL_LL_I2C_MASTER_TIMEOUT_START;
+        }
+    }
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pins_t *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) {
+    static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) );
+    static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) );
+    uint8_t hal_ll_module_id = 0;
+    uint8_t index_counter = 0;
+    uint8_t scl_index;
+    uint8_t sda_index;
+
+    if (( HAL_LL_PIN_NC == scl ) || ( HAL_LL_PIN_NC == sda )) {
+        return HAL_LL_PIN_NC;
+    }
+
+    for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) {
+        if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) {
+            for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) {
+                if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) {
+                    if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) {
+                        // Get module number
+                        hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index;
+                        // Map pin names
+                        index_list[hal_ll_module_id]->pin_scl = scl_index;
+                        index_list[hal_ll_module_id]->pin_sda = sda_index;
+
+                        // Check if module is taken
+                        if ( NULL == handle_map[hal_ll_module_id].hal_drv_i2c_master_handle ) {
+                            return hal_ll_module_id;
+                        } else if ( I2C_MODULE_COUNT == ++index_counter ) {
+                            return --index_counter;
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    if ( index_counter ) {
+        return hal_ll_module_id;
+    } else {
+        return HAL_LL_PIN_NC;
+    }
+}
+
+static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) {
+    uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / (sizeof( hal_ll_i2c_master_handle_register_t ));
+    static uint8_t hal_ll_module_error = hal_ll_module_count;
+
+    while( hal_ll_module_count-- ) {
+        if ( hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[ hal_ll_module_count ].base ) {
+            return &hal_ll_i2c_hw_specifics_map[ hal_ll_module_count ];
+        }
+    }
+
+    return &hal_ll_i2c_hw_specifics_map[ hal_ll_module_error ];
+}
+
+static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pins_t *index_list ) {
+    // Map new pins
+    hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl = hal_ll_i2c_scl_map[ index_list[module_index]->pin_scl ].pin;
+    hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda = hal_ll_i2c_sda_map[ index_list[module_index]->pin_sda ].pin;
+}
+
+static uint32_t hal_ll_i2c_get_speed( uint32_t bit_rate ) {
+    if ( HAL_LL_I2C_MASTER_SPEED_FULL >= bit_rate ) {
+        if ( HAL_LL_I2C_MASTER_SPEED_STANDARD >= bit_rate ) {
+            return HAL_LL_I2C_MASTER_SPEED_100K;
+        } else if ( HAL_LL_I2C_MASTER_SPEED_FULL >= bit_rate ) {
+            return HAL_LL_I2C_MASTER_SPEED_400K;
+        } else {
+            return HAL_LL_I2C_MASTER_SPEED_100K;
+        }
+    } else {
+        if ( HAL_LL_I2C_MASTER_SPEED_100K >= bit_rate ) {
+            return HAL_LL_I2C_MASTER_SPEED_100K;
+        } else if ( HAL_LL_I2C_MASTER_SPEED_400K >= bit_rate ) {
+            return HAL_LL_I2C_MASTER_SPEED_400K;
+        } else {
+            return HAL_LL_I2C_MASTER_SPEED_400K;
+        }
+    }
+}
+
+static void hal_ll_i2c_master_set_bit_rate( hal_ll_i2c_hw_specifics_map_t *map ) {
+    const hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base);
+    volatile uint8_t prescaler;
+    volatile uint32_t cpu_clk_hz;
+
+    prescaler = hal_ll_hw_reg->twsr & HAL_LL_I2C_TWSR_PRESCALER_MASK;
+    cpu_clk_hz = Get_Fosc_kHz() * 1000;
+
+    // SCLf = CPU_CLKf / (16 + 2*TWBR * 4^(TWPS))
+    write_reg( hal_ll_hw_reg->twbr, ( cpu_clk_hz - 16 * map->speed ) / ( map->speed * pow( 2, ( 2 * prescaler + 1 ))));
+}
+
+static void hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) {
+    hal_ll_i2c_master_set_bit_rate( map );
+}
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/src/i2c/implementation_2/hal_ll_i2c_master.c b/targets/avr_8bit/mikroe/avr/src/i2c/implementation_2/hal_ll_i2c_master.c
new file mode 100644
index 000000000..52c314507
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/i2c/implementation_2/hal_ll_i2c_master.c
@@ -0,0 +1,664 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_i2c_master.c
+ * @brief I2C master HAL LOW LEVEL layer implementation.
+ */
+
+#include "hal_ll_gpio.h"
+#include "hal_ll_i2c_master.h"
+#include "hal_ll_i2c_pin_map.h"
+
+/*!< @brief Local handle list */
+static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false };
+
+// ------------------------------------------------------------- PRIVATE MACROS
+/*!< @brief Helper macro for getting hal_ll_module_state address */
+#define hal_ll_i2c_get_module_state_address (( hal_ll_i2c_master_handle_register_t *)*handle)
+/*!< @brief Helper macro for getting module specific control register structure base address // first register address */
+#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle
+/*!< @brief Helper macro for getting module specific control register structure */
+#define hal_ll_i2c_get_base_struct(_handle) ((const hal_ll_i2c_base_handle_t *)_handle)
+/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */
+#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\
+                                            (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base
+
+/*!< @brief Default pass count value upon reset */
+#define HAL_LL_I2C_DEFAULT_PASS_COUNT    (10000)
+
+/*!< @brief Default I2C bit-rate if no speed is set */
+#define HAL_LL_I2C_MASTER_SPEED_100K     (100000UL)
+#define HAL_LL_I2C_MASTER_SPEED_400K     (400000UL)
+
+/*!< @brief Macros defining control register values */
+#define HAL_LL_I2C_CTRLA_MASTER_ENABLE   (3)
+#define HAL_LL_I2C_CTRLC_ACKACT_NACK     (0x4)
+#define HAL_LL_I2C_CTRLC_CMD_STOP        (0x3)
+#define HAL_LL_I2C_CTRLC_CMD_RESTART     (0x1)
+#define HAL_LL_I2C_CTRLC_CMD_BYTEREC     (0x2)
+
+/*!< @brief Macros defining status flags and bus states */
+#define HAL_LL_I2C_MASTER_STATUS_RIF      (7)
+#define HAL_LL_I2C_MASTER_STATUS_WIF      (6)
+#define HAL_LL_I2C_MASTER_STATUS_IDLE     (1)
+#define HAL_LL_I2C_MASTER_STATUS_BUS_MASK (0x3)
+
+// NOTE: Slave module is not used in this implementation. Set 'true' if needed.
+#define HAL_LL_I2C_SLAVE_ENABLE           (false)
+
+// -------------------------------------------------------------- PRIVATE TYPES
+/*!< @brief I2C register structures */
+typedef struct
+{
+    uint16_t ctrla;
+    uint16_t ctrlb;
+    uint16_t ctrlc;
+    uint16_t status;
+    uint16_t baud;
+    uint16_t addr;
+    uint16_t dat;
+} master_regs;
+
+#if HAL_LL_I2C_SLAVE_ENABLE
+typedef struct
+{
+    uint16_t ctrla;
+    uint16_t ctrlb;
+    uint16_t status;
+    uint16_t addr;
+    uint16_t dat;
+    uint16_t addrmask;
+} slave_regs;
+#endif
+
+typedef struct
+{
+    uint16_t ctrl;
+    master_regs master;
+    #if HAL_LL_I2C_SLAVE_ENABLE
+    slave_regs slave;
+    #endif
+} hal_ll_i2c_base_handle_t;
+
+/*!< @brief I2C hw specific structure */
+typedef struct
+{
+    const hal_ll_i2c_base_handle_t *base;
+    uint8_t module_index;
+    hal_ll_i2c_pins_t pins;
+    uint32_t speed;
+    uint8_t address;
+    uint16_t timeout;
+} hal_ll_i2c_hw_specifics_map_t;
+
+/*!< @brief I2C hw specific error values */
+typedef enum
+{
+    HAL_LL_I2C_MASTER_SUCCESS = 0,
+    HAL_LL_I2C_MASTER_WRONG_PINS,
+    HAL_LL_I2C_MASTER_MODULE_ERROR,
+
+    HAL_LL_I2C_MASTER_ERROR = (-1)
+} hal_ll_i2c_master_err_t;
+
+/*!< @brief I2C end mode selection values */
+typedef enum
+{
+    HAL_LL_I2C_MASTER_END_MODE_RESTART = 0,
+    HAL_LL_I2C_MASTER_END_MODE_STOP,
+    HAL_LL_I2C_MASTER_WRITE_THEN_READ
+} hal_ll_i2c_master_end_mode_t;
+
+/*!< @brief I2C timeout error values */
+typedef enum
+{
+    HAL_LL_I2C_MASTER_TIMEOUT_START = 1300,
+    HAL_LL_I2C_MASTER_TIMEOUT_WRITE,
+    HAL_LL_I2C_MASTER_TIMEOUT_READ,
+    HAL_LL_I2C_MASTER_ARBITRATION_LOST
+} hal_ll_i2c_master_timeout_t;
+
+/**
+ * @brief Enum containing predefined module standard speed values.
+ *
+ * Enum values:
+ * HAL_LL_I2C_MASTER_SPEED_STANDARD -- Speed set at 100K
+ * HAL_LL_I2C_MASTER_SPEED_FULL -- Speed set at 400K
+ */
+typedef enum
+{
+    HAL_LL_I2C_MASTER_SPEED_STANDARD = 0,
+    HAL_LL_I2C_MASTER_SPEED_FULL,
+    HAL_LL_I2C_MASTER_SPEED_FAST
+} hal_ll_i2c_master_speed_t;
+
+// ------------------------------------------------------------------ CONSTANTS
+/*!< @brief I2C modules register array */
+static const hal_ll_i2c_base_handle_t hal_ll_i2c_regs[ I2C_MODULE_COUNT + 1 ] = {
+    #ifdef TWI_MODULE_C
+    { HAL_LL_TWIC_CTRL_REG_ADDRESS,
+      { HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS, HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS, HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS,
+        HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS, HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS, HAL_LL_TWIC_MASTERADDR_REG_ADDRESS,
+        HAL_LL_TWIC_MASTERDATA_REG_ADDRESS }
+      #if HAL_LL_I2C_SLAVE_ENABLE
+      ,{ HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS, HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS, HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS,
+        HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS, HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS, HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS }
+      #endif
+    },
+    #endif
+    #ifdef TWI_MODULE_E
+    { HAL_LL_TWIE_CTRL_REG_ADDRESS,
+      { HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS, HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS, HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS,
+        HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS, HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS, HAL_LL_TWIE_MASTERADDR_REG_ADDRESS,
+        HAL_LL_TWIE_MASTERDATA_REG_ADDRESS }
+      #if HAL_LL_I2C_SLAVE_ENABLE
+      ,{ HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS, HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS, HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS,
+        HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS, HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS, HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS }
+      #endif
+    },
+    #endif
+    #ifdef TWI_MODULE_D
+    { HAL_LL_TWID_CTRL_REG_ADDRESS,
+      { HAL_LL_TWID_MASTERCTRLA_REG_ADDRESS, HAL_LL_TWID_MASTERCTRLB_REG_ADDRESS, HAL_LL_TWID_MASTERCTRLC_REG_ADDRESS,
+        HAL_LL_TWID_MASTERSTATUS_REG_ADDRESS, HAL_LL_TWID_MASTERBAUD_REG_ADDRESS, HAL_LL_TWID_MASTERADDR_REG_ADDRESS,
+        HAL_LL_TWID_MASTERDATA_REG_ADDRESS }
+      #if HAL_LL_I2C_SLAVE_ENABLE
+      ,{ HAL_LL_TWID_SLAVECTRLA_REG_ADDRESS, HAL_LL_TWID_SLAVECTRLB_REG_ADDRESS, HAL_LL_TWID_SLAVESTATUS_REG_ADDRESS,
+        HAL_LL_TWID_SLAVEADDR_REG_ADDRESS, HAL_LL_TWID_SLAVEDATA_REG_ADDRESS, HAL_LL_TWID_SLAVEADDRMASK_REG_ADDRESS }
+      #endif
+    },
+    #endif
+
+    { HAL_LL_MODULE_ERROR,
+      { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR }
+      #if HAL_LL_I2C_SLAVE_ENABLE
+      ,{ HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR }*/
+      #endif
+    }
+};
+
+// ------------------------------------------------------------------ VARIABLES
+/*!< @brief I2C hardware specific info */
+static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[ I2C_MODULE_COUNT + 1 ] = {
+    #ifdef TWI_MODULE_C
+    { &hal_ll_i2c_regs[ hal_ll_i2c_module_num( TWI_MODULE_C )], hal_ll_i2c_module_num(TWI_MODULE_C), {HAL_LL_PIN_NC,HAL_LL_PIN_NC}, HAL_LL_I2C_MASTER_SPEED_100K, 0, HAL_LL_I2C_DEFAULT_PASS_COUNT },
+    #endif
+    #ifdef TWI_MODULE_D
+    { &hal_ll_i2c_regs[ hal_ll_i2c_module_num( TWI_MODULE_D )], hal_ll_i2c_module_num(TWI_MODULE_D), {HAL_LL_PIN_NC,HAL_LL_PIN_NC}, HAL_LL_I2C_MASTER_SPEED_100K, 0, HAL_LL_I2C_DEFAULT_PASS_COUNT },
+    #endif
+    #ifdef TWI_MODULE_E
+    { &hal_ll_i2c_regs[ hal_ll_i2c_module_num( TWI_MODULE_E )], hal_ll_i2c_module_num(TWI_MODULE_E), {HAL_LL_PIN_NC,HAL_LL_PIN_NC}, HAL_LL_I2C_MASTER_SPEED_100K, 0, HAL_LL_I2C_DEFAULT_PASS_COUNT },
+    #endif
+
+    { &hal_ll_i2c_regs[ hal_ll_i2c_module_num( TWI_MODULE_COUNT )], HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC,HAL_LL_PIN_NC}, 0 , 0, 0 }
+};
+
+/*!< @brief Global handle variables used in functions */
+static volatile hal_ll_i2c_master_handle_register_t *low_level_handle;
+static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local;
+
+// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS
+/**
+  * @brief  Check if pins are adequate.
+  *
+  * Checks scl and sda pins the user has passed with pre-defined
+  * pins in scl and sda maps. Take into consideration that module
+  * index numbers have to be the same for both pins.
+  *
+  * @param[in]  scl - SCL pre-defined pin name.
+  * @param[in]  sda - SDA pre-defined pin name.
+  * @param[in]  *index_list - Array with SCL and SDA map index values
+  * @param[in]  *handle_map - Map containing I2C HAL low level and Driver handles.
+  *
+  * @return hal_ll_pin_name_t Module index based on pins.
+  *
+  * Returns pre-defined module index from pin maps, if pins
+  * are adequate.
+  */
+static hal_ll_pin_name_t hal_ll_i2c_master_check_pins(hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pins_t *index_list, hal_ll_i2c_master_handle_register_t *handle_map);
+
+/**
+  * @brief  Get local hardware specific map.
+  *
+  * Checks handle value and returns address of adequate
+  * hal_ll_i2c_hw_specifics_map array index.
+  *
+  * @param[in]  handle - Object specific context handler.
+  *
+  * @return hal_ll_i2c_hw_specifics_map_t Map address.
+  *
+  * Returns pre-defined map index address based on handle value,
+  * if handle is adequate.
+  */
+static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics(handle_t handle);
+
+/**
+  * @brief  Get adequate I2C bit-rate value.
+  *
+  * Returns one of pre-defined bit-rate values,
+  * or the closest bit-rate based on bit_rate
+  * value passed to the function.
+  *
+  * @param[in]  bit_rate - I2C bit rate.
+  *
+  * @return uint32_t Adequate bit-rate value.
+  *
+  * Returns adequate value to be latter written into bare metal register address.
+  * Take into consideration that this returns a predefined value.
+  *
+  * HAL_LL_I2C_MASTER_SPEED_100K -- 100Kbit/s
+  * HAL_LL_I2C_MASTER_SPEED_400K -- 400Kbit/s
+  */
+static uint32_t hal_ll_i2c_get_speed(uint32_t bit_rate);
+
+/**
+ * @brief  Maps new-found module specific values.
+ *
+ * Maps pin names and alternate function values for
+ * I2C SCL and SDA pins.
+ *
+ * @param[in]  module_index I2C HW module index -- 0,1,2...
+ * @param[in]  *index_list  Array with SCL and SDA map index values
+ *
+ * @return  None
+ */
+static void hal_ll_i2c_master_map_pins(uint8_t module_index, hal_ll_i2c_pins_t *index_list);
+
+/**
+  * @brief  Full I2C module initialization procedure.
+  *
+  * Initializes I2C module on hardware level, based on beforehand
+  * set configuration and module handler. Sets adequate pin alternate functions.
+  * Initializes module clock.
+  *
+  * @param[in]  map - Object specific context handler.
+  *
+  * @return hal_ll_err_t Module specific values.
+  *
+  * Returns one of pre-defined values.
+  * Take into consideration that this is hardware specific.
+  */
+static void hal_ll_i2c_init(hal_ll_i2c_hw_specifics_map_t *map);
+
+/**
+  * @brief  Perform a read on the I2C bus.
+  *
+  * Initializes I2C module on hardware level, if not initialized beforehand
+  * and continues to perform a read operation on the bus.
+  *
+  * @param[in]  map - Object specific context handler.
+  * @param[in]  read_data_buf - Pointer to data buffer.
+  * @param[in]  len_read_data - Number of data to be read.
+  * @param[in]  mode - I2C end mode.
+  *
+  * @return hal_ll_err_t Module specific values.
+  *
+  * Returns one of pre-defined values.
+  * Take into consideration that this is hardware specific.
+  */
+static hal_ll_err_t hal_ll_i2c_master_read_bare_metal(hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode);
+
+/**
+  * @brief  Perform a write on the I2C bus.
+  *
+  * Initializes I2C module on hardware level, if not initialized beforehand
+  * and continues to perform a write operation on the bus.
+  *
+  * @param[in]  map - Object specific context handler.
+  * @param[in]  write_data_buf - Pointer to data buffer.
+  * @param[in]  len_write_data - Number of data to be written.
+  * @param[in]  mode - I2C end mode.
+  *
+  * @return hal_ll_err_t Module specific values.
+  *
+  * Returns one of pre-defined values.
+  * Take into consideration that this is hardware specific.
+  */
+static hal_ll_err_t hal_ll_i2c_master_write_bare_metal(hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode);
+
+// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS
+hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) {
+    hal_ll_i2c_pins_t index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC};
+    uint16_t pin_check_result;
+
+    if ( HAL_LL_PIN_NC == ( pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, &index_list, handle_map ))) {
+        return HAL_LL_I2C_MASTER_WRONG_PINS;
+    };
+
+    if ( ( hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_scl != scl ) ||
+         ( hal_ll_i2c_hw_specifics_map[pin_check_result].pins.pin_sda != sda ) )
+    {
+        // Map new pins
+        hal_ll_i2c_master_map_pins( pin_check_result, &index_list );
+
+        handle_map[pin_check_result]->init_ll_state = false;
+    }
+
+    *hal_module_id = pin_check_result;
+
+    hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base;
+
+    handle_map[pin_check_result]->hal_ll_i2c_master_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle;
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) {
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address);
+    hal_ll_i2c_pins_t index_list[I2C_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC};
+    uint8_t pin_check_result;
+
+    if ( HAL_LL_PIN_NC == ( pin_check_result = hal_ll_i2c_master_check_pins( hal_ll_i2c_hw_specifics_map_local->pins.pin_scl,
+                                                                             hal_ll_i2c_hw_specifics_map_local->pins.pin_sda,
+                                                                             &index_list, (void *)0 )))
+    {
+        return HAL_LL_I2C_MASTER_WRONG_PINS;
+    };
+
+    hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local );
+
+    hal_ll_module_state[pin_check_result].hal_ll_i2c_master_handle = (handle_t *)&hal_ll_i2c_hw_specifics_map[pin_check_result].base;
+    hal_ll_module_state[pin_check_result].init_ll_state = true;
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) {
+    low_level_handle = hal_ll_i2c_get_handle;
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address );
+
+    low_level_handle->init_ll_state = false;
+    hal_ll_i2c_hw_specifics_map_local->speed = hal_ll_i2c_get_speed( speed );
+    hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local );
+    low_level_handle->init_ll_state = true;
+
+    return hal_ll_i2c_hw_specifics_map_local->speed;
+}
+
+void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) {
+    low_level_handle = hal_ll_i2c_get_handle;
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address);
+
+    hal_ll_i2c_hw_specifics_map_local->timeout = timeout;
+}
+
+void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr) {
+    low_level_handle = hal_ll_i2c_get_handle;
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address);
+
+    hal_ll_i2c_hw_specifics_map_local->address = addr;
+}
+
+hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) {
+    low_level_handle = hal_ll_i2c_get_handle;
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address);
+
+    return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_END_MODE_STOP );
+}
+
+hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) {
+    low_level_handle = hal_ll_i2c_get_handle;
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address);
+
+    return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP );
+}
+
+hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) {
+    low_level_handle = hal_ll_i2c_get_handle;
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address);
+
+    if( HAL_LL_I2C_MASTER_SUCCESS != hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ )) {
+        return HAL_LL_I2C_MASTER_TIMEOUT_WRITE;
+    }
+
+    /**
+     * @note Wait for drivers to set-up
+     * correctly.
+     **/
+    #ifdef __TFT_RESISTIVE_TSC2003__
+    Delay_22us();
+    #endif
+
+    if( HAL_LL_I2C_MASTER_SUCCESS != hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ )) {
+        return HAL_LL_I2C_MASTER_TIMEOUT_READ;
+    }
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+void hal_ll_i2c_master_close( handle_t *handle ) {
+    low_level_handle = hal_ll_i2c_get_handle;
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address);
+
+    if( NULL != low_level_handle->hal_ll_i2c_master_handle ) {
+        low_level_handle->hal_ll_i2c_master_handle = NULL;
+        low_level_handle->hal_drv_i2c_master_handle = NULL;
+
+        low_level_handle->init_ll_state = false;
+
+        hal_ll_i2c_hw_specifics_map_local->address = 0;
+        hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT;
+        hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_100K;
+
+        hal_ll_i2c_hw_specifics_map_local->pins.pin_scl = HAL_LL_PIN_NC;
+        hal_ll_i2c_hw_specifics_map_local->pins.pin_sda = HAL_LL_PIN_NC;
+    }
+}
+
+// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS
+static uint8_t hal_ll_i2c_master_is_idle( const hal_ll_i2c_base_handle_t *base ) {
+    return (( read_reg( base->master.status ) & HAL_LL_I2C_MASTER_STATUS_BUS_MASK ) == HAL_LL_I2C_MASTER_STATUS_IDLE );
+}
+
+static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data, hal_ll_i2c_master_end_mode_t mode ) {
+    const hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base);
+    uint16_t time_counter = map->timeout;
+
+    write_reg( hal_ll_hw_reg->master.addr, ( map->address ) << 1 | 1 );
+
+    // RIF is set when a byte is successfully received in master read mode.
+    while( !( check_reg_bit( hal_ll_hw_reg->master.status, HAL_LL_I2C_MASTER_STATUS_RIF ))) { // RIF
+        if ( map->timeout ) {
+            if ( !time_counter-- )
+                return HAL_LL_I2C_MASTER_TIMEOUT_READ;
+        }
+    }
+
+    for( int i = 0; i < len_read_data; i++ ) {
+        read_data_buf[i] = read_reg( hal_ll_hw_reg->master.dat );
+        if( i != len_read_data - 1 ) {
+            write_reg( hal_ll_hw_reg->master.ctrlc, HAL_LL_I2C_CTRLC_CMD_BYTEREC ); // Send ACK
+            // RIF is set when a byte is successfully received in master read mode.
+            while( !( check_reg_bit( hal_ll_hw_reg->master.status, HAL_LL_I2C_MASTER_STATUS_RIF ))) { // RIF
+                if ( map->timeout ) {
+                    if ( !time_counter-- )
+                        return HAL_LL_I2C_MASTER_TIMEOUT_READ;
+                }
+            }
+        } else {
+            write_reg( hal_ll_hw_reg->master.ctrlc, ( HAL_LL_I2C_CTRLC_ACKACT_NACK | HAL_LL_I2C_CTRLC_CMD_STOP )); // Send NACK
+        }
+    }
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) {
+    const hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base);
+    uint16_t time_counter = map->timeout;
+
+    while( !( hal_ll_i2c_master_is_idle( hal_ll_hw_reg ))) {
+        if ( map->timeout ) {
+            if ( !time_counter-- )
+                return HAL_LL_I2C_MASTER_TIMEOUT_WRITE;
+        }
+    }
+
+    write_reg( hal_ll_hw_reg->master.addr, ( map->address ) << 1 );
+    // WIF is cleared automatically when writing to ADDR and DATA register.
+    while( !( check_reg_bit( hal_ll_hw_reg->master.status, HAL_LL_I2C_MASTER_STATUS_WIF ))) {
+        if ( map->timeout ) {
+            if ( !time_counter-- )
+                return HAL_LL_I2C_MASTER_TIMEOUT_WRITE;
+        }
+    }
+
+    for( int i = 0; i < len_write_data; i++ ) {
+        write_reg( hal_ll_hw_reg->master.dat, write_data_buf[i] );
+        // WIF is cleared automatically when writing to ADDR and DATA register.
+        while( !( check_reg_bit( hal_ll_hw_reg->master.status, HAL_LL_I2C_MASTER_STATUS_WIF ))) {
+            if ( map->timeout ) {
+                if ( !time_counter-- )
+                    return HAL_LL_I2C_MASTER_TIMEOUT_WRITE;
+            }
+        }
+    }
+    if( HAL_LL_I2C_MASTER_END_MODE_STOP == mode )
+        write_reg( hal_ll_hw_reg->master.ctrlc, HAL_LL_I2C_CTRLC_CMD_STOP );
+    else if ( HAL_LL_I2C_MASTER_WRITE_THEN_READ == mode )
+        write_reg( hal_ll_hw_reg->master.ctrlc, HAL_LL_I2C_CTRLC_CMD_RESTART );
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_pins_t *index_list, hal_ll_i2c_master_handle_register_t *handle_map ) {
+    static const uint16_t scl_map_size = ( sizeof( hal_ll_i2c_scl_map ) / sizeof( hal_ll_i2c_pin_map_t ) );
+    static const uint16_t sda_map_size = ( sizeof( hal_ll_i2c_sda_map ) / sizeof( hal_ll_i2c_pin_map_t ) );
+    uint8_t hal_ll_module_id = 0;
+    uint8_t index_counter = 0;
+    uint8_t scl_index;
+    uint8_t sda_index;
+
+    if (( HAL_LL_PIN_NC == scl ) || ( HAL_LL_PIN_NC == sda )) {
+        return HAL_LL_PIN_NC;
+    }
+
+    for ( scl_index = 0; scl_index < scl_map_size; scl_index++ ) {
+        if ( hal_ll_i2c_scl_map[ scl_index ].pin == scl ) {
+            for ( sda_index = 0; sda_index < sda_map_size; sda_index++ ) {
+                if ( hal_ll_i2c_sda_map[ sda_index ].pin == sda ) {
+                    if ( hal_ll_i2c_scl_map[ scl_index ].module_index == hal_ll_i2c_sda_map[ sda_index ].module_index ) {
+                        // Get module number
+                        hal_ll_module_id = hal_ll_i2c_scl_map[ scl_index ].module_index;
+                        // Map pin names
+                        index_list[hal_ll_module_id]->pin_scl = scl_index;
+                        index_list[hal_ll_module_id]->pin_sda = sda_index;
+
+                        // Check if module is taken
+                        if ( NULL == handle_map[hal_ll_module_id].hal_drv_i2c_master_handle ) {
+                            return hal_ll_module_id;
+                        } else if ( I2C_MODULE_COUNT == ++index_counter ) {
+                            return --index_counter;
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    if ( index_counter ) {
+        return hal_ll_module_id;
+    } else {
+        return HAL_LL_PIN_NC;
+    }
+}
+
+static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) {
+    uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / (sizeof( hal_ll_i2c_master_handle_register_t ));
+    static uint8_t hal_ll_module_error = hal_ll_module_count;
+
+    while( hal_ll_module_count-- ) {
+        if ( hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[ hal_ll_module_count ].base ) {
+            return &hal_ll_i2c_hw_specifics_map[ hal_ll_module_count ];
+        }
+    }
+
+    return &hal_ll_i2c_hw_specifics_map[ hal_ll_module_error ];
+}
+
+static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_i2c_pins_t *index_list ) {
+    // Map new pins
+    hal_ll_i2c_hw_specifics_map[module_index].pins.pin_scl = hal_ll_i2c_scl_map[ index_list[module_index]->pin_scl ].pin;
+    hal_ll_i2c_hw_specifics_map[module_index].pins.pin_sda = hal_ll_i2c_sda_map[ index_list[module_index]->pin_sda ].pin;
+}
+
+static uint32_t hal_ll_i2c_get_speed( uint32_t bit_rate ) {
+    // AVR has 100kHz and 400kHz bus frequency support
+    if ( HAL_LL_I2C_MASTER_SPEED_FULL >= bit_rate ) {
+        if ( HAL_LL_I2C_MASTER_SPEED_STANDARD >= bit_rate ) {
+            return HAL_LL_I2C_MASTER_SPEED_100K;
+        } else if ( HAL_LL_I2C_MASTER_SPEED_FULL >= bit_rate ) {
+            return HAL_LL_I2C_MASTER_SPEED_400K;
+        } else {
+            return HAL_LL_I2C_MASTER_SPEED_100K;
+        }
+    } else {
+        if ( HAL_LL_I2C_MASTER_SPEED_100K >= bit_rate ) {
+            return HAL_LL_I2C_MASTER_SPEED_100K;
+        } else if ( HAL_LL_I2C_MASTER_SPEED_400K >= bit_rate ) {
+            return HAL_LL_I2C_MASTER_SPEED_400K;
+        } else {
+            return HAL_LL_I2C_MASTER_SPEED_400K;
+        }
+    }
+}
+
+static void hal_ll_i2c_master_set_bit_rate( hal_ll_i2c_hw_specifics_map_t *map ) {
+    const hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base);
+    volatile uint32_t cpu_clk_hz;
+
+    cpu_clk_hz = Get_Fosc_kHz() * 1000;
+
+    // SCLf = CPU_CLKf / 2 * (5 + BAUD)
+    write_reg( hal_ll_hw_reg->master.baud, ( cpu_clk_hz - 10 * map->speed ) / ( 2 * map->speed ));
+}
+
+static void hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) {
+    const hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base);
+
+    // The BAUD register should only be written while master is disabled.
+    hal_ll_i2c_master_set_bit_rate( map );
+
+    // Enable TWI Master
+    set_reg_bit( hal_ll_hw_reg->master.ctrla, HAL_LL_I2C_CTRLA_MASTER_ENABLE );
+
+    // Force IDLE state
+    write_reg( hal_ll_hw_reg->master.status, HAL_LL_I2C_MASTER_STATUS_IDLE );
+}
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/src/i2c/implementation_3/hal_ll_i2c_master.c b/targets/avr_8bit/mikroe/avr/src/i2c/implementation_3/hal_ll_i2c_master.c
new file mode 100644
index 000000000..a44d8ad41
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/i2c/implementation_3/hal_ll_i2c_master.c
@@ -0,0 +1,921 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_i2c_master.c
+ * @brief I2C master HAL LOW LEVEL layer implementation.
+ */
+
+#include "hal_ll_gpio.h"
+#include "hal_ll_i2c_master.h"
+
+/*!< @brief Local handle list */
+static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false };
+
+// ------------------------------------------------------------- PRIVATE MACROS
+/*!< @brief Helper macro for getting hal_ll_module_state address */
+#define hal_ll_i2c_get_module_state_address (( hal_ll_i2c_master_handle_register_t *)*handle)
+/*!< @brief Helper macro for getting module specific control register structure base address // first register address */
+#define hal_ll_i2c_get_handle (hal_ll_i2c_master_handle_register_t *)hal_ll_i2c_get_module_state_address->hal_ll_i2c_master_handle
+/*!< @brief Helper macro for getting module specific control register structure */
+#define hal_ll_i2c_get_base_struct(_handle) (( hal_ll_i2c_base_handle_t *)_handle)
+/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */
+#define hal_ll_i2c_get_base_from_hal_handle ((hal_ll_i2c_hw_specifics_map_t *)((hal_ll_i2c_master_handle_register_t *)\
+                                            (((hal_ll_i2c_master_handle_register_t *)(handle))->hal_ll_i2c_master_handle))->hal_ll_i2c_master_handle)->base
+
+/*!< @brief Helper macro for getting adequate module index number. */
+#define hal_ll_i2c_module_num(_module_num) (_module_num - 1)
+
+/*!< @brief Default pass count value upon reset. */
+#define HAL_LL_I2C_DEFAULT_PASS_COUNT (10000)
+
+/*!< @brief Default I2C bit-rate if no speed is set. */
+#define HAL_LL_I2C_MASTER_SPEED_50K (50000UL)
+
+/*!< @brief Helper macro for getting adequate slave address bit count. */
+#define HAL_LL_I2C_MASTER_BIT_COUNTER (0x80)
+
+/*!< @brief Helper macro for getting adequate slave address byte size. */
+#define HAL_LL_I2C_MASTER_SLAVE_ADDRESS_BYTE (1)
+
+/*!< @brief Helper macros for getting adequate software I2C timings. */
+void software_i2c_timing_value_a( void ) {
+    Delay_1us(); Delay_1us();
+}
+
+void software_i2c_timing_value_b( void ) {
+    Delay_1us(); Delay_1us();
+    Delay_1us(); Delay_1us();
+}
+
+void software_i2c_timing_value_c( void ) {
+    Delay_1us(); Delay_1us();
+    Delay_1us(); Delay_1us();
+    Delay_1us(); Delay_1us();
+    Delay_1us(); Delay_1us();
+}
+
+// -------------------------------------------------------------- PRIVATE TYPES
+/*!< @brief I2C register structure */
+typedef struct {
+    hal_ll_base_addr_t port_reg_addr;
+    hal_ll_base_addr_t ddr_reg_addr;
+    hal_ll_base_addr_t pin_reg_addr;
+} hal_ll_i2c_base_handle_t;
+
+/*!< @brief Software I2C hw specific pointers to functions. */
+typedef struct {
+    hal_ll_err_t ( *mapped_function_software_i2c_signal_write )( hal_ll_i2c_base_handle_t *, uint8_t *write_data_buf, size_t len_write_data );
+    hal_ll_err_t ( *mapped_function_software_i2c_signal_read )( hal_ll_i2c_base_handle_t *, uint8_t *read_data_buf, size_t len_read_data );
+} hal_ll_software_i2c_functions;
+
+/*!< @brief Context structure for storing pin mask for both SCL and SDA. */
+typedef struct {
+    hal_ll_pin_name_t pin_mask_scl;
+    hal_ll_pin_name_t pin_mask_sda;
+} hal_ll_i2c_pins_mask_t;
+
+/*!< @brief I2C hw specific structure */
+typedef struct {
+    hal_ll_i2c_base_handle_t *base;
+    hal_ll_pin_name_t module_index;
+    hal_ll_i2c_pins_t pins;
+    hal_ll_i2c_pins_mask_t pins_mask;
+    uint32_t speed;
+    uint8_t address;
+    uint16_t timeout;
+    hal_ll_software_i2c_functions mapped_functions;
+} hal_ll_i2c_hw_specifics_map_t;
+
+/*!< @brief I2C hw specific module values */
+typedef struct {
+    hal_ll_pin_name_t pin_scl;
+    hal_ll_pin_name_t pin_sda;
+} hal_ll_i2c_pin_id;
+
+/*!< @brief I2C hw specific error values */
+typedef enum {
+    HAL_LL_I2C_MASTER_SUCCESS = 0,
+    HAL_LL_I2C_MASTER_WRONG_PINS,
+    HAL_LL_I2C_MASTER_MODULE_ERROR,
+
+    HAL_LL_I2C_MASTER_ERROR = (-1)
+} hal_ll_i2c_master_err_t;
+
+/*!< @brief I2C end mode selection values */
+typedef enum {
+    HAL_LL_I2C_MASTER_END_MODE_RESTART = 0,
+    HAL_LL_I2C_MASTER_END_MODE_STOP,
+    HAL_LL_I2C_MASTER_WRITE_THEN_READ
+} hal_ll_i2c_master_end_mode_t;
+
+/*!< @brief I2C timeout error values */
+typedef enum {
+    HAL_LL_I2C_MASTER_TIMEOUT_START = 1300,
+    HAL_LL_I2C_MASTER_TIMEOUT_WRITE,
+    HAL_LL_I2C_MASTER_TIMEOUT_READ,
+    HAL_LL_I2C_MASTER_ARBITRATION_LOST,
+    HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE,
+    HAL_LL_I2C_MASTER_WRITE_COLLISION
+} hal_ll_i2c_master_timeout_t;
+
+// ------------------------------------------------------------------ CONSTANTS
+/*!< @brief I2C registers array */
+static  hal_ll_i2c_base_handle_t hal_ll_i2c_hw_regs[ I2C_MODULE_COUNT + 1 ] = {
+    #ifdef __PORT_A_CN
+    { PORTA_REG_ADDRESS, DDRA_REG_ADDRESS, PINA_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_B_CN
+    { PORTB_REG_ADDRESS, DDRB_REG_ADDRESS, PINB_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_C_CN
+    { PORTC_REG_ADDRESS, DDRC_REG_ADDRESS, PINC_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_D_CN
+    { PORTD_REG_ADDRESS, DDRD_REG_ADDRESS, PIND_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_E_CN
+    { PORTE_REG_ADDRESS, DDRE_REG_ADDRESS, PINE_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_F_CN
+    { PORTF_REG_ADDRESS, DDRF_REG_ADDRESS, PINF_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_G_CN
+    { PORTG_REG_ADDRESS, DDRG_REG_ADDRESS, PING_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_H_CN
+    { PORTH_REG_ADDRESS, DDRH_REG_ADDRESS, PINH_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_J_CN
+    { PORTJ_REG_ADDRESS, DDRJ_REG_ADDRESS, PINJ_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_K_CN
+    { PORTK_REG_ADDRESS, DDRK_REG_ADDRESS, PINK_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_L_CN
+    { PORTL_REG_ADDRESS, DDRL_REG_ADDRESS, PINL_REG_ADDRESS },
+    #endif
+    #ifdef __PORT_R_CN
+    { PORTR_REG_ADDRESS, DDRR_REG_ADDRESS, PINR_REG_ADDRESS },
+    #endif
+    { HAL_LL_PORT_NC, HAL_LL_PORT_NC, HAL_LL_PORT_NC }
+};
+
+// ------------------------------------------------------------------ VARIABLES
+/*!< @brief I2C hardware specific info */
+static hal_ll_i2c_hw_specifics_map_t hal_ll_i2c_hw_specifics_map[ I2C_MODULE_COUNT + 1 ] = {
+    #ifdef __PORT_A_CN
+    { &hal_ll_i2c_hw_regs[ PORT_A ], hal_ll_i2c_module_num( PORT_A + 1 ), { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, HAL_LL_I2C_MASTER_SPEED_50K, 0, HAL_LL_I2C_DEFAULT_PASS_COUNT, NULL },
+    #endif
+    #ifdef __PORT_B_CN
+    { &hal_ll_i2c_hw_regs[ PORT_B ], hal_ll_i2c_module_num( PORT_B + 1 ), { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, HAL_LL_I2C_MASTER_SPEED_50K, 0, HAL_LL_I2C_DEFAULT_PASS_COUNT, NULL },
+    #endif
+    #ifdef __PORT_C_CN
+    { &hal_ll_i2c_hw_regs[ PORT_C ], hal_ll_i2c_module_num( PORT_C + 1 ), { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, HAL_LL_I2C_MASTER_SPEED_50K, 0, HAL_LL_I2C_DEFAULT_PASS_COUNT, NULL },
+    #endif
+    #ifdef __PORT_D_CN
+    { &hal_ll_i2c_hw_regs[ PORT_D ], hal_ll_i2c_module_num( PORT_D + 1 ), { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, HAL_LL_I2C_MASTER_SPEED_50K, 0, HAL_LL_I2C_DEFAULT_PASS_COUNT, NULL },
+    #endif
+    #ifdef __PORT_E_CN
+    { &hal_ll_i2c_hw_regs[ PORT_E ], hal_ll_i2c_module_num( PORT_E + 1 ), { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, HAL_LL_I2C_MASTER_SPEED_50K, 0, HAL_LL_I2C_DEFAULT_PASS_COUNT, NULL },
+    #endif
+    #ifdef __PORT_F_CN
+    { &hal_ll_i2c_hw_regs[ PORT_F ], hal_ll_i2c_module_num( PORT_F + 1 ), { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, HAL_LL_I2C_MASTER_SPEED_50K, 0, HAL_LL_I2C_DEFAULT_PASS_COUNT, NULL },
+    #endif
+    #ifdef __PORT_G_CN
+    { &hal_ll_i2c_hw_regs[ PORT_G ], hal_ll_i2c_module_num( PORT_G + 1 ), { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, HAL_LL_I2C_MASTER_SPEED_50K, 0, HAL_LL_I2C_DEFAULT_PASS_COUNT, NULL },
+    #endif
+    #ifdef __PORT_H_CN
+    { &hal_ll_i2c_hw_regs[ PORT_H ], hal_ll_i2c_module_num( PORT_H + 1 ), { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, HAL_LL_I2C_MASTER_SPEED_50K, 0, HAL_LL_I2C_DEFAULT_PASS_COUNT, NULL },
+    #endif
+    #ifdef __PORT_J_CN
+    { &hal_ll_i2c_hw_regs[ PORT_J ], hal_ll_i2c_module_num( PORT_J + 1 ), { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, HAL_LL_I2C_MASTER_SPEED_50K, 0, HAL_LL_I2C_DEFAULT_PASS_COUNT, NULL },
+    #endif
+    #ifdef __PORT_K_CN
+    { &hal_ll_i2c_hw_regs[ PORT_K ], hal_ll_i2c_module_num( PORT_K + 1 ), { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, HAL_LL_I2C_MASTER_SPEED_50K, 0, HAL_LL_I2C_DEFAULT_PASS_COUNT, NULL },
+    #endif
+    #ifdef __PORT_L_CN
+    { &hal_ll_i2c_hw_regs[ PORT_L ], hal_ll_i2c_module_num( PORT_L + 1 ), { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, HAL_LL_I2C_MASTER_SPEED_50K, 0, HAL_LL_I2C_DEFAULT_PASS_COUNT, NULL },
+    #endif
+    #ifdef __PORT_R_CN
+    { &hal_ll_i2c_hw_regs[ PORT_R ], hal_ll_i2c_module_num( PORT_R + 1 ), { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, HAL_LL_I2C_MASTER_SPEED_50K, 0, HAL_LL_I2C_DEFAULT_PASS_COUNT, NULL },
+    #endif
+
+    { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, { HAL_LL_PIN_NC, HAL_LL_PIN_NC }, HAL_LL_I2C_MASTER_SPEED_50K, 0,
+    HAL_LL_I2C_DEFAULT_PASS_COUNT, NULL }
+};
+/*!< @brief Global handle variables used in functions */
+static volatile hal_ll_i2c_master_handle_register_t *low_level_handle;
+static volatile hal_ll_i2c_hw_specifics_map_t *hal_ll_i2c_hw_specifics_map_local;
+
+// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS
+/**
+  * @brief Check if pins are adequate.
+  *
+  * Checks scl and sda pins the user has passed with pre-defined
+  * pins in scl and sda maps. Take into consideration that module
+  * index numbers have to be the same for both pins.
+  *
+  * @param[in] scl - SCL pre-defined pin name.
+  * @param[in] sda - SDA pre-defined pin name.
+  * @param[in] *handle_map - Local handle list.
+  *
+  * @return hal_ll_pin_name_t Module index based on pins.
+  *
+  * Returns pre-defined module index from pin maps, if pins
+  * are adequate.
+  */
+static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map );
+
+/**
+  * @brief Get local hardware specific map.
+  *
+  * Checks handle value and returns address of adequate
+  * hal_ll_i2c_hw_specifics_map array index.
+  *
+  * @param[in] handle - Object specific context handler.
+  *
+  * @return hal_ll_i2c_hw_specifics_map_t Map address.
+  *
+  * Returns pre-defined map index address based on handle value,
+  * if handle is adequate.
+  */
+static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle );
+
+/**
+ * @brief Maps new-found module specific values.
+ *
+ * Maps pin names and alternate function values for
+ * I2C SCL and SDA pins.
+ *
+ * @param[in] module_index I2C HW module index -- 0,1,2...
+ * @param[in] scl Clock pin.
+ * @param[in] sda Data pin.
+ *
+ * @return  None
+ */
+static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_pin_name_t scl, hal_ll_pin_name_t sda );
+
+/**
+  * @brief Full software I2C module initialization procedure.
+  *
+  * Initializes I2C module on hardware level, based on beforehand
+  * set configuration and module handler.
+  *
+  * @param[in] *map - Object specific context handler.
+  *
+  * @return hal_ll_err_t Module specific values.
+  * Take into consideration that this is hardware specific.
+  */
+static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map );
+
+/**
+  * @brief Map adequate function addresses.
+  *
+  * Function maps adequate function addresses.
+  *
+  * @param[in] hal_ll_module_id - Module index.
+  *
+  * @return none
+  *
+  */
+static inline void map_pointer_functions( uint8_t hal_ll_module_id );
+
+/**
+  * @brief Software I2C "write bytes" function.
+  *
+  * Function starts generating how many bytes there are on SDA pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of software I2C module.
+  * @param[in] *write_data_buf - Pointer to data buffer.
+  * @param[in] len_write_data - Number of data to be written.
+  *
+  * @return hal_ll_err_t Module specific values.
+  *
+  */
+static inline hal_ll_err_t ptr_function_software_i2c_signal_write_bytes( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buf, size_t len_write_data );
+
+/**
+  * @brief Software I2C "read bytes" function.
+  *
+  * Function starts reading how many bytes there are on SDA pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of software I2C module.
+  * @param[in] *read_data_buf - Pointer to data buffer.
+  * @param[in] len_read_data - Number of data to be read.
+  *
+  * @return hal_ll_err_t Module specific values.
+  *
+  */
+static inline hal_ll_err_t ptr_function_software_i2c_signal_read_bytes( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buf, size_t len_read_data );
+
+/**
+  * @brief Generates start signal on I2C bus.
+  *
+  * Generates a start signal on the I2C bus.
+  *
+  * @param[in] *map - Object specific context handler.
+  *
+  * @return hal_ll_err_t Module specific values.
+  *
+  * Returns one of pre-defined values.
+  * Take into consideration that this is hardware specific.
+  */
+static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map );
+
+/**
+  * @brief Generates stop signal on I2C bus.
+  *
+  * Generates a stop signal on the I2C bus.
+  *
+  * @param[in] *map - Object specific context handler.
+  *
+  * @return hal_ll_err_t Module specific values.
+  *
+  * Returns one of pre-defined values.
+  * Take into consideration that this is hardware specific.
+  */
+static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map );
+
+/**
+  * @brief Perform a read on the I2C bus.
+  *
+  * Initializes I2C module on hardware level, if not initialized beforehand
+  * and continues to perform a read operation on the bus.
+  *
+  * @param[in] *map - Object specific context handler.
+  * @param[in] *read_data_buf - Pointer to data buffer.
+  * @param[in] len_read_data - Number of data to be read.
+  *
+  * @return hal_ll_err_t Module specific values.
+  *
+  * Returns one of pre-defined values.
+  * Take into consideration that this is hardware specific.
+  */
+static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data );
+
+/**
+  * @brief Perform a write on the I2C bus.
+  *
+  * Initializes I2C module on hardware level, if not initialized beforehand
+  * and continues to perform a write operation on the bus.
+  *
+  * @param[in] *map - Object specific context handler.
+  * @param[in] *write_data_buf - Pointer to data buffer.
+  * @param[in] len_write_data - Number of data to be written.
+  *
+  * @return hal_ll_err_t Module specific values.
+  *
+  * Returns one of pre-defined values.
+  * Take into consideration that this is hardware specific.
+  */
+static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode );
+
+// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS
+hal_ll_err_t hal_ll_i2c_master_register_handle( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map, uint8_t *hal_module_id ) {
+    hal_ll_i2c_pin_id index_list[ I2C_MODULE_COUNT ] = { HAL_LL_PIN_NC, HAL_LL_PIN_NC };
+    uint8_t pin_check_result;
+
+    if ( HAL_LL_PIN_NC == ( pin_check_result = hal_ll_i2c_master_check_pins( scl, sda, handle_map ) ) ) {
+        return HAL_LL_I2C_MASTER_WRONG_PINS;
+    };
+
+    if ( ( hal_ll_i2c_hw_specifics_map[ pin_check_result ].pins.pin_scl != scl ) ||
+         ( hal_ll_i2c_hw_specifics_map[ pin_check_result ].pins.pin_sda != sda ) ) {
+        // Map new pins.
+        hal_ll_i2c_master_map_pins( pin_check_result, scl, sda );
+
+        // Set HAL initialization state to false.
+        handle_map[ pin_check_result ]->init_ll_state = false;
+
+        // Initialize HAL Low Level software I2C module.
+        if ( HAL_LL_I2C_MASTER_SUCCESS != ( hal_ll_i2c_init( &hal_ll_i2c_hw_specifics_map[ pin_check_result ] ) ) ) {
+            return HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE;
+        }
+    }
+
+    *hal_module_id = pin_check_result;
+
+    hal_ll_module_state[ pin_check_result ].hal_ll_i2c_master_handle = ( handle_t * )&hal_ll_i2c_hw_specifics_map[ pin_check_result ].base;
+
+    handle_map[ pin_check_result ]->hal_ll_i2c_master_handle = ( handle_t * )&hal_ll_module_state[ pin_check_result ].hal_ll_i2c_master_handle;
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_module_configure_i2c( handle_t *handle ) {
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address );
+    uint8_t pin_check_result;
+
+    if ( HAL_LL_PIN_NC == ( pin_check_result = hal_ll_i2c_master_check_pins( hal_ll_i2c_hw_specifics_map_local->pins.pin_scl,
+                                               hal_ll_i2c_hw_specifics_map_local->pins.pin_sda, (void *)0 ) ) ) {
+        return HAL_LL_I2C_MASTER_WRONG_PINS;
+    };
+
+    if ( HAL_LL_I2C_MASTER_SUCCESS != ( hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_local ) ) ) {
+        return HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE;
+    }
+
+    hal_ll_module_state[ pin_check_result ].hal_ll_i2c_master_handle = (handle_t * )&hal_ll_i2c_hw_specifics_map[ pin_check_result ].base;
+
+    hal_ll_module_state[ pin_check_result ].init_ll_state = true;
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_i2c_master_set_speed( handle_t *handle, uint32_t speed ) {
+    /* NOTE 1:
+     * Speed selection currently not applicable for software I2C implementation,
+     * it is dependable of MCU clock frequency itself.
+     *
+     * NOTE 2:
+     * Realistic software I2C speeds (after testing Mikroe's Click Boards with this implementation):
+     * ~50kHz @16MHz;
+     * ~25kHz @8MHz. */
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+void hal_ll_i2c_master_set_timeout( handle_t *handle, uint16_t timeout ) {
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address );
+
+    if( hal_ll_i2c_hw_specifics_map_local->module_index != HAL_LL_MODULE_ERROR ) {
+        hal_ll_i2c_hw_specifics_map_local->timeout = timeout;
+    }
+}
+
+void hal_ll_i2c_master_set_slave_address( handle_t *handle, uint8_t addr ) {
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address );
+
+    hal_ll_i2c_hw_specifics_map_local->address = addr;
+}
+
+hal_ll_err_t hal_ll_i2c_master_read( handle_t *handle, uint8_t *read_data_buf, size_t len_read_data ) {
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_i2c_get_module_state_address);
+
+    return hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data );
+}
+
+hal_ll_err_t hal_ll_i2c_master_write( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data ) {
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address );
+
+    return hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_END_MODE_STOP );
+}
+
+hal_ll_err_t hal_ll_i2c_master_write_then_read( handle_t *handle, uint8_t *write_data_buf, size_t len_write_data, uint8_t *read_data_buf, size_t len_read_data ) {
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address );
+
+    if( hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_local, write_data_buf, len_write_data, HAL_LL_I2C_MASTER_WRITE_THEN_READ ) != HAL_LL_I2C_MASTER_SUCCESS ) {
+        return HAL_LL_I2C_MASTER_TIMEOUT_WRITE;
+    }
+
+    /**
+     * @note Wait for drivers to set-up
+     * correctly.
+     **/
+    #ifdef __TFT_RESISTIVE_TSC2003__
+    Delay_22us();
+    #endif
+
+    if( hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_local, read_data_buf, len_read_data ) != HAL_LL_I2C_MASTER_SUCCESS ) {
+        return HAL_LL_I2C_MASTER_TIMEOUT_READ;
+    }
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+void hal_ll_i2c_master_close( handle_t *handle ) {
+    low_level_handle = hal_ll_i2c_get_handle;
+    hal_ll_i2c_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_i2c_get_module_state_address );
+
+    if( low_level_handle->hal_ll_i2c_master_handle != NULL ) {
+        low_level_handle->hal_ll_i2c_master_handle = NULL;
+        low_level_handle->hal_drv_i2c_master_handle = NULL;
+        low_level_handle->init_ll_state = false;
+
+        hal_ll_i2c_hw_specifics_map_local->address = 0;
+        hal_ll_i2c_hw_specifics_map_local->timeout = HAL_LL_I2C_DEFAULT_PASS_COUNT;
+        hal_ll_i2c_hw_specifics_map_local->speed = HAL_LL_I2C_MASTER_SPEED_50K;
+
+        hal_ll_i2c_hw_specifics_map_local->pins.pin_scl = HAL_LL_PIN_NC;
+        hal_ll_i2c_hw_specifics_map_local->pins.pin_sda = HAL_LL_PIN_NC;
+    }
+}
+
+// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS
+static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *read_data_buf, size_t len_read_data ) {
+    uint8_t ptr_slave_address = ( ( hal_ll_i2c_hw_specifics_map_local->address << 1 ) | 1 );
+    uint16_t time_counter = map->timeout;
+
+    // Start signal.
+    hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_local );
+
+    // Map write and read functions.
+    map_pointer_functions( hal_ll_i2c_hw_specifics_map_local->module_index );
+
+    // Send slave address and a "Read" bit (via function pointer).
+    ( hal_ll_i2c_hw_specifics_map_local->mapped_functions.mapped_function_software_i2c_signal_write )
+    ( hal_ll_i2c_hw_specifics_map_local->base, &ptr_slave_address, HAL_LL_I2C_MASTER_SLAVE_ADDRESS_BYTE );
+
+    // User-defined timeout.
+    if ( time_counter ) {
+        while ( time_counter-- );
+    }
+
+    // Read byte(s) of data (via function pointer).
+    ( hal_ll_i2c_hw_specifics_map_local->mapped_functions.mapped_function_software_i2c_signal_read )
+    ( hal_ll_i2c_hw_specifics_map_local->base, read_data_buf, len_read_data );
+
+    // Stop signal.
+    hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_local );
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_map_t *map, uint8_t *write_data_buf, size_t len_write_data, hal_ll_i2c_master_end_mode_t mode ) {
+    uint8_t ptr_slave_address = hal_ll_i2c_hw_specifics_map_local->address << 1;
+
+    /*!< @brief Start signal. */
+    hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_local );
+
+    // Map write function.
+    map_pointer_functions( hal_ll_i2c_hw_specifics_map_local->module_index );
+
+    /*!< @brief Send slave address and a "Write" bit (via function pointer). */
+    ( hal_ll_i2c_hw_specifics_map_local->mapped_functions.mapped_function_software_i2c_signal_write )
+    ( hal_ll_i2c_hw_specifics_map_local->base, &ptr_slave_address, HAL_LL_I2C_MASTER_SLAVE_ADDRESS_BYTE );
+
+    /*!< @brief Write byte(s) of data (via function pointer). */
+    ( hal_ll_i2c_hw_specifics_map_local->mapped_functions.mapped_function_software_i2c_signal_write )
+    ( hal_ll_i2c_hw_specifics_map_local->base, write_data_buf, len_write_data );
+
+    /*!< @brief Stop signal. */
+    if ( HAL_LL_I2C_MASTER_WRITE_THEN_READ == mode ) {
+        hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_local );
+    }
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+static hal_ll_err_t hal_ll_i2c_master_start( hal_ll_i2c_hw_specifics_map_t *map ) {
+    // Get appropriate PORT, PIN and DDR registers.
+    hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base );
+
+    // Set SDA direction to be input.
+    clear_reg_bit( hal_ll_hw_reg->ddr_reg_addr, map->pins_mask.pin_mask_sda );
+
+    // Stabilization time.
+    software_i2c_timing_value_a();
+
+    // Set SCL direction to be input.
+    clear_reg_bit( hal_ll_hw_reg->ddr_reg_addr, map->pins_mask.pin_mask_scl );
+
+    // Stabilization time.
+    software_i2c_timing_value_a();
+
+    // Set SDA direction to be output.
+    set_reg_bit( hal_ll_hw_reg->ddr_reg_addr, map->pins_mask.pin_mask_sda );
+
+    // Stabilization time.
+    software_i2c_timing_value_a();
+
+    // Set SCL direction to be output.
+    set_reg_bit( hal_ll_hw_reg->ddr_reg_addr, map->pins_mask.pin_mask_scl );
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+static hal_ll_err_t hal_ll_i2c_master_stop( hal_ll_i2c_hw_specifics_map_t *map ) {
+    uint16_t time_counter = map->timeout;
+
+    // Get appropriate PORT, PIN and DDR registers.
+    hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base );
+
+    // Set SDA direction to be output.
+    set_reg_bit( hal_ll_hw_reg->ddr_reg_addr, map->pins_mask.pin_mask_sda );
+
+    // Stabilization time.
+    software_i2c_timing_value_a();
+
+    // Set SCL direction to be input.
+    clear_reg_bit( hal_ll_hw_reg->ddr_reg_addr, map->pins_mask.pin_mask_scl );
+
+    // Wait until SCL pin is unblocked.
+    while ( !( check_reg_bit( hal_ll_hw_reg->pin_reg_addr, map->pins_mask.pin_mask_scl ) ) ) {
+        // User-defined timeout.
+        if ( time_counter ) {
+            if ( !time_counter-- ) {
+                return HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE;
+            }
+        }
+    }
+
+    // Stabilization time.
+    software_i2c_timing_value_c();
+
+    // Set SDA direction to be input.
+    clear_reg_bit( hal_ll_hw_reg->ddr_reg_addr, map->pins_mask.pin_mask_sda );
+
+    // Stabilization time.
+    software_i2c_timing_value_a();
+
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+static hal_ll_pin_name_t hal_ll_i2c_master_check_pins( hal_ll_pin_name_t scl, hal_ll_pin_name_t sda, hal_ll_i2c_master_handle_register_t *handle_map ) {
+    uint8_t hal_ll_module_id = 0;
+
+    // Check if pins are valid.
+    if ( ( HAL_LL_PIN_NC == scl ) || ( HAL_LL_PIN_NC == sda ) ) {
+        return HAL_LL_PIN_NC;
+    }
+
+    // Check if both SCL and SDA pins are on the same port.
+    if ( ( hal_ll_gpio_port_index( scl ) ) == ( hal_ll_gpio_port_index( sda ) ) ) {
+        // Get module number.
+        hal_ll_module_id = hal_ll_gpio_port_index( scl );
+    }
+
+    // Check if module is taken.
+    if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_i2c_master_handle ) {
+        return hal_ll_module_id;
+    } else {
+        return HAL_LL_PIN_NC;
+    }
+}
+
+static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) {
+    uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_i2c_master_handle_register_t ) );
+    static uint8_t hal_ll_module_error = hal_ll_module_count;
+
+    while( hal_ll_module_count-- ) {
+        if ( hal_ll_i2c_get_base_from_hal_handle == hal_ll_i2c_hw_specifics_map[ hal_ll_module_count ].base ) {
+            return &hal_ll_i2c_hw_specifics_map[ hal_ll_module_count ];
+        }
+    }
+
+    return &hal_ll_i2c_hw_specifics_map[ hal_ll_module_error ];
+}
+
+static void hal_ll_i2c_master_map_pins( uint8_t module_index, hal_ll_pin_name_t scl, hal_ll_pin_name_t sda ) {
+    // Map new pins.
+    hal_ll_i2c_hw_specifics_map[ module_index ].pins.pin_scl = scl;
+    hal_ll_i2c_hw_specifics_map[ module_index ].pins.pin_sda = sda;
+
+    // Map new pin's masks.
+    hal_ll_i2c_hw_specifics_map[ module_index ].pins_mask.pin_mask_scl = ( uint8_t )scl % PORT_SIZE;
+    hal_ll_i2c_hw_specifics_map[ module_index ].pins_mask.pin_mask_sda = ( uint8_t )sda % PORT_SIZE;
+}
+
+static hal_ll_err_t hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) {
+    uint16_t time_counter = map->timeout;
+
+    // Get appropriate PORT, PIN and DDR registers.
+    hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base );
+
+    // Set SDA direction to be input.
+    clear_reg_bit( hal_ll_hw_reg->ddr_reg_addr, map->pins_mask.pin_mask_sda );
+
+    // Set SCL direction to be input.
+    clear_reg_bit( hal_ll_hw_reg->ddr_reg_addr, map->pins_mask.pin_mask_scl );
+
+    // Clear output on SDA pin.
+    clear_reg_bit( hal_ll_hw_reg->port_reg_addr, map->pins_mask.pin_mask_sda );
+
+    // Clear output on SCL pin.
+    clear_reg_bit( hal_ll_hw_reg->port_reg_addr, map->pins_mask.pin_mask_scl );
+
+    // Wait until SCL pin is unblocked.
+    while ( !( check_reg_bit( hal_ll_hw_reg->pin_reg_addr, map->pins_mask.pin_mask_scl ) ) ) {
+        // User-defined timeout.
+        if ( time_counter ) {
+            if ( !time_counter-- ) {
+                return HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE;
+            }
+        }
+    }
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+// ---------------------------------------------------- STATIC POINTER FUNCTIONS
+static inline void map_pointer_functions( uint8_t hal_ll_module_id ) {
+    hal_ll_i2c_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_software_i2c_signal_write = &ptr_function_software_i2c_signal_write_bytes;
+    hal_ll_i2c_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_software_i2c_signal_read = &ptr_function_software_i2c_signal_read_bytes;
+}
+
+static inline hal_ll_err_t ptr_function_software_i2c_signal_write_bytes( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buf, size_t len_write_data ) {
+    uint16_t time_counter = hal_ll_i2c_hw_specifics_map_local->timeout;
+    size_t byte_counter = 0;
+    uint16_t bit_counter;
+
+    while ( ( byte_counter < len_write_data ) ) {
+        bit_counter = HAL_LL_I2C_MASTER_BIT_COUNTER;
+            while ( bit_counter ) {
+                // Stabilization time.
+                software_i2c_timing_value_b();
+
+                // Set SCL direction to be output.
+                set_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_scl );
+
+                // Stabilization time.
+                software_i2c_timing_value_a();
+
+                if ( write_data_buf[ byte_counter ] & bit_counter ){
+                    // Set SDA direction to be input.
+                    clear_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_sda );
+                } else {
+                    // Set SDA direction to be output.
+                    set_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_sda );
+                }
+                // Stabilization time.
+                software_i2c_timing_value_a();
+
+                // Set SCL direction to be input.
+                clear_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_scl );
+
+                // Wait until SCL pin is unblocked.
+                while ( !( check_reg_bit( hal_ll_hw_reg->pin_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_scl ) ) ) {
+                    // User-defined timeout.
+                    if ( time_counter ) {
+                        if ( !time_counter-- ) {
+                            return HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE;
+                        }
+                    }
+                }
+
+                bit_counter >>= 1;
+            }
+            ++byte_counter;
+
+        // Stabilization time.
+        software_i2c_timing_value_a();
+
+        // Set SCL direction to be output.
+        set_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_scl );
+
+        // Stabilization time.
+        software_i2c_timing_value_a();
+
+        // Set SDA direction to be input.
+        clear_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_sda );
+
+        // Stabilization time.
+        software_i2c_timing_value_b();
+
+        // Set SCL direction to be input.
+        clear_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_scl );
+
+        // Wait until SCL pin is unblocked.
+        while ( !( check_reg_bit( hal_ll_hw_reg->pin_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_scl ) ) ) {
+            // User-defined timeout.
+            if ( time_counter ) {
+                if ( !time_counter-- ) {
+                    return HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE;
+                }
+            }
+        }
+
+        // Stabilization time.
+        software_i2c_timing_value_a();
+
+        if ( ( check_reg_bit( hal_ll_hw_reg->pin_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_sda ) ) ) {
+            return HAL_LL_I2C_MASTER_WRITE_COLLISION;
+        }
+
+        // Stabilization time.
+        software_i2c_timing_value_c();
+
+        // Set SCL direction to be output.
+        set_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_scl );
+
+        // Set SDA direction to be output.
+        set_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_sda );
+    }
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+
+static inline hal_ll_err_t ptr_function_software_i2c_signal_read_bytes( hal_ll_i2c_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buf, size_t len_read_data ) {
+    uint16_t time_counter = hal_ll_i2c_hw_specifics_map_local->timeout;
+    size_t byte_counter = 0;
+    uint16_t bit_counter;
+
+    while ( ( byte_counter < len_read_data ) ) {
+        bit_counter = HAL_LL_I2C_MASTER_BIT_COUNTER;
+        while ( bit_counter ) {
+            // Stabilization time.
+            software_i2c_timing_value_a();
+
+            // Set SDA direction to be input.
+            clear_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_sda );
+
+            // Stabilization time.
+            software_i2c_timing_value_a();
+
+            // Set SCL direction to be input.
+            clear_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_scl );
+
+            // Wait until SCL pin is unblocked.
+            while ( !( check_reg_bit( hal_ll_hw_reg->pin_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_scl ) ) ) {
+                // User-defined timeout.
+                if ( time_counter ) {
+                    if ( !time_counter-- ) {
+                        return HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE;
+                    }
+                }
+            }
+
+            // Sample the data.
+            if ( ( check_reg_bit( hal_ll_hw_reg->pin_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_sda ) ) ) {
+                read_data_buf[ byte_counter ] |= bit_counter;
+            }
+
+            // Stabilization time.
+            software_i2c_timing_value_a();
+
+            // Set SCL direction to be output.
+            set_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_scl );
+
+            bit_counter >>= 1;
+        }
+        ++byte_counter;
+
+        // Set SDA direction to be input.
+        clear_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_sda );
+
+        // Stabilization time.
+        software_i2c_timing_value_a();
+
+        // Ack.
+        if ( byte_counter < len_read_data ) {
+            // Set SDA direction to be output.
+            set_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_sda );
+        } else {
+            // Set SDA direction to be input.
+            clear_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_sda );
+        }
+
+        // Stabilization time.
+        software_i2c_timing_value_a();
+
+        // Set SCL direction to be input.
+        clear_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_scl );
+
+        // Wait until SCL pin is unblocked.
+        while ( !( check_reg_bit( hal_ll_hw_reg->pin_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_scl ) ) ) {
+            // User-defined timeout.
+            if ( time_counter ) {
+                if ( !time_counter-- ) {
+                    return HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE;
+                }
+            }
+        }
+
+        // Stabilization time.
+        software_i2c_timing_value_a();
+
+        // Set SCL direction to be output.
+        set_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_scl );
+
+        // Stabilization time.
+        software_i2c_timing_value_a();
+
+        // Set SDA direction to be output.
+        set_reg_bit( hal_ll_hw_reg->ddr_reg_addr, hal_ll_i2c_hw_specifics_map_local->pins_mask.pin_mask_sda );
+    }
+    return HAL_LL_I2C_MASTER_SUCCESS;
+}
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/src/one_wire/CMakeLists.txt b/targets/avr_8bit/mikroe/avr/src/one_wire/CMakeLists.txt
new file mode 100644
index 000000000..bc4ae896d
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/one_wire/CMakeLists.txt
@@ -0,0 +1,37 @@
+set(hal_ll_def_list)
+list(APPEND hal_ll_def_list "MACRO_USAGE_ONE_WIRE")
+
+mikrosdk_add_library(lib_hal_ll_one_wire MikroSDK.HalLowLevel.OneWire
+    hal_ll_one_wire.c
+
+    ../../include/one_wire/hal_ll_one_wire.h
+)
+
+target_compile_definitions(lib_hal_ll_one_wire PUBLIC
+    ${hal_ll_def_list}
+)
+
+target_link_libraries(lib_hal_ll_one_wire PUBLIC
+    MikroC.Core
+    MikroSDK.HalLowLevel.GPIO
+    MikroSDK.HalLowLevelCommon
+)
+
+target_include_directories(lib_hal_ll_one_wire
+    PRIVATE 
+        ../../include/one_wire
+    INTERFACE
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include>
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio>
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include/one_wire>
+        $<INSTALL_INTERFACE:include/hal_ll_port>
+)
+
+mikrosdk_install(MikroSDK.HalLowLevel.OneWire)
+
+install(
+    FILES
+        ../../include/one_wire/hal_ll_one_wire.h
+    DESTINATION
+        ${CMAKE_INSTALL_PREFIX}/include/hal_ll_port
+)
diff --git a/targets/avr_8bit/mikroe/avr/src/one_wire/hal_ll_one_wire.c b/targets/avr_8bit/mikroe/avr/src/one_wire/hal_ll_one_wire.c
new file mode 100644
index 000000000..db576a204
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/one_wire/hal_ll_one_wire.c
@@ -0,0 +1,50 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_one_wire.c
+ * @brief One Wire HAL LOW LEVEL layer implementation.
+ */
+#include "hal_ll_one_wire.h"
+
+/**
+ * @attention One wire not yet implemented for ATmega MCUs.
+ * @note It will be implemented in a future release.
+ */
+
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/src/spi_master/CMakeLists.txt b/targets/avr_8bit/mikroe/avr/src/spi_master/CMakeLists.txt
new file mode 100644
index 000000000..7e2a8482e
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/spi_master/CMakeLists.txt
@@ -0,0 +1,68 @@
+set(hal_ll_def_list "")
+if((${CORE_NAME} MATCHES "GT64K") OR (${CORE_NAME} MATCHES "LTE64K"))
+    list(APPEND hal_ll_def_list "__avr_8_bit__")
+else()
+    list(APPEND hal_ll_def_list "__family_not_supported__")
+endif()
+list(APPEND hal_ll_def_list ${MCU_NAME})
+
+set(spi_master_implementation "implementation_1") # SPI implementation.
+
+if ((${MCU_NAME} MATCHES "ATX"))
+    list(APPEND hal_ll_def_list __hal_ll_spi_master_subset_atxmega__)
+elseif ((${MCU_NAME} MATCHES "AT"))
+    list(APPEND hal_ll_def_list __hal_ll_spi_master_subset_atmega__)
+    list(APPEND hal_ll_def_list "HAL_LL_SPI0_CTRL_REG_ADDRESS=HAL_LL_SPI0_SPCR_REG_ADDRESS")
+    list(APPEND hal_ll_def_list "HAL_LL_SPI0_STATUS_REG_ADDRESS=HAL_LL_SPI0_SPSR_REG_ADDRESS")
+    list(APPEND hal_ll_def_list "HAL_LL_SPI0_DATA_REG_ADDRESS=HAL_LL_SPI0_SPDR_REG_ADDRESS")
+    list(APPEND hal_ll_def_list "HAL_LL_SPI1_CTRL_REG_ADDRESS=HAL_LL_SPI1_SPCR_REG_ADDRESS")
+    list(APPEND hal_ll_def_list "HAL_LL_SPI1_STATUS_REG_ADDRESS=HAL_LL_SPI1_SPSR_REG_ADDRESS")
+    list(APPEND hal_ll_def_list "HAL_LL_SPI1_DATA_REG_ADDRESS=HAL_LL_SPI1_SPDR_REG_ADDRESS")
+else()
+    set(spi_master_implementation "__mcu_not_supported__")
+    list(APPEND hal_ll_def_list __hal_ll_spi_master_subset_atmega__)
+endif()
+
+list(APPEND hal_ll_def_list "MACRO_USAGE_SPI")
+
+mikrosdk_add_library(lib_hal_ll_spi_master MikroSDK.HalLowLevel.SPI.Master
+    ${spi_master_implementation}/hal_ll_spi_master.c
+    ../../include/hal_ll_target.h
+# ::  BEGIN SPI
+    ../../include/spi_master/hal_ll_spi_master.h
+    ../../include/spi_master/hal_ll_spi_master_pin_map.h
+# ::  END SPI
+)
+
+target_compile_definitions(lib_hal_ll_spi_master PUBLIC
+    ${hal_ll_def_list}
+)
+
+target_link_libraries(lib_hal_ll_spi_master PUBLIC
+    MikroC.Core
+    MikroSDK.HalLowLevelCore
+    MikroSDK.HalLowLevelCommon
+)
+string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER)
+target_include_directories(lib_hal_ll_spi_master
+    PRIVATE
+        ../../include
+        ../../include/gpio
+        ../../include/spi_master
+    INTERFACE
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include>
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio>
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include/spi_master>
+        $<INSTALL_INTERFACE:include/hal_ll_port>
+        $<INSTALL_INTERFACE:include/${MCU_NAME_LOWER}>
+)
+
+mikrosdk_install(MikroSDK.HalLowLevel.SPI.Master)
+
+install(
+    FILES
+        ../../include/spi_master/hal_ll_spi_master.h
+        ../../include/spi_master/hal_ll_spi_master_pin_map.h
+    DESTINATION
+        ${CMAKE_INSTALL_PREFIX}/include/hal_ll_port
+)
diff --git a/targets/avr_8bit/mikroe/avr/src/spi_master/implementation_1/hal_ll_spi_master.c b/targets/avr_8bit/mikroe/avr/src/spi_master/implementation_1/hal_ll_spi_master.c
new file mode 100644
index 000000000..cb52b491d
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/spi_master/implementation_1/hal_ll_spi_master.c
@@ -0,0 +1,812 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_spi_master.c
+ * @brief SPI master HAL LOW LEVEL layer implementation.
+ */
+
+#include "hal_ll_spi_master.h"
+#include "hal_ll_gpio_port.h"
+#include "hal_ll_spi_master_pin_map.h"
+
+/*!< @brief Local handle list */
+static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[SPI_MODULE_COUNT] = {(handle_t *)NULL, (handle_t *)NULL, false};
+
+// ------------------------------------------------------------- PRIVATE MACROS
+/*!< @brief Helper macro for getting hal_ll_module_state address */
+#define hal_ll_spi_master_get_module_state_address ((hal_ll_spi_master_handle_register_t *)*handle)
+/*!< @brief Helper macro for getting module specific control register structure base address // first register address */
+#define hal_ll_spi_master_get_handle (hal_ll_spi_master_handle_register_t *)hal_ll_spi_master_get_module_state_address->hal_ll_spi_master_handle
+/*!< @brief Helper macro for getting module specific control register structure */
+#define hal_ll_spi_master_get_base_struct(_handle) ((const hal_ll_spi_master_base_handle_t *)_handle)
+/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */
+#define hal_ll_spi_master_get_base_from_hal_handle ((hal_ll_spi_master_hw_specifics_map_t *)((hal_ll_spi_master_handle_register_t *)\
+                                                   (((hal_ll_spi_master_handle_register_t *)(handle))->hal_ll_spi_master_handle))->hal_ll_spi_master_handle)->base
+
+/*!< @brief Helper macros for baud rate dividers. */
+#define HAL_LL_SPI_MASTER_CLK_BAUD_RATE_DIVIDER_2 (2)
+#define HAL_LL_SPI_MASTER_CLK_BAUD_RATE_DIVIDER_4 (4)
+#define HAL_LL_SPI_MASTER_CLK_BAUD_RATE_DIVIDER_8 (8)
+#define HAL_LL_SPI_MASTER_CLK_BAUD_RATE_DIVIDER_16 (16)
+#define HAL_LL_SPI_MASTER_CLK_BAUD_RATE_DIVIDER_32 (32)
+#define HAL_LL_SPI_MASTER_CLK_BAUD_RATE_DIVIDER_64 (64)
+#define HAL_LL_SPI_MASTER_CLK_BAUD_RATE_DIVIDER_128 (128)
+
+/*!< @brief Helper macro for clock polarity. */
+#define HAL_LL_SPI_MASTER_CLK_POLARITY (3)
+
+/*!< @brief Helper macro for clock phase. */
+#define HAL_LL_SPI_MASTER_CLK_PHASE (2)
+
+/*!< @brief Helper macro for configuring SPI module as a master. */
+#define HAL_LL_SPI_MASTER_MODE (4)
+
+/*!< @brief Helper macro for enabling SPI module. */
+#define HAL_LL_SPI_MODULE_ENABLE (6)
+
+/*!< @brief Helper macro for serial transfer complete. */
+#define HAL_LL_SPI_MASTER_TRANSFER_COMPLETE_FLAG_BIT (7)
+
+/*!< @brief Helper macros for baud rate selection. */
+#define HAL_LL_SPI_MASTER_CLK_BAUD_RATE_BIT_0 (0)
+#define HAL_LL_SPI_MASTER_CLK_BAUD_RATE_BIT_1 (1)
+#define HAL_LL_SPI_MASTER_CLK_BAUD_RATE_BIT_2 (7)
+
+/*!< @brief Helper macros for powering up/down SPI module. */
+#define HAL_LL_PRR0_PRSPI0_BIT (2)
+#define HAL_LL_PRR1_PRSPI1_BIT (1)
+#define HAL_LL_PRR_SPI_BIT (3)
+
+/*!< @brief Helper macro for retrieving MCU clock in Hz. */
+#define _fosc (Get_Fosc_kHz()*1000)
+
+/*!< @brief Default SPI Master bit-rate if no speed is set. */
+#define HAL_LL_SPI_MASTER_SPEED_100K (100000)
+
+/*!< @brief Helper macro for masking SPI0 PRR0 module for MCUs which utilize SPI PRR module only. */
+#ifdef HAL_LL_PRR_REG_ADDRESS
+#define HAL_LL_PRR0_REG_ADDRESS HAL_LL_PRR_REG_ADDRESS
+#endif
+
+// -------------------------------------------------------------- PRIVATE TYPES
+/*!< @brief SPI register structure. */
+typedef struct {
+    hal_ll_base_addr_t spi_spcr_reg_addr; // SPI Control register.
+    hal_ll_base_addr_t spi_spsr_reg_addr; // SPI Status register.
+    hal_ll_base_addr_t spi_spdr_reg_addr; // SPI Data register.
+} hal_ll_spi_master_base_handle_t;
+
+/*!< @brief SPI Master hardware specific structure */
+typedef struct {
+    const hal_ll_spi_master_base_handle_t *base;
+    uint8_t module_index;
+    hal_ll_spi_master_pins_t pins;
+    uint8_t  dummy_data;
+    uint32_t speed;
+    uint32_t hw_actual_speed;
+    hal_ll_spi_master_mode_t mode;
+} hal_ll_spi_master_hw_specifics_map_t;
+
+/*!< @brief SPI Master hw specific error values */
+typedef enum {
+    HAL_LL_SPI_MASTER_SUCCESS = 0,
+    HAL_LL_SPI_MASTER_WRONG_PINS,
+    HAL_LL_SPI_MASTER_MODULE_ERROR,
+
+    HAL_LL_SPI_MASTER_ERROR = (-1)
+} hal_ll_spi_master_err_t;
+
+// ------------------------------------------------------------------ CONSTANTS
+// SPI Master module registers array.
+static const hal_ll_spi_master_base_handle_t hal_ll_spi_master_registers[ SPI_MODULE_COUNT + 1 ] = {
+    #ifdef SPI_MODULE_0
+    { HAL_LL_SPI0_CTRL_REG_ADDRESS, HAL_LL_SPI0_STATUS_REG_ADDRESS, HAL_LL_SPI0_DATA_REG_ADDRESS },
+    #endif
+
+    #ifdef SPI_MODULE_1
+    { HAL_LL_SPI1_CTRL_REG_ADDRESS, HAL_LL_SPI1_STATUS_REG_ADDRESS, HAL_LL_SPI1_DATA_REG_ADDRESS },
+    #endif
+
+    #ifdef SPI_MODULE_2
+    #if defined (__hal_ll_spi_master_subset_atxmega__)
+    { HAL_LL_SPI2_CTRL_REG_ADDRESS, HAL_LL_SPI2_STATUS_REG_ADDRESS, HAL_LL_SPI2_DATA_REG_ADDRESS },
+    #endif
+    #endif
+
+    #ifdef SPI_MODULE_3
+    #if defined (__hal_ll_spi_master_subset_atxmega__)
+    { HAL_LL_SPI3_CTRL_REG_ADDRESS, HAL_LL_SPI3_STATUS_REG_ADDRESS, HAL_LL_SPI3_DATA_REG_ADDRESS },
+    #endif
+    #endif
+
+    { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR }
+};
+
+// ------------------------------------------------------------------ VARIABLES
+/*!< @brief SPI Master hardware specific info */
+static hal_ll_spi_master_hw_specifics_map_t hal_ll_spi_master_hw_specifics_map[ SPI_MODULE_COUNT + 1 ] = {
+    #ifdef SPI_MODULE_0
+    { &hal_ll_spi_master_registers[hal_ll_spi_master_module_num(SPI_MODULE_0)], hal_ll_spi_master_module_num(SPI_MODULE_0),
+    { HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC }, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT },
+    #endif
+
+    #ifdef SPI_MODULE_1
+    { &hal_ll_spi_master_registers[hal_ll_spi_master_module_num(SPI_MODULE_1)], hal_ll_spi_master_module_num(SPI_MODULE_1),
+    { HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC }, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT },
+    #endif
+
+    #ifdef SPI_MODULE_2
+    #if defined (__hal_ll_spi_master_subset_atxmega__)
+    { &hal_ll_spi_master_registers[hal_ll_spi_master_module_num(SPI_MODULE_2)], hal_ll_spi_master_module_num(SPI_MODULE_2),
+    { HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC }, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT },
+    #endif
+    #endif
+
+    #ifdef SPI_MODULE_3
+    #if defined (__hal_ll_spi_master_subset_atxmega__)
+    { &hal_ll_spi_master_registers[hal_ll_spi_master_module_num(SPI_MODULE_3)], hal_ll_spi_master_module_num(SPI_MODULE_3),
+    { HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC }, 0, HAL_LL_SPI_MASTER_SPEED_100K, 0, HAL_LL_SPI_MASTER_MODE_DEFAULT },
+    #endif
+    #endif
+
+    { &hal_ll_spi_master_registers[SPI_MODULE_COUNT], HAL_LL_MODULE_ERROR,
+    { HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC }, NULL, NULL, NULL }
+};
+
+/*!< @brief Global handle variables used in functions */
+static volatile hal_ll_spi_master_handle_register_t *low_level_handle;
+static volatile hal_ll_spi_master_hw_specifics_map_t *hal_ll_spi_master_hw_specifics_map_local;
+
+// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS
+
+/**
+  * @brief Check if pins are adequate.
+  *
+  * Checks SCK, MISO and MOSI pins the user has passed with pre-defined
+  * pins in SCK, MISO and MOSI maps. Take into consideration that module
+  * index numbers have to be the same for both pins.
+  *
+  * @param[in] sck - SCK pre-defined pin name.
+  * @param[in] miso - MISO pre-defined pin name.
+  * @param[in] mosi - MOSI pre-defined pin name.
+  * @param[in] *index_list - Index list.
+  * @return hal_ll_pin_name_t Module index based on pins.
+  *
+  * Returns pre-defined module index from pin maps, if pins
+  * are adequate.
+  */
+static hal_ll_pin_name_t hal_ll_spi_master_check_pins( hal_ll_pin_name_t sck, hal_ll_pin_name_t miso,
+                                                       hal_ll_pin_name_t mosi, hal_ll_spi_master_pins_t *index_list,
+                                                       hal_ll_spi_master_handle_register_t *handle_map );
+
+/**
+  * @brief Get local hardware specific map.
+  *
+  * Checks handle value and returns address of adequate
+  * hal_ll_spi_master_hw_specifics_map array index.
+  *
+  * @param[in] handle - Object specific context handler.
+  * @return hal_ll_spi_master_hw_specifics_map_t Map address.
+  *
+  * Returns pre-defined map index address based on handle value,
+  * if handle is adequate.
+  */
+static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle );
+
+/**
+  * @brief Enable clock for SPI module on hardware level.
+  *
+  * Initializes SPI module clock on hardware level, based on beforehand
+  * set configuration and module handler.
+  *
+  * @param[in] *map - Object specific context handler.
+  * @param[in] hal_ll_state - True(enable clock)/False(disable clock).
+  * @return None
+  */
+static void hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state );
+
+/**
+  * @brief Full SPI Master module initialization procedure.
+  *
+  * Initializes SPI Master module on hardware level, based on beforehand
+  * set configuration and module handler. Sets adequate pin alternate functions.
+  * Initializes module clock.
+  *
+  * @param[in] *map - Object specific context handler.
+  * @return hal_ll_err_t Module specific values.
+  *
+  * Returns one of pre-defined values.
+  * Take into consideration that this is hardware specific.
+  */
+static void hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_t *map );
+
+/**
+ * @brief Maps new-found module specific values.
+ *
+ * Maps pin names and alternate function values for
+ * SPI SCK, MISO and MOSI pins.
+ *
+ * @param[in]  module_index SPI HW module index -- 0,1,2...
+ * @param[in]  *index_list  Array with SCK, MISO and MOSI map index values
+ *
+ * @return None
+ */
+static void hal_ll_spi_master_map_pins( uint8_t module_index, hal_ll_spi_master_pins_t *index_list );
+
+/**
+  * @brief Perform a read on the SPI Master bus.
+  *
+  * Initializes SPI Master module on hardware level, if not initialized beforehand
+  * and continues to perform a read operation on the bus.
+  *
+  * @param[in] *map - Object specific context handler.
+  * @param[in] *read_data_buffer - Pointer to data buffer.
+  * @param[in] read_data_length - Number of data to be read.
+  * @param[in] dummy_data - Data required for read procedure.
+  * @return hal_ll_err_t Module specific error values.
+  *
+  * Returns one of pre-defined error values.
+  * Take into consideration that this is hardware specific.
+  */
+static void hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_hw_specifics_map_t *map, uint8_t *read_data_buffer,
+                                               size_t read_data_length, uint8_t dummy_data );
+
+/**
+  * @brief Perform a write on the SPI Master bus.
+  *
+  * Initializes SPI Master module on hardware level, if not initialized beforehand
+  * and continues to perform a write operation on the bus.
+  *
+  * @param[in] *map - Object specific context handler.
+  * @param[in] *write_data_buffer - Pointer to data buffer.
+  * @param[in] write_data_length - Number of data to be written.
+  * @return hal_ll_err_t Module specific error values.
+  *
+  * Returns one of pre-defined error values.
+  * Take into consideration that this is hardware specific.
+  */
+static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_hw_specifics_map_t *map, uint8_t *write_data_buffer,
+                                                size_t write_data_length );
+
+/**
+  * @brief Perform a transfer on the SPI Master bus.
+  *
+  * Initializes SPI Master module on hardware level, if not initialized beforehand
+  * and continues to perform a write operation on the bus.
+  *
+  * @param[in] *map - Object specific context handler.
+  * @param[in] data_buffer - User-specific data, or dummy data.
+  * @return data Read data.
+  *
+  * Returns one of pre-defined error values.
+  * Take into consideration that this is hardware specific.
+  */
+static uint8_t hal_ll_spi_master_transfer_bare_metal( hal_ll_spi_master_hw_specifics_map_t *map, uint8_t data_buffer );
+
+/**
+ * @brief Set GPIO state.
+ *
+ * Sets adequate TRISx register
+ * values for adequate functionality.
+ *
+ * @param *map - Object specific context handler.
+ * @param hal_ll_state - init or deinit
+ *
+ * @return none.
+ *
+ * @note AVR specific.
+ */
+static void hal_ll_spi_master_configure_pins( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state );
+
+/**
+ * @brief Set SPI baud rate.
+ *
+ * Calculate Baud Rate value.
+ *
+ * @param[in] *map - Object specific context handler.
+ *
+ * @return none.
+ *
+ * @note AVR specific.
+ */
+static void hal_ll_spi_master_set_baud_rate(hal_ll_spi_master_hw_specifics_map_t *map);
+
+// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS
+hal_ll_err_t hal_ll_spi_master_register_handle(hal_ll_pin_name_t sck, hal_ll_pin_name_t miso, hal_ll_pin_name_t mosi,
+                                               hal_ll_spi_master_handle_register_t *handle_map, uint8_t *hal_module_id ) {
+    hal_ll_spi_master_pins_t index_list[ SPI_MODULE_COUNT ] = { HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC };
+    uint8_t pin_check_result;
+
+    // Check user-defined pins.
+    if ( HAL_LL_PIN_NC == ( pin_check_result = hal_ll_spi_master_check_pins(sck, miso, mosi, &index_list, handle_map ) ) ) {
+        return HAL_LL_SPI_MASTER_WRONG_PINS;
+    }
+
+    // If user has come with the same SPI hardware module, and with the same pair of the pins, the pin mapping procedure
+    // will not take a place; otherwise, clear af-s, map new pins, set af-s, and set init state to false.
+    if ( ( hal_ll_spi_master_hw_specifics_map[ pin_check_result ].pins.sck != sck ) ||
+        ( hal_ll_spi_master_hw_specifics_map[ pin_check_result ].pins.miso != miso ) ||
+        ( hal_ll_spi_master_hw_specifics_map[ pin_check_result ].pins.mosi != mosi ) ) {
+
+        // Map new pps.
+        hal_ll_spi_master_map_pins( pin_check_result, &index_list );
+
+        handle_map[ pin_check_result ]->init_ll_state = false;
+    }
+
+    // Return id of the SPI module that is going to be used.
+    *hal_module_id = pin_check_result;
+
+    // Insert current module into hal_ll_module_state map.
+    hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[ pin_check_result ].base;
+
+    // Return the same info about module one level up (into the HAL level).
+    handle_map[ pin_check_result ]->hal_ll_spi_master_handle = (handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle;
+
+    return HAL_LL_SPI_MASTER_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_module_configure_spi( handle_t *handle ) {
+    low_level_handle = hal_ll_spi_master_get_handle;
+    hal_ll_spi_master_pins_t index_list[ SPI_MODULE_COUNT ] = { HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC };
+    hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address);
+    uint8_t pin_check_result;
+
+    if ( HAL_LL_PIN_NC == ( pin_check_result = hal_ll_spi_master_check_pins( hal_ll_spi_master_hw_specifics_map_local->pins.sck,
+                                               hal_ll_spi_master_hw_specifics_map_local->pins.miso,
+                                               hal_ll_spi_master_hw_specifics_map_local->pins.mosi,
+                                               &index_list, (void *)0 )) ) {
+        return HAL_LL_SPI_MASTER_WRONG_PINS;
+    };
+
+    hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_local );
+
+    hal_ll_module_state[ pin_check_result ].hal_ll_spi_master_handle = (handle_t *)&hal_ll_spi_master_hw_specifics_map[ pin_check_result ].base;
+    hal_ll_module_state[ pin_check_result ].init_ll_state = true;
+
+    return HAL_LL_SPI_MASTER_SUCCESS;
+}
+
+void hal_ll_spi_master_set_default_write_data( handle_t *handle, uint8_t dummy_data ) {
+    low_level_handle = hal_ll_spi_master_get_handle;
+    // Get appropriate hw specifics map.
+    hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address);
+
+    hal_ll_spi_master_hw_specifics_map_local->dummy_data = dummy_data;
+}
+
+hal_ll_err_t hal_ll_spi_master_write( handle_t *handle, uint8_t *write_data_buffer, size_t length_data ) {
+    // Get low level HAL handle.
+    low_level_handle = hal_ll_spi_master_get_handle;
+
+    // Get appropriate hw specifics map.
+    hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address);
+
+    hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_hw_specifics_map_local, write_data_buffer, length_data );
+
+    return HAL_LL_SPI_MASTER_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_spi_master_read( handle_t *handle, uint8_t *read_data_buffer, size_t length_data ) {
+    // Get low level HAL handle.
+    low_level_handle = hal_ll_spi_master_get_handle;
+
+    // Get appropriate hw specifics map.
+    hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address);
+
+    hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_hw_specifics_map_local, read_data_buffer, length_data,
+                                       hal_ll_spi_master_hw_specifics_map_local->dummy_data );
+
+    return HAL_LL_SPI_MASTER_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_spi_master_write_then_read( handle_t *handle, uint8_t *write_data_buffer, size_t length_write_data,
+                                                uint8_t *read_data_buffer, size_t length_read_data ) {
+    // Get low level HAL handle.
+    low_level_handle = hal_ll_spi_master_get_handle;
+
+    // Get appropriate hw specifics map.
+    hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address);
+
+    hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_hw_specifics_map_local, write_data_buffer, length_write_data );
+
+    hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_hw_specifics_map_local, read_data_buffer, length_read_data,
+                                       hal_ll_spi_master_hw_specifics_map_local->dummy_data );
+
+    return HAL_LL_SPI_MASTER_SUCCESS;
+}
+
+uint32_t hal_ll_spi_master_set_speed( handle_t *handle, uint32_t speed ) {
+    // Get low level HAL handle.
+    low_level_handle = hal_ll_spi_master_get_handle;
+
+    // Get appropriate hw specifics map.
+    hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address);
+
+    low_level_handle->init_ll_state = false;
+
+    // Insert user-defined baud rate into local map.
+    hal_ll_spi_master_hw_specifics_map_local->speed = speed;
+
+    // Init once again, but with updated SPI Master baud rate value.
+    hal_ll_spi_master_init(hal_ll_spi_master_hw_specifics_map_local);
+
+    low_level_handle->init_ll_state = true;
+
+    // Return value of the SPI Master baud rate value.
+    return hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed;
+}
+
+hal_ll_err_t hal_ll_spi_master_set_mode( handle_t *handle, hal_ll_spi_master_mode_t mode ) {
+    // Get low level HAL handle.
+    low_level_handle = hal_ll_spi_master_get_handle;
+
+    // Get appropriate hw specifics map.
+    hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address);
+
+    low_level_handle->init_ll_state = false;
+
+    // Insert user-defined baud rate into local map.
+    hal_ll_spi_master_hw_specifics_map_local->mode = mode;
+
+    // Init once again, but with updated SPI Master mode value.
+    hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_local );
+
+    low_level_handle->init_ll_state = true;
+
+    // Return value of the SPI Master mode that is going to be used.
+    return HAL_LL_SPI_MASTER_SUCCESS;
+}
+
+void hal_ll_spi_master_close( handle_t* handle ) {
+    // Get low level HAL handle.
+    low_level_handle = hal_ll_spi_master_get_handle;
+
+    // Get appropriate hw specifics map.
+    hal_ll_spi_master_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_spi_master_get_module_state_address);
+
+    if( NULL != low_level_handle->hal_ll_spi_master_handle ) {
+        low_level_handle->hal_ll_spi_master_handle  = NULL;
+        low_level_handle->hal_drv_spi_master_handle  = NULL;
+        low_level_handle->init_ll_state = false;
+
+        hal_ll_spi_master_hw_specifics_map_local->mode = HAL_LL_SPI_MASTER_MODE_DEFAULT;
+        hal_ll_spi_master_hw_specifics_map_local->speed = HAL_LL_SPI_MASTER_SPEED_100K;
+        hal_ll_spi_master_hw_specifics_map_local->dummy_data = 0;
+        hal_ll_spi_master_hw_specifics_map_local->hw_actual_speed = 0;
+
+        hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_local, false );
+        hal_ll_spi_master_configure_pins( hal_ll_spi_master_hw_specifics_map_local, false );
+
+        hal_ll_spi_master_hw_specifics_map_local->pins.sck = HAL_LL_PIN_NC;
+        hal_ll_spi_master_hw_specifics_map_local->pins.miso = HAL_LL_PIN_NC;
+        hal_ll_spi_master_hw_specifics_map_local->pins.mosi = HAL_LL_PIN_NC;
+    }
+}
+
+// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS
+static uint8_t hal_ll_spi_master_transfer_bare_metal( hal_ll_spi_master_hw_specifics_map_t *map, uint8_t data_buffer ) {
+    const hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = hal_ll_spi_master_get_base_struct( map->base );
+
+    // Write user-defined data ( 'hal_ll_spi_master_read_bare_metal' procedure will send dummy data ).
+    write_reg( hal_ll_hw_reg->spi_spdr_reg_addr, data_buffer );
+
+    // Wait until transmission of byte is completed.
+    while ( !check_reg_bit( hal_ll_hw_reg->spi_spsr_reg_addr, HAL_LL_SPI_MASTER_TRANSFER_COMPLETE_FLAG_BIT ) );
+
+    // Return read data.
+    return read_reg( hal_ll_hw_reg->spi_spdr_reg_addr );
+}
+
+static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_hw_specifics_map_t *map, uint8_t *write_data_buffer,
+                                                size_t write_data_length ) {
+    uint16_t transfer_counter;
+    const hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = hal_ll_spi_master_get_base_struct( map->base );
+
+    // Write the first data to be transmitted into the SPI_DR register.
+    for( transfer_counter = 0; transfer_counter < write_data_length; transfer_counter++ ) {
+        // If we are good to go ( if the tx buffer value has been shifted to the shift register ), write the data.
+        hal_ll_spi_master_transfer_bare_metal( map, write_data_buffer[ transfer_counter ] );
+    }
+}
+
+static void hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_hw_specifics_map_t *map, uint8_t *read_data_buffer,
+                                               size_t read_data_length, uint8_t dummy_data ) {
+    const hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = hal_ll_spi_master_get_base_struct( map->base );
+    volatile uint16_t transfer_counter;
+
+    // Read the first data to be transmitted into the SPI_DR register.
+    for( transfer_counter = 0; transfer_counter < read_data_length; transfer_counter++ ) {
+        // If we are good to go (if the value from shift register has been shifted to the rx register), read the data.
+        read_data_buffer[ transfer_counter ] = hal_ll_spi_master_transfer_bare_metal( map, dummy_data );
+    }
+}
+
+static hal_ll_pin_name_t hal_ll_spi_master_check_pins( hal_ll_pin_name_t sck_pin, hal_ll_pin_name_t miso_pin,
+                                                       hal_ll_pin_name_t mosi_pin, hal_ll_spi_master_pins_t *index_list,
+                                                       hal_ll_spi_master_handle_register_t *handle_map ) {
+    static const uint8_t sck_map_size  = ( sizeof( _spi_sck_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) );
+    static const uint8_t miso_map_size = ( sizeof( _spi_miso_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) );
+    static const uint8_t mosi_map_size = ( sizeof( _spi_mosi_map ) ) / ( sizeof( hal_ll_spi_master_pin_map_t ) );
+    uint8_t hal_ll_module_id = 0;
+    uint8_t index_counter = 0;
+    uint8_t miso_index;
+    uint8_t mosi_index;
+    uint8_t sck_index;
+
+    if ( ( HAL_LL_PIN_NC == sck_pin ) || ( HAL_LL_PIN_NC == miso_pin ) || ( HAL_LL_PIN_NC == mosi_pin ) ) {
+        return HAL_LL_PIN_NC;
+    }
+
+    // Check pins from the specific pin maps with the user defined pins.
+    for ( sck_index = 0; sck_index < sck_map_size; sck_index++ ) {
+        if ( _spi_sck_map[sck_index].pin == sck_pin ) {
+            for ( miso_index = 0; miso_index < miso_map_size; miso_index++ ) {
+                if ( _spi_miso_map[miso_index].pin == miso_pin ) {
+                    if ( _spi_sck_map[sck_index].module_index ==_spi_miso_map[miso_index].module_index ) {
+                        for ( mosi_index = 0; mosi_index < mosi_map_size; mosi_index++ ) {
+                            if ( _spi_mosi_map[mosi_index ].pin ==  mosi_pin ) {
+                                if ( _spi_sck_map[sck_index].module_index ==_spi_mosi_map[mosi_index].module_index ) {
+                                    // Get module number
+                                    hal_ll_module_id = _spi_sck_map[ sck_index ].module_index;
+
+                                    // Map pin names
+                                    index_list[ hal_ll_module_id ]->sck = sck_index;
+                                    index_list[ hal_ll_module_id ]->miso = miso_index;
+                                    index_list[ hal_ll_module_id ]->mosi = mosi_index;
+                                    index_list[ hal_ll_module_id ]->ss = sck_index;
+
+                                    // Check if module is taken
+                                    if ( NULL == handle_map[hal_ll_module_id]->hal_drv_spi_master_handle ) {
+                                        return hal_ll_module_id;
+                                    } else if ( SPI_MODULE_COUNT == ++index_counter ) {
+                                        return --index_counter;
+                                    }
+                                }
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    if ( index_counter ) {
+        return hal_ll_module_id;
+    } else {
+        return HAL_LL_PIN_NC;
+    }
+}
+
+static void hal_ll_spi_master_map_pins( uint8_t module_index, hal_ll_spi_master_pins_t *index_list ) {
+    hal_ll_spi_master_hw_specifics_map[ module_index ].pins.sck  = _spi_sck_map[ index_list[ module_index ]->sck ].pin;
+    hal_ll_spi_master_hw_specifics_map[ module_index ].pins.miso = _spi_miso_map[ index_list[ module_index ]->miso ].pin;
+    hal_ll_spi_master_hw_specifics_map[ module_index ].pins.mosi = _spi_mosi_map[ index_list[ module_index ]->mosi ].pin;
+    #if defined (__hal_ll_spi_master_subset_atmega__)
+    hal_ll_spi_master_hw_specifics_map[ module_index ].pins.ss = _spi_ss_map[ index_list[ module_index ]->ss ].pin;
+    #endif
+}
+
+static hal_ll_spi_master_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) {
+    uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_spi_master_handle_register_t ) );
+
+    static uint8_t hal_ll_module_error = hal_ll_module_count;
+
+    while ( hal_ll_module_count-- ) {
+        if ( hal_ll_spi_master_get_base_from_hal_handle == hal_ll_spi_master_hw_specifics_map[ hal_ll_module_count ].base ) {
+            return &hal_ll_spi_master_hw_specifics_map[ hal_ll_module_count ];
+        }
+    }
+
+    // If NOK, return pointer to the last row of this map ( point to null pointer ).
+    return &hal_ll_spi_master_hw_specifics_map[ hal_ll_module_error ];
+}
+
+static void hal_ll_spi_master_configure_pins( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ) {
+    hal_ll_gpio_pin_t local_pin;
+
+    if ( ( HAL_LL_PIN_NC != map->pins.sck ) && ( HAL_LL_PIN_NC != map->pins.miso ) && ( HAL_LL_PIN_NC != map->pins.mosi ) ) {
+        if ( hal_ll_state ) {
+            hal_ll_gpio_configure_pin( &local_pin, map->pins.sck, HAL_LL_GPIO_DIGITAL_OUTPUT );
+            hal_ll_gpio_configure_pin( &local_pin, map->pins.miso, HAL_LL_GPIO_DIGITAL_INPUT );
+            hal_ll_gpio_configure_pin( &local_pin, map->pins.mosi, HAL_LL_GPIO_DIGITAL_OUTPUT );
+            #if defined (__hal_ll_spi_master_subset_atmega__)
+            hal_ll_gpio_configure_pin( &local_pin, map->pins.ss, HAL_LL_GPIO_DIGITAL_OUTPUT );
+            #endif
+        } else {
+            hal_ll_gpio_configure_pin( &local_pin, map->pins.sck, HAL_LL_GPIO_DIGITAL_INPUT );
+            hal_ll_gpio_configure_pin( &local_pin, map->pins.miso, HAL_LL_GPIO_DIGITAL_INPUT );
+            hal_ll_gpio_configure_pin( &local_pin, map->pins.mosi, HAL_LL_GPIO_DIGITAL_INPUT );
+            #if defined (__hal_ll_spi_master_subset_atmega__)
+            hal_ll_gpio_configure_pin( &local_pin, map->pins.ss, HAL_LL_GPIO_DIGITAL_INPUT );
+            #endif
+        }
+    }
+}
+
+static void hal_ll_spi_master_set_clock( hal_ll_spi_master_hw_specifics_map_t *map, bool hal_ll_state ) {
+    switch ( map->module_index ) {
+        #ifdef SPI_MODULE_0
+        #if defined (__hal_ll_spi_master_subset_atmega__)
+        #ifdef HAL_LL_PRR0_REG_ADDRESS
+        case hal_ll_spi_master_module_num( SPI_MODULE_0 ):
+            ( true == hal_ll_state )?(clear_reg_bit( HAL_LL_PRR0_REG_ADDRESS, HAL_LL_PRR0_PRSPI0_BIT )):
+            (set_reg_bit( HAL_LL_PRR0_REG_ADDRESS, HAL_LL_PRR0_PRSPI0_BIT ));
+            break;
+        #endif
+        #elif defined (__hal_ll_spi_master_subset_atxmega__)
+        #ifdef HAL_LL_PRPC_REG_ADDRESS
+        case hal_ll_spi_master_module_num( SPI_MODULE_0 ):
+            ( true == hal_ll_state )?(clear_reg_bit( HAL_LL_PRPC_REG_ADDRESS, HAL_LL_PRR_SPI_BIT )):(set_reg_bit( HAL_LL_PRPC_REG_ADDRESS, HAL_LL_PRR_SPI_BIT ));
+            break;
+        #endif
+        #endif
+        #endif
+
+        #ifdef SPI_MODULE_1
+        #if defined (__hal_ll_spi_master_subset_atmega__)
+        #ifdef HAL_LL_PRR2_REG_ADDRESS
+        case hal_ll_spi_master_module_num( SPI_MODULE_1 ):
+            ( true == hal_ll_state )?(clear_reg_bit( HAL_LL_PRR2_REG_ADDRESS, HAL_LL_PRR1_PRSPI1_BIT )):
+            (set_reg_bit( HAL_LL_PRR2_REG_ADDRESS, HAL_LL_PRR1_PRSPI1_BIT ));
+            break;
+        #endif
+        #elif defined (__hal_ll_spi_master_subset_atxmega__)
+        #ifdef HAL_LL_PRPD_REG_ADDRESS
+        case hal_ll_spi_master_module_num( SPI_MODULE_1 ):
+            ( true == hal_ll_state )?(clear_reg_bit( HAL_LL_PRPD_REG_ADDRESS, HAL_LL_PRR_SPI_BIT )):(set_reg_bit( HAL_LL_PRPD_REG_ADDRESS, HAL_LL_PRR_SPI_BIT ));
+            break;
+        #endif
+        #endif
+        #endif
+
+        #ifdef SPI_MODULE_2
+        #ifdef HAL_LL_PRPE_REG_ADDRESS
+        #if defined (__hal_ll_spi_master_subset_atxmega__)
+        case hal_ll_spi_master_module_num( SPI_MODULE_2 ):
+            ( true == hal_ll_state )?(clear_reg_bit( HAL_LL_PRPE_REG_ADDRESS, HAL_LL_PRR_SPI_BIT )):(set_reg_bit( HAL_LL_PRPE_REG_ADDRESS, HAL_LL_PRR_SPI_BIT ));
+            break;
+        #endif
+        #endif
+        #endif
+
+        #ifdef SPI_MODULE_3
+        #if defined (__hal_ll_spi_master_subset_atxmega__)
+        #ifdef HAL_LL_PRPF_REG_ADDRESS
+        case hal_ll_spi_master_module_num( SPI_MODULE_3 ):
+            ( true == hal_ll_state )?(clear_reg_bit( HAL_LL_PRPF_REG_ADDRESS, HAL_LL_PRR_SPI_BIT )):(set_reg_bit( HAL_LL_PRPF_REG_ADDRESS, HAL_LL_PRR_SPI_BIT ));
+            break;
+        #endif
+        #endif
+        #endif
+
+        default:
+            break;
+    }
+}
+
+static void hal_ll_spi_master_set_baud_rate( hal_ll_spi_master_hw_specifics_map_t *map ) {
+    // Get hardware register list for user-defined SPI pins.
+    const hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = hal_ll_spi_master_get_base_struct( map->base );
+
+    bool prescaler_bit_0 = 0;
+    bool prescaler_bit_1 = 0;
+    bool prescaler_bit_2 = 0;
+
+    // Calculate SPI speed via prescaler values that are eligible.
+    ( ( _fosc / HAL_LL_SPI_MASTER_CLK_BAUD_RATE_DIVIDER_2 ) <= map->speed )?( prescaler_bit_0 = true, prescaler_bit_1 = false, prescaler_bit_2 = false ):
+    ( ( ( _fosc / HAL_LL_SPI_MASTER_CLK_BAUD_RATE_DIVIDER_4 ) <= map->speed )?( prescaler_bit_0 = false, prescaler_bit_1 = false, prescaler_bit_2 = false ):
+    ( ( ( _fosc / HAL_LL_SPI_MASTER_CLK_BAUD_RATE_DIVIDER_8 ) <= map->speed )?( prescaler_bit_0 = true, prescaler_bit_1 = true, prescaler_bit_2 = false ):
+    ( ( ( _fosc / HAL_LL_SPI_MASTER_CLK_BAUD_RATE_DIVIDER_16 ) <= map->speed )?( prescaler_bit_0 = false, prescaler_bit_1 = true, prescaler_bit_2 = false ):
+    ( ( ( _fosc / HAL_LL_SPI_MASTER_CLK_BAUD_RATE_DIVIDER_32 ) <= map->speed )?( prescaler_bit_0 = true, prescaler_bit_1 = false, prescaler_bit_2 = true ):
+    ( ( ( _fosc / HAL_LL_SPI_MASTER_CLK_BAUD_RATE_DIVIDER_64 ) <= map->speed )?( prescaler_bit_0 = false, prescaler_bit_1 = false, prescaler_bit_2 = true ):
+    ( ( ( _fosc / HAL_LL_SPI_MASTER_CLK_BAUD_RATE_DIVIDER_128 ) <= map->speed )?( prescaler_bit_0 = false, prescaler_bit_1 = true, prescaler_bit_2 = true ):
+    ( prescaler_bit_0 = false, prescaler_bit_1 = true, prescaler_bit_2 = true ) ) ) ) ) ) );
+
+    // Configure SPI prescaler bit 0 (SPI2X bit) appropriately.
+    #if defined (__hal_ll_spi_master_subset_atmega__)
+    ( prescaler_bit_0 )?( set_reg_bit( hal_ll_hw_reg->spi_spsr_reg_addr, HAL_LL_SPI_MASTER_CLK_BAUD_RATE_BIT_0 ) ):
+    ( clear_reg_bit( hal_ll_hw_reg->spi_spsr_reg_addr, HAL_LL_SPI_MASTER_CLK_BAUD_RATE_BIT_0 ) );
+    #elif defined (__hal_ll_spi_master_subset_atxmega__)
+    ( prescaler_bit_0 )?( set_reg_bit( hal_ll_hw_reg->spi_spcr_reg_addr, HAL_LL_SPI_MASTER_CLK_BAUD_RATE_BIT_2 ) ):
+    ( clear_reg_bit( hal_ll_hw_reg->spi_spsr_reg_addr, HAL_LL_SPI_MASTER_CLK_BAUD_RATE_BIT_0 ) );
+    #endif
+
+    // Configure SPI prescaler bit 1 (SPR0 bit) appropriately.
+    ( prescaler_bit_1 )?( set_reg_bit( hal_ll_hw_reg->spi_spcr_reg_addr, HAL_LL_SPI_MASTER_CLK_BAUD_RATE_BIT_0 ) ):
+    ( clear_reg_bit( hal_ll_hw_reg->spi_spcr_reg_addr, HAL_LL_SPI_MASTER_CLK_BAUD_RATE_BIT_0 ) );
+
+    // Configure SPI prescaler bit 2 (SPR1 bit) appropriately.
+    ( prescaler_bit_2 )?( set_reg_bit( hal_ll_hw_reg->spi_spcr_reg_addr, HAL_LL_SPI_MASTER_CLK_BAUD_RATE_BIT_1 ) ):
+    ( clear_reg_bit( hal_ll_hw_reg->spi_spcr_reg_addr, HAL_LL_SPI_MASTER_CLK_BAUD_RATE_BIT_1 ) );
+}
+
+static void hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map ) {
+    // Get hardware register list for user-defined SPI pins.
+    const hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = hal_ll_spi_master_get_base_struct( map->base );
+
+    /* Clear SPI Control register:
+     * - disable SPI interrupt;
+     * - disable SPI module;
+     * - set MSB to be transmitted first;
+     * - set SPI Slave mode;
+     * - set SPI mode 0;
+     * - set SPI baud rate to be fosc/4.
+    */
+    clear_reg( hal_ll_hw_reg->spi_spcr_reg_addr );
+
+    // Set SPI master mode.
+    set_reg_bit( hal_ll_hw_reg->spi_spcr_reg_addr, HAL_LL_SPI_MASTER_MODE );
+
+    /* Set Clock Polarity.
+     * Choose whether idle state for the clock is high level (1) or low level (0).
+     */
+    if ( HAL_LL_SPI_MASTER_MODE_1 >= map->mode ) {
+        clear_reg_bit( hal_ll_hw_reg->spi_spcr_reg_addr, HAL_LL_SPI_MASTER_CLK_POLARITY );
+    } else {
+        set_reg_bit( hal_ll_hw_reg->spi_spcr_reg_addr, HAL_LL_SPI_MASTER_CLK_POLARITY );
+    }
+
+    /* Set Clock Phase.
+     * Choose whether transmit occurs on the transition from ACTIVE to IDLE ( 1 ), or vice versa ( 0 ).
+     */
+    if ( HAL_LL_SPI_MASTER_MODE_0 == map->mode || HAL_LL_SPI_MASTER_MODE_2 == map->mode ) {
+        clear_reg_bit( hal_ll_hw_reg->spi_spcr_reg_addr, HAL_LL_SPI_MASTER_CLK_PHASE );
+    } else {
+        set_reg_bit( hal_ll_hw_reg->spi_spcr_reg_addr, HAL_LL_SPI_MASTER_CLK_PHASE );
+    }
+
+    // Configure SPI speed.
+    hal_ll_spi_master_set_baud_rate( map );
+
+    // Enable SPI module.
+    set_reg_bit( hal_ll_hw_reg->spi_spcr_reg_addr, HAL_LL_SPI_MODULE_ENABLE );
+}
+
+static void hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_t *map ) {
+    // Enable specific clock module.
+    hal_ll_spi_master_set_clock ( map, true );
+
+    // Configure pins which are going to be used for SPI communication.
+    hal_ll_spi_master_configure_pins( map, true );
+
+    // Finally, write user-defined settings into hardware registers.
+    hal_ll_spi_master_hw_init( map );
+}
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/src/tim/CMakeLists.txt b/targets/avr_8bit/mikroe/avr/src/tim/CMakeLists.txt
new file mode 100644
index 000000000..56fad0d4d
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/tim/CMakeLists.txt
@@ -0,0 +1,79 @@
+set(hal_ll_def_list "")
+if((${CORE_NAME} MATCHES "GT64K") OR (${CORE_NAME} MATCHES "LTE64K"))
+    list(APPEND hal_ll_def_list "__avr_8_bit__")
+else()
+    list(APPEND hal_ll_def_list "__family_not_supported__")
+endif()
+
+list(APPEND hal_ll_def_list ${MCU_NAME})
+
+string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH)
+MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3")
+string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3)
+
+## BEGIN TIM
+if (${MCU_NAME} MATCHES "ATX")
+    set(tim_implementation "implementation_3")
+    list(APPEND hal_ll_def_list "HAL_LL_TIM4_CCCBUF_REG_ADDRESS=NULL")
+    list(APPEND hal_ll_def_list "HAL_LL_TIM4_CCDBUF_REG_ADDRESS=NULL")
+    list(APPEND hal_ll_def_list "HAL_LL_TIM5_CCCBUF_REG_ADDRESS=NULL")
+    list(APPEND hal_ll_def_list "HAL_LL_TIM5_CCDBUF_REG_ADDRESS=NULL")
+    list(APPEND hal_ll_def_list "HAL_LL_TIM6_CCCBUF_REG_ADDRESS=NULL")
+    list(APPEND hal_ll_def_list "HAL_LL_TIM6_CCDBUF_REG_ADDRESS=NULL")
+    list(APPEND hal_ll_def_list "HAL_LL_TIM7_CCCBUF_REG_ADDRESS=NULL")
+    list(APPEND hal_ll_def_list "HAL_LL_TIM7_CCDBUF_REG_ADDRESS=NULL")
+elseif ( ( ${MCU_NAME} MATCHES "^ATMEGA(16|32|64|128)4(A|P|PA)?$" ) OR ( ${MCU_NAME} MATCHES "^AT90USB(64|128)[67]$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA(64|128|256)[01]$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA168$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA(168|328)(A|P|PA)?$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA(168|324|328)PB$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA(16|32|64)M1$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA(16|32)U[24]$" ) OR ( ${MCU_NAME} MATCHES "^ATMEGA406$" ) OR ( ${MCU_NAME} MATCHES "^ATTINY16(34|7)$" ) )
+    set(tim_implementation "implementation_2")
+elseif (${MCU_NAME} MATCHES "AT")
+    set(tim_implementation "implementation_1")
+else()
+    set(tim_implementation "__mcu_not_supported__")
+endif()
+
+if (${MCU_NAME} MATCHES "^ATXMEGA(16|32)E5$")
+    list(APPEND hal_ll_def_list __hal_ll_tim_subset_atxmega_e5_series__)
+endif()
+## END TIM
+
+list(APPEND hal_ll_def_list "MACRO_USAGE_TIM")
+
+mikrosdk_add_library(lib_hal_ll_tim MikroSDK.HalLowLevel.TIM
+    ${tim_implementation}/hal_ll_tim.c
+
+    ../../include/hal_ll_target.h
+    ../../include/tim/hal_ll_tim.h
+)
+
+target_compile_definitions(lib_hal_ll_tim PUBLIC
+    ${hal_ll_def_list}
+)
+
+target_link_libraries(lib_hal_ll_tim PUBLIC
+    MikroC.Core
+    MikroSDK.HalLowLevelCore
+    MikroSDK.HalLowLevelCommon
+)
+
+string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER)
+target_include_directories(lib_hal_ll_tim
+    PRIVATE
+        ../../include
+        ../../include/gpio
+        ../../include/tim
+    INTERFACE
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include>
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include/gpio>
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include/tim>
+        $<INSTALL_INTERFACE:include/hal_ll_port>
+        $<INSTALL_INTERFACE:include/${MCU_NAME_LOWER}>
+)
+
+mikrosdk_install(MikroSDK.HalLowLevel.TIM)
+
+install(
+    FILES
+        ../../include/tim/hal_ll_tim.h
+        ../../include/tim/hal_ll_tim_pin_map.h
+    DESTINATION
+        ${CMAKE_INSTALL_PREFIX}/include/hal_ll_port
+)
diff --git a/targets/avr_8bit/mikroe/avr/src/tim/implementation_1/hal_ll_tim.c b/targets/avr_8bit/mikroe/avr/src/tim/implementation_1/hal_ll_tim.c
new file mode 100644
index 000000000..c7d41ad46
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/tim/implementation_1/hal_ll_tim.c
@@ -0,0 +1,886 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_tim.c
+ * @brief TIMER HAL LOW LEVEL layer implementation.
+ */
+
+#include "hal_ll_tim.h"
+#include "hal_ll_gpio.h"
+#include "hal_ll_tim_pin_map.h"
+
+/*!< @brief Local handle list */
+static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ] = { (handle_t *)NULL, (handle_t *)NULL, false };
+
+// ------------------------------------------------------------- PRIVATE MACROS
+/*!< @brief Helper macros for getting module specific index. */
+#define HAL_LL_TIM_8_BIT_MODULE_0 (0)
+#define HAL_LL_TIM_8_BIT_MODULE_2 (2)
+
+/*!< @brief Helper macro for getting module specific control register structure */
+#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle)
+
+/*!< @brief Helper macro for getting hal_ll_module_state address */
+#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle)
+
+/*!< @brief Helper macro for getting module specific control register structure base address // first register address */
+#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle
+
+/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */
+#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\
+                                            (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base
+
+/*!< @brief Helper macros for getting module specific prescaler register bit values. */
+#define HAL_LL_TIM_PRESCALER_REG_VALUE_1 (1)
+#define HAL_LL_TIM_PRESCALER_REG_VALUE_5 (5)
+#define HAL_LL_TIM_PRESCALER_REG_VALUE_7 (7)
+
+/*!< @brief Helper macro for stopping a timer module. */
+#define HAL_LL_TIM_8_BIT_TIMER_STOPPED (0x07)
+#define HAL_LL_TIM_16_BIT_TIMER_STOPPED (0x30)
+
+/*!< @brief Helper mask macros. */
+#define HAL_LL_TIM_8_BIT_MASK (0xFF)
+#define HAL_LL_TIM_8_BIT_SHIFT (8)
+#define HAL_LL_TIM_FORCE_OUTPUT_COMPARE_MATCH_BIT (7)
+
+/*!< @brief Helper macros for determining duty cycle ranges. */
+#define HAL_LL_TIM_DUTY_RATIO_MAX (1.0)
+#define HAL_LL_TIM_DUTY_RATIO_MIN (0.0)
+
+/*!< @brief Helper macros for getting appropriate PWM resolution. */
+#define HAL_LL_TIM_8_BIT_RESOLUTION (255)
+#define HAL_LL_TIM_8_BIT_RESOLUTION_MASK (256)
+#define HAL_LL_TIM_10_BIT_RESOLUTION (1024)
+#define HAL_LL_TIM_10_BIT_PWM_RESOLUTION_MASK (0x03)
+
+/*!< @brief Helper macros for applying non-inverting PWM mode. */
+#define HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_0 (4)
+#define HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_1 (5)
+#define HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_2 (7)
+
+/*!< @brief Helper macros for applying Fast PWM 10-bit resolution mode. */
+#define HAL_LL_TIM_FAST_PWM_10_BIT_RESOLUTION_BIT_0 (0)
+#define HAL_LL_TIM_FAST_PWM_10_BIT_RESOLUTION_BIT_1 (1)
+#define HAL_LL_TIM_FAST_PWM_10_BIT_RESOLUTION_BIT_2 (3)
+#define HAL_LL_TIM_FAST_PWM_10_BIT_RESOLUTION_BIT_3 (4)
+
+/*!< @brief Helper macros for applying Fast PWM 8-bit resolution mode. */
+#define HAL_LL_TIM_FAST_PWM_8_BIT_RESOLUTION_BIT_0 (6)
+#define HAL_LL_TIM_FAST_PWM_8_BIT_RESOLUTION_BIT_1 (3)
+
+/*!< @brief Helper macros for disconnecting PWM driver units. */
+#define HAL_LL_TIM_DISCONNECT_PWM_UNIT_A (0xC0)
+#define HAL_LL_TIM_DISCONNECT_PWM_UNIT_B (0x30)
+
+/*!< @brief Helper macro for getting current MCU clock value (in Hertz). */
+#define _fosc (Get_Fosc_kHz()*1000)
+// -------------------------------------------------------------- PRIVATE TYPES
+typedef struct {
+    /*!< @brief 8-bit Timer/Counter register specifics. */
+    hal_ll_base_addr_t pwm_tccrxa_reg_addr; // 8/16-bit Timer/Counter Control register A.
+    hal_ll_base_addr_t pwm_tcntx_reg_addr; // Timer/Counter register.
+    hal_ll_base_addr_t pwm_ocrxa_reg_addr; // Output Compare register A.
+    /*!< @brief 16-bit Timer/Counter register specifics. */
+    hal_ll_base_addr_t pwm_tccrxb_reg_addr; // Timer/Counter Control register B.
+    hal_ll_base_addr_t pwm_tcntxh_reg_addr; // Timer/Counter High register.
+    hal_ll_base_addr_t pwm_tcntxl_reg_addr; // Timer/Counter Low register.
+    hal_ll_base_addr_t pwm_ocrxah_reg_addr; // Output Compare register A High.
+    hal_ll_base_addr_t pwm_ocrxal_reg_addr; // Output Compare register A Low.
+    hal_ll_base_addr_t pwm_ocrxbh_reg_addr; // Output Compare register B High.
+    hal_ll_base_addr_t pwm_ocrxbl_reg_addr; // Output Compare register B Low.
+} hal_ll_tim_base_handle_t;
+
+/*!< @brief TIM hw specific pointers to functions. */
+typedef struct {
+    void ( *mapped_function_signal_start )( hal_ll_tim_base_handle_t * );
+    void ( *mapped_function_signal_stop )( hal_ll_tim_base_handle_t * );
+    void ( *mapped_function_set_duty )( hal_ll_tim_base_handle_t *, float );
+    void ( *mapped_function_set_prescaler )( hal_ll_tim_base_handle_t * );
+    void ( *mapped_function_hw_init_pwm_mode )( hal_ll_tim_base_handle_t * );
+} hal_ll_tim_functions;
+
+/*!< @brief TIM hw specific structure */
+typedef struct {
+    hal_ll_tim_base_handle_t *base;
+    hal_ll_pin_name_t pin;
+    uint32_t max_period;
+    uint32_t freq_hz;
+    uint8_t module_index;
+    uint8_t channel;
+    hal_ll_tim_functions mapped_functions;
+} hal_ll_tim_hw_specifics_map_t;
+
+/*!< @brief TIM hw specific error values */
+typedef enum {
+    HAL_LL_TIM_SUCCESS = 0,
+    HAL_LL_TIM_MODULE_ERROR,
+    HAL_LL_TIM_WRONG_PIN,
+
+    HAL_LL_TIM_ERROR = (-1)
+} hal_ll_tim_err_t;
+
+// ------------------------------------------------------------------ CONSTANTS
+/*!< @brief PWM ( CCP ) array */
+static hal_ll_tim_base_handle_t tim_ll_reg_offsets[ TIM_MODULE_COUNT + 1 ] = {
+    #ifdef TIM_MODULE_0
+    { HAL_LL_TIM0_TCCR0A_REG_ADDRESS, HAL_LL_TIM0_TCNT0_REG_ADDRESS, HAL_LL_TIM0_OCR0A_REG_ADDRESS },
+    #endif
+    #ifdef TIM_MODULE_1
+    { HAL_LL_TIM1_TCCR1A_REG_ADDRESS, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_TIM1_TCCR1B_REG_ADDRESS,
+      HAL_LL_TIM1_TCNT1H_REG_ADDRESS, HAL_LL_TIM1_TCNT1L_REG_ADDRESS, HAL_LL_TIM1_OCR1AH_REG_ADDRESS,
+      HAL_LL_TIM1_OCR1AL_REG_ADDRESS, HAL_LL_TIM1_OCR1BH_REG_ADDRESS, HAL_LL_TIM1_OCR1BL_REG_ADDRESS },
+    #endif
+    #ifdef TIM_MODULE_2
+    { HAL_LL_TIM2_TCCR2A_REG_ADDRESS, HAL_LL_TIM2_TCNT2_REG_ADDRESS, HAL_LL_TIM2_OCR2A_REG_ADDRESS },
+    #endif
+    #ifdef TIM_MODULE_3
+    { HAL_LL_TIM3_TCCR3A_REG_ADDRESS, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_TIM3_TCCR3B_REG_ADDRESS,
+      HAL_LL_TIM3_TCNT3H_REG_ADDRESS, HAL_LL_TIM3_TCNT3L_REG_ADDRESS, HAL_LL_TIM3_OCR3AH_REG_ADDRESS,
+      HAL_LL_TIM3_OCR3AL_REG_ADDRESS, HAL_LL_TIM3_OCR3BH_REG_ADDRESS, HAL_LL_TIM3_OCR3BL_REG_ADDRESS },
+    #endif
+
+    { HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC }
+};
+
+// ------------------------------------------------------------------ VARIABLES
+/*!< @brief TIM specific info */
+static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[ TIM_MODULE_COUNT + 1 ] = {
+    #ifdef TIM_MODULE_0
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_0) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+    #ifdef TIM_MODULE_1
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_1) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+    #ifdef TIM_MODULE_2
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_2) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+    #ifdef TIM_MODULE_3
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_3) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+
+    { &tim_ll_reg_offsets[ TIM_MODULE_COUNT ], HAL_LL_PIN_NC, 0, 0, HAL_LL_MODULE_ERROR, HAL_LL_TIM_CH_DEFAULT, NULL }
+};
+
+/*!< @brief Global handle variables used in functions */
+static volatile hal_ll_tim_handle_register_t  *low_level_handle;
+static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local;
+
+// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS
+/**
+  * @brief Get local hardware specific map.
+  *
+  * Checks handle value and returns address of adequate
+  * hal_ll_tim_hw_specifics_map array index.
+  *
+  * @param[in] handle - Object specific context handler.
+  * @return hal_ll_tim_hw_specifics_map_t Map address.
+  *
+  * Returns pre-defined map index address based on handle value,
+  * if handle is adequate.
+  */
+static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle );
+
+/**
+  * @brief Full TIM module initialization procedure.
+  *
+  * Initializes TIM module on hardware level, based on beforehand
+  * set configuration and module handler. Sets adequate pin alternate functions.
+  * Initializes module clock.
+  *
+  * @param[in] *map - Object specific context handler.
+  * @return none
+  *
+  */
+static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map );
+
+/**
+ * @brief Maps new-found module specific values.
+ *
+ * Maps pin names and PPS function values for
+ * TIM pin.
+ *
+ * @param[in] module_index TIM HW module index -- 0,1,2...
+ * @param[in] index Array with TIM pin map index values.
+ *
+ * @return  None
+ */
+static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index );
+
+/**
+  * @brief Check if pin is adequate.
+  *
+  * Checks tim pin the user has passed with pre-defined
+  * pin in tim map.
+  *
+  * @param[in] pin - TIM pre-defined pin name.
+  * @param[in] *index Array with TIM pin map index values.
+  * @param[in] *handle_map Structure with info about available TIM modules.
+  * @return hal_ll_pin_name_t Module index based on pin.
+  *
+  * Returns pre-defined module index from pin maps, if pin
+  * is adequate.
+  */
+static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map );
+
+/**
+ * @brief Set GPIO state.
+ *
+ * Sets adequate register
+ * values for adequate functionality.
+ *
+ * @param[in] *map - Object specific context handler.
+ * @param[in] hal_ll_state - init or deinit
+ *
+ * @return  none.
+ */
+static void _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state );
+
+/**
+  * @brief Map adequate function addresses.
+  *
+  * Function maps adequate function addresses.
+  *
+  * @param[in] hal_ll_module_id - Module index.
+  *
+  * @return none
+  *
+  */
+static inline void map_pointer_functions( uint8_t hal_ll_module_id, uint8_t channel );
+
+/**
+  * @brief Timer/Counter 0 and Timer/Counter 2 start function.
+  *
+  * Function starts generating PWM signal on Timer/Counter 0 and Timer/Counter 2 PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_0_and_timer_2_start( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter 1 and Timer/Counter 3 start function (channel A).
+  *
+  * Function starts generating PWM signal on Timer/Counter 1 and Timer/Counter 3 PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_1_and_timer_3_start_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter 1 and Timer/Counter 3 start function (channel B).
+  *
+  * Function starts generating PWM signal on Timer/Counter 1 and Timer/Counter 3 PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_1_and_timer_3_start_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter 0 and Timer/Counter 2 start function.
+  *
+  * Function stops generating PWM signal on Timer/Counter 0 and Timer/Counter 2 PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_0_and_timer_2_stop( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter 1 and Timer/Counter 3 stop function (channel A).
+  *
+  * Function stops generating PWM signal on Timer/Counter 1 and Timer/Counter 3 PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_1_and_timer_3_stop_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter 1 and Timer/Counter 3 stop function (channel B).
+  *
+  * Function stops generating PWM signal on Timer/Counter 1 and Timer/Counter 3 PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_1_and_timer_3_stop_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter 0 and Timer/Counter 2 set duty function.
+  *
+  * Function configures duty cycle on Timer/Counter 0 and Timer/Counter 2 PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  * @param[in] user_defined_duty - Defined PWM duty cycle.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_0_and_timer_2_set_duty( hal_ll_tim_base_handle_t *hal_ll_hw_reg, float user_defined_duty );
+
+/**
+  * @brief Timer/Counter 1 and Timer/Counter 3 set duty function (channel A).
+  *
+  * Function configures duty cycle on Timer/Counter 1 and Timer/Counter 3 PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  * @param[in] user_defined_duty - Defined PWM duty cycle.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_1_and_timer_3_set_duty_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg, float user_defined_duty );
+
+/**
+  * @brief Timer/Counter 1 and Timer/Counter 3 set duty function (channel B).
+  *
+  * Function configures duty cycle on Timer/Counter 1 and Timer/Counter 3 PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  * @param[in] user_defined_duty - Defined PWM duty cycle.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_1_and_timer_3_set_duty_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg, float user_defined_duty );
+
+/**
+  * @brief Timer/Counter 0 set prescaler function.
+  *
+  * Function configures prescaler value on Timer/Counter 0 module.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_0_set_prescaler( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter 2 set prescaler function.
+  *
+  * Function configures prescaler value on Timer/Counter 2 module.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_2_set_prescaler( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter 1 and Timer/Counter 3 set prescaler function.
+  *
+  * Function configures prescaler value on Timer/Counter 1 and Timer/Counter 3 modules.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_1_and_timer_3_set_prescaler( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Initialize Timer/Counter 0 and Timer/Counter 2 on hardware level (channel B).
+  *
+  * Initializes Timer/Counter 0 and/or Timer/Counter 2 modules on hardware level, based on beforehand
+  * set configuration and module handler.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_0_and_timer_2_hw_init_pwm_mode( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Initialize Timer/Counter 1 and Timer/Counter 3 on hardware level.
+  *
+  * Initializes Timer/Counter 1 and/or Timer/Counter 3 modules on hardware level, based on beforehand
+  * set configuration and module handler.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_1_and_timer_3_hw_init_pwm_mode( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS
+hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, uint8_t *hal_module_id ) {
+    uint8_t pin_check_result;
+    uint8_t index;
+
+    if (  HAL_LL_PIN_NC == ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) ) {
+        return HAL_LL_TIM_WRONG_PIN;
+    }
+
+    if ( ( hal_ll_tim_hw_specifics_map[ pin_check_result ].pin != pin ) ) {
+        _hal_ll_tim_map_pin( pin_check_result, index );
+
+        handle_map[ pin_check_result ]->init_ll_state = false;
+
+        hal_ll_module_state[ pin_check_result ].init_ll_state = false;
+    }
+
+    *hal_module_id = pin_check_result;
+
+    hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base;
+
+    handle_map[ pin_check_result ]->hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle;
+
+    return HAL_LL_TIM_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) {
+    uint8_t pin_check_result;
+    uint8_t index;
+
+    low_level_handle = hal_ll_tim_get_handle;
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    if ( HAL_LL_PIN_NC == ( pin_check_result = _hal_ll_tim_check_pin( hal_ll_tim_hw_specifics_map_local->pin, &index, (void *)0 ) ) ) {
+        return HAL_LL_TIM_WRONG_PIN;
+    }
+
+    _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local );
+
+    hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base;
+
+    return HAL_LL_TIM_SUCCESS;
+}
+
+uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) {
+    low_level_handle = hal_ll_tim_get_handle;
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base );
+
+    low_level_handle->init_ll_state = false;
+
+    hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz;
+
+    _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local );
+
+    // Configure PWM prescaler value (via function pointers).
+    ( hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_set_prescaler )
+    ( hal_ll_tim_hw_specifics_map_local->base );
+
+    low_level_handle->init_ll_state = true;
+
+    return hal_ll_tim_hw_specifics_map_local->max_period;
+}
+
+hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) {
+    low_level_handle = hal_ll_tim_get_handle;
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base );
+
+    if ( low_level_handle->init_ll_state == false ) {
+        _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local );
+        low_level_handle->init_ll_state = true;
+    }
+
+    // Set appropriate PWM duty cycle (via function pointers).
+    ( hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_set_duty )
+    ( hal_ll_tim_hw_specifics_map_local->base, duty_ratio );
+
+    return HAL_LL_TIM_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_tim_start( handle_t *handle ) {
+    low_level_handle = hal_ll_tim_get_handle;
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base );
+
+    // Enable PWM driver circuit, non-inverting submode (via function pointers).
+    ( hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_signal_start )
+    ( hal_ll_tim_hw_specifics_map_local->base );
+
+    return HAL_LL_TIM_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) {
+    low_level_handle = hal_ll_tim_get_handle;
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base );
+
+    // Disconnect PWM driver circuit (via function pointers).
+    ( hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_signal_stop )
+    ( hal_ll_tim_hw_specifics_map_local->base );
+
+    return HAL_LL_TIM_SUCCESS;
+}
+
+void hal_ll_tim_close( handle_t *handle ) {
+    low_level_handle = hal_ll_tim_get_handle;
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    if( low_level_handle->hal_ll_tim_handle != NULL ) {
+
+        low_level_handle->hal_ll_tim_handle = NULL;
+        low_level_handle->hal_drv_tim_handle = NULL;
+        low_level_handle->init_ll_state = false;
+
+        _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, false );
+
+        hal_ll_tim_hw_specifics_map_local->freq_hz = 0;
+        hal_ll_tim_hw_specifics_map_local->max_period = 0;
+        hal_ll_tim_hw_specifics_map_local->pin = HAL_LL_PIN_NC;
+        hal_ll_tim_hw_specifics_map_local->channel = HAL_LL_TIM_CH_DEFAULT;
+    }
+}
+
+// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS
+static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) {
+    uint8_t pin_num;
+    uint8_t index_counter = 0;
+    uint8_t hal_ll_module_id = 0;
+    static uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) );
+
+    if ( HAL_LL_PIN_NC == pin ) {
+        return HAL_LL_PIN_NC;
+    }
+
+    // Check if the selected pin is valid.
+    for ( pin_num = 0; pin_num < map_size; pin_num++ ) {
+        if ( _tim_map[ pin_num ].pin == pin ) {
+            // Get module number
+            hal_ll_module_id = _tim_map[ pin_num ].module_index;
+            map_pointer_functions( hal_ll_module_id, _tim_map[ pin_num ].channel );
+            if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) {
+                *index = pin_num;
+                return hal_ll_module_id;
+            } else if ( TIM_MODULE_COUNT == ++index_counter ) {
+                return --index_counter;
+            }
+        }
+    }
+    // By default return last error msg.
+    if ( index_counter ) {
+        return hal_ll_module_id;
+    } else {
+        return HAL_LL_PIN_NC;
+    }
+}
+
+static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) {
+    uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) );
+    static uint8_t hal_ll_module_error = hal_ll_module_count;
+
+    while( hal_ll_module_count-- ) {
+        if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base ) {
+            return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ];
+        }
+    }
+
+    return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ];
+}
+
+static void _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) {
+    hal_ll_gpio_pin_t pin;
+    hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base );
+
+    if ( hal_ll_state ) {
+        hal_ll_gpio_configure_pin( &pin, map->pin, HAL_LL_GPIO_DIGITAL_OUTPUT );
+    } else {
+        hal_ll_gpio_configure_pin( &pin, map->pin, HAL_LL_GPIO_DIGITAL_INPUT );
+    }
+}
+
+static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) {
+    // Memorize PWM pin.
+    hal_ll_tim_hw_specifics_map[ module_index ].pin = _tim_map[ index ].pin;
+
+    // Memorize PWM pin channel.
+    hal_ll_tim_hw_specifics_map[ module_index ].channel = _tim_map[ index ].channel;
+}
+
+static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) {
+    // Configure PWM pin.
+    _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, true );
+
+    // Hardware initialization of a Timer/Counter (PWM) module (via function pointers).
+    ( hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_hw_init_pwm_mode )
+    ( hal_ll_tim_hw_specifics_map_local->base );
+}
+
+// ---------------------------------------------------- STATIC POINTER FUNCTIONS
+static inline void map_pointer_functions( uint8_t hal_ll_module_id, uint8_t channel ) {
+    if ( ( HAL_LL_TIM_8_BIT_MODULE_0 == hal_ll_module_id ) || ( HAL_LL_TIM_8_BIT_MODULE_2 == hal_ll_module_id ) ) {
+        hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_signal_start = &ptr_function_timer_0_and_timer_2_start;
+        hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_signal_stop = &ptr_function_timer_0_and_timer_2_stop;
+        hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_set_duty = &ptr_function_timer_0_and_timer_2_set_duty;
+        hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_hw_init_pwm_mode = &ptr_function_timer_0_and_timer_2_hw_init_pwm_mode;
+
+        if ( HAL_LL_TIM_8_BIT_MODULE_0 == hal_ll_module_id ) {
+            hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_set_prescaler = &ptr_function_timer_0_set_prescaler;
+        } else {
+            hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_set_prescaler = &ptr_function_timer_2_set_prescaler;
+        }
+    } else {
+        switch ( channel ) {
+            case ( HAL_LL_TIM_CH_A ):
+                hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_signal_start = &ptr_function_timer_1_and_timer_3_start_ch_a;
+                hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_signal_stop = &ptr_function_timer_1_and_timer_3_stop_ch_a;
+                hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_set_duty = &ptr_function_timer_1_and_timer_3_set_duty_ch_a;
+                break;
+            case ( HAL_LL_TIM_CH_B ):
+                hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_signal_start = &ptr_function_timer_1_and_timer_3_start_ch_b;
+                hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_signal_stop = &ptr_function_timer_1_and_timer_3_stop_ch_b;
+                hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_set_duty = &ptr_function_timer_1_and_timer_3_set_duty_ch_b;
+                break;
+        }
+
+        hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_hw_init_pwm_mode = &ptr_function_timer_1_and_timer_3_hw_init_pwm_mode;
+        hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_set_prescaler = &ptr_function_timer_1_and_timer_3_set_prescaler;
+    }
+}
+
+static inline void ptr_function_timer_0_and_timer_2_start( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    // PWM driver enabled, non-inverting submode.
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_0 );
+    set_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_1 );
+}
+
+static inline void ptr_function_timer_1_and_timer_3_start_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg ){
+    // PWM driver enabled, non-inverting submode.
+    set_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_2 );
+}
+
+static inline void ptr_function_timer_1_and_timer_3_start_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg ){
+    // PWM driver enabled, non-inverting submode.
+    set_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_1 );
+}
+
+static inline void ptr_function_timer_0_and_timer_2_stop( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    // PWM driver disconnected.
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_0 );
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_1 );
+
+    // Timer/Counter stopped (no clock source).
+    clear_reg_bits( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_8_BIT_TIMER_STOPPED );
+}
+
+static inline void ptr_function_timer_1_and_timer_3_stop_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg ){
+    // PWM driver disconnected for Unit A, TCCR1A<7:6>
+    clear_reg_bits( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_DISCONNECT_PWM_UNIT_A );
+
+    // No clock source (Timer/Counter stopped), TCCR1B<2:0>
+    clear_reg_bits( hal_ll_hw_reg->pwm_tccrxb_reg_addr, HAL_LL_TIM_16_BIT_TIMER_STOPPED );
+}
+
+static inline void ptr_function_timer_1_and_timer_3_stop_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg ){
+    // PWM driver disconnected for Unit B, TCCR1A<5:4>
+    clear_reg_bits( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_DISCONNECT_PWM_UNIT_B );
+
+    // No clock source (Timer/Counter stopped), TCCR1B<2:0>
+    clear_reg_bits( hal_ll_hw_reg->pwm_tccrxb_reg_addr, HAL_LL_TIM_16_BIT_TIMER_STOPPED );
+}
+
+static inline void ptr_function_timer_0_and_timer_2_set_duty( hal_ll_tim_base_handle_t *hal_ll_hw_reg, float user_defined_duty ) {
+    if ( user_defined_duty >= HAL_LL_TIM_DUTY_RATIO_MAX ) {
+        write_reg( hal_ll_hw_reg->pwm_ocrxa_reg_addr, HAL_LL_TIM_8_BIT_MASK );
+    } else if ( user_defined_duty <= HAL_LL_TIM_DUTY_RATIO_MIN ) {
+        clear_reg( hal_ll_hw_reg->pwm_ocrxa_reg_addr );
+    } else {
+        write_reg( hal_ll_hw_reg->pwm_ocrxa_reg_addr, (uint8_t)( user_defined_duty * HAL_LL_TIM_8_BIT_RESOLUTION ) );
+    }
+}
+
+static inline void ptr_function_timer_1_and_timer_3_set_duty_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg, float user_defined_duty ){
+    if ( user_defined_duty >= HAL_LL_TIM_DUTY_RATIO_MAX ) {
+        _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, true );
+        write_reg( hal_ll_hw_reg->pwm_ocrxah_reg_addr, HAL_LL_TIM_10_BIT_PWM_RESOLUTION_MASK );
+        write_reg( hal_ll_hw_reg->pwm_ocrxal_reg_addr, HAL_LL_TIM_8_BIT_MASK );
+    } else if ( user_defined_duty <= HAL_LL_TIM_DUTY_RATIO_MIN ) {
+        _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, false );
+        clear_reg( hal_ll_hw_reg->pwm_ocrxah_reg_addr );
+        clear_reg( hal_ll_hw_reg->pwm_ocrxal_reg_addr );
+    } else {
+        _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, true );
+        clear_reg( hal_ll_hw_reg->pwm_tcntxh_reg_addr );
+        clear_reg( hal_ll_hw_reg->pwm_tcntxl_reg_addr );
+        uint16_t test_var = user_defined_duty * HAL_LL_TIM_10_BIT_RESOLUTION;
+
+        write_reg( hal_ll_hw_reg->pwm_ocrxah_reg_addr, test_var >> HAL_LL_TIM_8_BIT_SHIFT );
+        write_reg( hal_ll_hw_reg->pwm_ocrxal_reg_addr, (uint8_t)test_var );
+    }
+}
+
+static inline void ptr_function_timer_1_and_timer_3_set_duty_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg, float user_defined_duty ){
+    if ( user_defined_duty >= HAL_LL_TIM_DUTY_RATIO_MAX ) {
+        _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, true );
+        write_reg( hal_ll_hw_reg->pwm_ocrxbh_reg_addr, HAL_LL_TIM_10_BIT_PWM_RESOLUTION_MASK );
+        write_reg( hal_ll_hw_reg->pwm_ocrxbl_reg_addr, HAL_LL_TIM_8_BIT_MASK );
+    } else if ( user_defined_duty <= HAL_LL_TIM_DUTY_RATIO_MIN ) {
+        _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, false );
+        clear_reg( hal_ll_hw_reg->pwm_ocrxbh_reg_addr );
+        clear_reg( hal_ll_hw_reg->pwm_ocrxbl_reg_addr );
+    } else {
+        _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, true );
+        clear_reg( hal_ll_hw_reg->pwm_tcntxh_reg_addr );
+        clear_reg( hal_ll_hw_reg->pwm_tcntxl_reg_addr );
+        uint16_t test_var = user_defined_duty * HAL_LL_TIM_10_BIT_RESOLUTION;
+
+        write_reg( hal_ll_hw_reg->pwm_ocrxbh_reg_addr, test_var >> HAL_LL_TIM_8_BIT_SHIFT );
+        write_reg( hal_ll_hw_reg->pwm_ocrxbl_reg_addr, (uint8_t)test_var );
+    }
+}
+
+static inline void ptr_function_timer_0_set_prescaler( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    uint8_t local_loop_counter = 0;
+    uint8_t prescaler_value = 0;
+
+    // Prescaler divider array for Timer/Counter modules 0 and 1.
+    const volatile uint8_t prescaler_divider_array_0[HAL_LL_TIM_PRESCALER_REG_VALUE_5] = { 1, 8, 64, 256, 1024 };
+
+    // By default, set minimal PWM frequency available.
+    prescaler_value = HAL_LL_TIM_PRESCALER_REG_VALUE_5;
+    hal_ll_tim_hw_specifics_map_local->max_period = ( _fosc / ( ( prescaler_divider_array_0[sizeof(prescaler_divider_array_0) - 1] ) * HAL_LL_TIM_8_BIT_RESOLUTION_MASK ) );
+
+    // Check if better PWM frequency can be achieved.
+    for ( local_loop_counter = 0; local_loop_counter < sizeof(prescaler_divider_array_0); local_loop_counter++ ) {
+        if ( hal_ll_tim_hw_specifics_map_local->freq_hz >= ( _fosc / ( prescaler_divider_array_0[local_loop_counter] * HAL_LL_TIM_8_BIT_RESOLUTION_MASK ) ) ) {
+            prescaler_value = local_loop_counter + 1;
+            hal_ll_tim_hw_specifics_map_local->max_period = (_fosc / ( prescaler_divider_array_0[local_loop_counter] * HAL_LL_TIM_8_BIT_RESOLUTION_MASK ) );
+            break;
+        }
+    }
+
+    // Timer/Counter stopped (no clock source).
+    clear_reg_bits( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_8_BIT_TIMER_STOPPED );
+
+    // Set appropriate prescaler value.
+    set_reg_bits( hal_ll_hw_reg->pwm_tccrxa_reg_addr, prescaler_value );
+}
+
+static inline void ptr_function_timer_2_set_prescaler( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    uint8_t local_loop_counter = 0;
+    uint8_t prescaler_value = 0;
+
+    // Prescaler divider array for Timer/Counter module 2.
+    const volatile uint8_t prescaler_divider_array_1[HAL_LL_TIM_PRESCALER_REG_VALUE_7] = { 1, 8, 32, 64, 128, 256, 1024 };
+
+    // By default, set minimal PWM frequency available.
+    prescaler_value = HAL_LL_TIM_PRESCALER_REG_VALUE_7;
+    hal_ll_tim_hw_specifics_map_local->max_period = ( _fosc / ( prescaler_divider_array_1[sizeof(prescaler_divider_array_1) - 1] * HAL_LL_TIM_8_BIT_RESOLUTION_MASK ) );
+
+    // Check if better PWM frequency can be achieved.
+    for ( local_loop_counter = 0; local_loop_counter < sizeof(prescaler_divider_array_1); local_loop_counter++ ) {
+        if ( hal_ll_tim_hw_specifics_map_local->freq_hz >= ( _fosc / ( prescaler_divider_array_1[local_loop_counter] * HAL_LL_TIM_8_BIT_RESOLUTION_MASK ) ) ) {
+            prescaler_value = local_loop_counter + 1;
+            hal_ll_tim_hw_specifics_map_local->max_period = (_fosc / ( prescaler_divider_array_1[local_loop_counter] * HAL_LL_TIM_8_BIT_RESOLUTION_MASK ) );
+            break;
+        }
+    }
+    // Timer/Counter stopped (no clock source).
+    clear_reg_bits( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_8_BIT_TIMER_STOPPED );
+
+    // Set appropriate prescaler value.
+    set_reg_bits( hal_ll_hw_reg->pwm_tccrxa_reg_addr, prescaler_value );
+}
+
+static inline void ptr_function_timer_1_and_timer_3_set_prescaler( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    uint8_t local_loop_counter = 0;
+    uint8_t prescaler_value = 0;
+
+    // Prescaler divider array for Timer/Counter modules 0 and 1.
+    const volatile uint8_t prescaler_divider_array_0[HAL_LL_TIM_PRESCALER_REG_VALUE_5] = { 1, 8, 64, 256, 1024 };
+
+    // By default, set max PWM frequency available.
+    prescaler_value = HAL_LL_TIM_PRESCALER_REG_VALUE_1;
+    hal_ll_tim_hw_specifics_map_local->max_period = ( _fosc / ( prescaler_divider_array_0[sizeof(prescaler_divider_array_0) - 1] * HAL_LL_TIM_10_BIT_RESOLUTION ) );
+
+    // Check if better PWM frequency can be achieved.
+    for ( local_loop_counter = 0; local_loop_counter < sizeof(prescaler_divider_array_0); local_loop_counter++ ) {
+        if ( hal_ll_tim_hw_specifics_map_local->freq_hz >= _fosc / ( ( prescaler_divider_array_0[local_loop_counter] ) * HAL_LL_TIM_10_BIT_RESOLUTION ) ) {
+            prescaler_value = local_loop_counter + 1;
+            hal_ll_tim_hw_specifics_map_local->max_period = _fosc / ( ( prescaler_divider_array_0[local_loop_counter] ) * HAL_LL_TIM_10_BIT_RESOLUTION );
+            break;
+        }
+    }
+
+    // Set appropriate prescaler value.
+    set_reg_bits( hal_ll_hw_reg->pwm_tccrxb_reg_addr, prescaler_value );
+}
+
+static inline void ptr_function_timer_0_and_timer_2_hw_init_pwm_mode( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    // Do not force output compare match.
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_FORCE_OUTPUT_COMPARE_MATCH_BIT );
+
+    // Set Waveform Generation Mode to Fast PWM.
+    set_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_FAST_PWM_8_BIT_RESOLUTION_BIT_0 );
+    set_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_FAST_PWM_8_BIT_RESOLUTION_BIT_1 );
+
+    // PWM driver disconnected.
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_0 );
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_1 );
+
+    // Timer/Counter stopped (no clock source).
+    clear_reg_bits( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_8_BIT_TIMER_STOPPED );
+}
+
+static inline void ptr_function_timer_1_and_timer_3_hw_init_pwm_mode( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    // Set Waveform Generation Mode to Fast PWM, 10-bit, for controlling the duty.
+    set_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_FAST_PWM_10_BIT_RESOLUTION_BIT_0 );
+    set_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_FAST_PWM_10_BIT_RESOLUTION_BIT_1 );
+    set_reg_bit( hal_ll_hw_reg->pwm_tccrxb_reg_addr, HAL_LL_TIM_FAST_PWM_10_BIT_RESOLUTION_BIT_2 );
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxb_reg_addr, HAL_LL_TIM_FAST_PWM_10_BIT_RESOLUTION_BIT_3 );
+}
+
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/src/tim/implementation_2/hal_ll_tim.c b/targets/avr_8bit/mikroe/avr/src/tim/implementation_2/hal_ll_tim.c
new file mode 100644
index 000000000..eaabe89ea
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/tim/implementation_2/hal_ll_tim.c
@@ -0,0 +1,1016 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_tim.c
+ * @brief TIMER HAL LOW LEVEL layer implementation.
+ */
+
+#include "hal_ll_tim.h"
+#include "hal_ll_gpio.h"
+#include "hal_ll_tim_pin_map.h"
+
+/*!< @brief Local handle list */
+static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ] = { (handle_t *)NULL, (handle_t *)NULL, false };
+
+// ------------------------------------------------------------- PRIVATE MACROS
+/*!< @brief Helper macros for getting module specific index. */
+#define HAL_LL_TIM_8_BIT_MODULE_0 (0)
+#define HAL_LL_TIM_8_BIT_MODULE_2 (2)
+
+/*!< @brief Helper macro for getting module specific control register structure */
+#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle)
+
+/*!< @brief Helper macro for getting hal_ll_module_state address */
+#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle)
+
+/*!< @brief Helper macro for getting module specific control register structure base address // first register address */
+#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle
+
+/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */
+#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\
+                                            (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base
+
+/*!< @brief Helper macro for getting Power Reduction registers bits for Timer/Counter specific modules. */
+#define HAL_LL_TIM_MODULE_PRTIM0_BIT (5)
+#define HAL_LL_TIM_MODULE_PRTIM1_BIT (3)
+#define HAL_LL_TIM_MODULE_PRTIM2_BIT (6)
+#define HAL_LL_TIM_MODULE_PRTIM3_BIT (3)
+
+/*!< @brief Helper macros for getting module specific prescaler register bit values. */
+#define HAL_LL_TIM_PRESCALER_REG_VALUE_1 (1)
+#define HAL_LL_TIM_PRESCALER_REG_VALUE_5 (5)
+#define HAL_LL_TIM_PRESCALER_REG_VALUE_7 (7)
+
+/*!< @brief Helper macro for stopping a timer module. */
+#define HAL_LL_TIM_TIMER_STOPPED (0x07)
+
+/*!< @brief Helper mask macros. */
+#define HAL_LL_TIM_8_BIT_MASK (0xFF)
+#define HAL_LL_TIM_8_BIT_SHIFT (8)
+#define HAL_LL_TIM_FORCE_OUTPUT_COMPARE_MATCH_BIT_CH_A (7)
+#define HAL_LL_TIM_FORCE_OUTPUT_COMPARE_MATCH_BIT_CH_B (6)
+
+/*!< @brief Helper macros for determining duty cycle ranges. */
+#define HAL_LL_TIM_DUTY_RATIO_MAX (1.0)
+#define HAL_LL_TIM_DUTY_RATIO_MIN (0.0)
+
+/*!< @brief Helper macros for getting appropriate PWM resolution. */
+#define HAL_LL_TIM_8_BIT_RESOLUTION (255)
+#define HAL_LL_TIM_8_BIT_RESOLUTION_MASK (256)
+#define HAL_LL_TIM_10_BIT_RESOLUTION (1024)
+#define HAL_LL_TIM_10_BIT_PWM_RESOLUTION_MASK (0x03)
+
+/*!< @brief Helper macros for applying non-inverting PWM mode. */
+#define HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_0 (4)
+#define HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_1 (5)
+#define HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_2 (6)
+#define HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_3 (7)
+
+/*!< @brief Helper macros for applying Fast PWM 8-bit resolution mode. */
+#define HAL_LL_TIM_FAST_PWM_8_BIT_RESOLUTION_BIT_0 (0)
+#define HAL_LL_TIM_FAST_PWM_8_BIT_RESOLUTION_BIT_1 (1)
+#define HAL_LL_TIM_FAST_PWM_8_BIT_RESOLUTION_BIT_2 (3)
+
+/*!< @brief Helper macro for getting current MCU clock value (in Hertz). */
+#define _fosc (Get_Fosc_kHz()*1000)
+
+// -------------------------------------------------------------- PRIVATE TYPES
+typedef struct {
+    hal_ll_base_addr_t pwm_tccrxa_reg_addr; // Timer/Counter Control register A.
+    hal_ll_base_addr_t pwm_tccrxb_reg_addr; // Timer/Counter Control register B.
+    hal_ll_base_addr_t pwm_tccrxc_reg_addr; // Timer/Counter Control register C (Non-existant for Timer/Counter0 and 2 modules).
+    hal_ll_base_addr_t pwm_tcntxh_reg_addr; // Timer/Counter High register (Non-existant for Timer/Counter0 and 2 modules).
+    hal_ll_base_addr_t pwm_tcntxl_reg_addr; // Timer/Counter Low register.
+    hal_ll_base_addr_t pwm_ocrxah_reg_addr; // Output Compare register A High (Non-existant for Timer/Counter0 and 2 modules).
+    hal_ll_base_addr_t pwm_ocrxal_reg_addr; // Output Compare register A Low.
+    hal_ll_base_addr_t pwm_ocrxbh_reg_addr; // Output Compare register B High (Non-existant for Timer/Counter0 and 2 modules).
+    hal_ll_base_addr_t pwm_ocrxbl_reg_addr; // Output Compare register B Low.
+} hal_ll_tim_base_handle_t;
+
+/*!< @brief TIM hw specific pointers to functions. */
+typedef struct {
+    void ( *mapped_function_signal_start )( hal_ll_tim_base_handle_t * );
+    void ( *mapped_function_signal_stop )( hal_ll_tim_base_handle_t * );
+    void ( *mapped_function_set_duty )( hal_ll_tim_base_handle_t *, float );
+    void ( *mapped_function_set_prescaler )( hal_ll_tim_base_handle_t * );
+    void ( *mapped_function_hw_init_pwm_mode )( hal_ll_tim_base_handle_t * );
+} hal_ll_tim_functions;
+
+/*!< @brief TIM hw specific structure */
+typedef struct {
+    hal_ll_tim_base_handle_t *base;
+    hal_ll_pin_name_t pin;
+    uint32_t max_period;
+    uint32_t freq_hz;
+    uint8_t module_index;
+    uint8_t channel;
+    hal_ll_tim_functions mapped_functions;
+} hal_ll_tim_hw_specifics_map_t;
+
+/*!< @brief TIM hw specific error values */
+typedef enum {
+    HAL_LL_TIM_SUCCESS = 0,
+    HAL_LL_TIM_MODULE_ERROR,
+    HAL_LL_TIM_WRONG_PIN,
+
+    HAL_LL_TIM_ERROR = (-1)
+} hal_ll_tim_err_t;
+
+// ------------------------------------------------------------------ CONSTANTS
+/*!< @brief PWM ( CCP ) array */
+static hal_ll_tim_base_handle_t tim_ll_reg_offsets[ TIM_MODULE_COUNT + 1 ] = {
+    #ifdef TIM_MODULE_0
+    { HAL_LL_TIM0_TCCR0A_REG_ADDRESS, HAL_LL_TIM0_TCCR0B_REG_ADDRESS, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_TIM0_TCNT0_REG_ADDRESS,
+      HAL_LL_PIN_NC, HAL_LL_TIM0_OCR0A_REG_ADDRESS, HAL_LL_PIN_NC, HAL_LL_TIM0_OCR0B_REG_ADDRESS },
+    #endif
+    #ifdef TIM_MODULE_1
+    { HAL_LL_TIM1_TCCR1A_REG_ADDRESS, HAL_LL_TIM1_TCCR1B_REG_ADDRESS, HAL_LL_TIM1_TCCR1C_REG_ADDRESS, HAL_LL_TIM1_TCNT1H_REG_ADDRESS,
+      HAL_LL_TIM1_TCNT1L_REG_ADDRESS, HAL_LL_TIM1_OCR1AH_REG_ADDRESS, HAL_LL_TIM1_OCR1AL_REG_ADDRESS, HAL_LL_TIM1_OCR1BH_REG_ADDRESS,
+      HAL_LL_TIM1_OCR1BL_REG_ADDRESS },
+    #endif
+    #ifdef TIM_MODULE_2
+    { HAL_LL_TIM2_TCCR2A_REG_ADDRESS, HAL_LL_TIM2_TCCR2B_REG_ADDRESS, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_TIM2_TCNT2_REG_ADDRESS,
+      HAL_LL_PIN_NC, HAL_LL_TIM2_OCR2A_REG_ADDRESS, HAL_LL_PIN_NC, HAL_LL_TIM2_OCR2B_REG_ADDRESS },
+    #endif
+    #ifdef TIM_MODULE_3
+    { HAL_LL_TIM3_TCCR3A_REG_ADDRESS, HAL_LL_TIM3_TCCR3B_REG_ADDRESS, HAL_LL_TIM3_TCCR3C_REG_ADDRESS, HAL_LL_TIM3_TCNT3H_REG_ADDRESS,
+      HAL_LL_TIM3_TCNT3L_REG_ADDRESS, HAL_LL_TIM3_OCR3AH_REG_ADDRESS, HAL_LL_TIM3_OCR3AL_REG_ADDRESS, HAL_LL_TIM3_OCR3BH_REG_ADDRESS,
+      HAL_LL_TIM3_OCR3BL_REG_ADDRESS },
+    #endif
+    #ifdef TIM_MODULE_4
+    { HAL_LL_TIM4_TCCR4A_REG_ADDRESS, HAL_LL_TIM4_TCCR4B_REG_ADDRESS, HAL_LL_TIM4_TCCR4C_REG_ADDRESS, HAL_LL_TIM4_TCNT4H_REG_ADDRESS,
+      HAL_LL_TIM4_TCNT4L_REG_ADDRESS, HAL_LL_TIM4_OCR4AH_REG_ADDRESS, HAL_LL_TIM4_OCR4AL_REG_ADDRESS, HAL_LL_TIM4_OCR4BH_REG_ADDRESS,
+      HAL_LL_TIM4_OCR4BL_REG_ADDRESS },
+    #endif
+    #ifdef TIM_MODULE_5
+    { HAL_LL_TIM5_TCCR5A_REG_ADDRESS, HAL_LL_TIM5_TCCR5B_REG_ADDRESS, HAL_LL_TIM5_TCCR5C_REG_ADDRESS, HAL_LL_TIM5_TCNT5H_REG_ADDRESS,
+      HAL_LL_TIM5_TCNT5L_REG_ADDRESS, HAL_LL_TIM5_OCR5AH_REG_ADDRESS, HAL_LL_TIM5_OCR5AL_REG_ADDRESS, HAL_LL_TIM5_OCR5BH_REG_ADDRESS,
+      HAL_LL_TIM5_OCR5BL_REG_ADDRESS },
+    #endif
+
+    { HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC }
+};
+
+// ------------------------------------------------------------------ VARIABLES
+/*!< @brief TIM specific info */
+static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[ TIM_MODULE_COUNT + 1 ] = {
+    #ifdef TIM_MODULE_0
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_0) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+    #ifdef TIM_MODULE_1
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_1) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+    #ifdef TIM_MODULE_2
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_2) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+    #ifdef TIM_MODULE_3
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_3) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+    #ifdef TIM_MODULE_4
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_4) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+    #ifdef TIM_MODULE_5
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_5) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_5), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+
+    { &tim_ll_reg_offsets[ TIM_MODULE_COUNT ], HAL_LL_PIN_NC, 0, 0, HAL_LL_MODULE_ERROR, HAL_LL_TIM_CH_DEFAULT, NULL }
+};
+
+/*!< @brief Global handle variables used in functions */
+static volatile hal_ll_tim_handle_register_t  *low_level_handle;
+static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local;
+
+// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS
+/**
+  * @brief Enable module for TIM module on hardware level.
+  *
+  * Initializes TIM module on hardware level, based on beforehand
+  * set configuration and module handler.
+  *
+  * @param[in] *map - Object specific context handler.
+  * @param[in] hal_ll_state - True(enable Timer/Counter module)/False(disable Timer/Counter module).
+  *
+  * @return void None.
+  */
+static void _hal_ll_tim_set_module_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state );
+
+/**
+  * @brief Get local hardware specific map.
+  *
+  * Checks handle value and returns address of adequate
+  * hal_ll_tim_hw_specifics_map array index.
+  *
+  * @param[in] handle - Object specific context handler.
+  *
+  * @return hal_ll_tim_hw_specifics_map_t Map address.
+  *
+  * Returns pre-defined map index address based on handle value,
+  * if handle is adequate.
+  */
+static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle );
+
+/**
+  * @brief Full TIM module initialization procedure.
+  *
+  * Initializes TIM module on hardware level, based on beforehand
+  * set configuration and module handler. Sets adequate pin alternate functions.
+  * Initializes module clock.
+  *
+  * @param[in] *map - Object specific context handler.
+  * @return none
+  *
+  */
+static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map );
+
+/**
+ * @brief Maps new-found module specific values.
+ *
+ * Maps pin names and PPS function values for
+ * TIM pin.
+ *
+ * @param[in] module_index TIM HW module index -- 0,1,2...
+ * @param[in] index_list  Array with TIM pin map index values.
+ *
+ * @return  None
+ */
+static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index );
+
+/**
+  * @brief Check if pin is adequate.
+  *
+  * Checks tim pin the user has passed with pre-defined
+  * pin in tim map.
+  *
+  * @param[in] pin - TIM pre-defined pin name.
+  * @param[in] *index Array with TIM pin map index values.
+  * @param[in] *handle_map Structure with info about available TIM modules.
+  *
+  * @return hal_ll_pin_name_t Module index based on pin.
+  *
+  * Returns pre-defined module index from pin maps, if pin
+  * is adequate.
+  */
+static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map );
+
+/**
+ * @brief Set GPIO state.
+ *
+ * Sets adequate TRISx register
+ * values for adequate functionality.
+ *
+ * @param[in] *map - Object specific context handler.
+ * @param[in] hal_ll_state - init or deinit
+ *
+ * @return  none.
+ *
+ */
+static void _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state );
+
+/**
+  * @brief Map adequate function addresses.
+  *
+  * Function maps adequate function addresses.
+  *
+  * @param[in] hal_ll_module_id - Module index.
+  *
+  * @return none
+  *
+  */
+static inline void map_pointer_functions( uint8_t hal_ll_module_id, uint8_t channel );
+
+/**
+  * @brief Timer/Counter start function (channel A).
+  *
+  * Function starts generating PWM signal on Timer/Counter PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_start_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter start function (channel B).
+  *
+  * Function starts generating PWM signal on Timer/Counter PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_start_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter stop function (channel A).
+  *
+  * Function stops generating PWM signal on Timer/Counter PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_stop_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter stop function (channel B).
+  *
+  * Function stops generating PWM signal on Timer/Counter PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_stop_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter 0 and Timer/Counter 2 set duty function (channel A).
+  *
+  * Function configures duty cycle on Timer/Counter 0 and Timer/Counter 2 PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  * @param[in] user_defined_duty - Defined PWM duty cycle.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_0_and_timer_2_set_duty_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg, float user_defined_duty );
+
+/**
+  * @brief Timer/Counter 0 and Timer/Counter 2 set duty function (channel B).
+  *
+  * Function configures duty cycle on Timer/Counter 0 and Timer/Counter 2 PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  * @param[in] user_defined_duty - Defined PWM duty cycle.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_0_and_timer_2_set_duty_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg, float user_defined_duty );
+
+/**
+  * @brief Timer/Counter modules 1, 3, 4 and 5 set duty function (channel A).
+  *
+  * Function configures duty cycle on Timer/Counter 1 and Timer/Counter 3 PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  * @param[in] user_defined_duty - Defined PWM duty cycle.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timers_1_3_4_5_set_duty_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg, float user_defined_duty );
+
+/**
+  * @brief Timer/Counter modules 1, 3, 4 and 5 set duty function (channel B).
+  *
+  * Function configures duty cycle on Timer/Counter 1 and Timer/Counter 3 PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  * @param[in] user_defined_duty - Defined PWM duty cycle.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timers_1_3_4_5_set_duty_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg, float user_defined_duty );
+
+/**
+  * @brief Timer/Counter 0 set prescaler function.
+  *
+  * Function configures prescaler value on Timer/Counter 0 module.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_0_set_prescaler( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter 2 set prescaler function.
+  *
+  * Function configures prescaler value on Timer/Counter 2 module.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_2_set_prescaler( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter 1 and Timer/Counter 3 set prescaler function.
+  *
+  * Function configures prescaler value on Timer/Counter 1 and Timer/Counter 3 modules.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_1_and_timer_3_set_prescaler( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Initialize Timer/Counter 0 and Timer/Counter 2 on hardware level (channel A).
+  *
+  * Initializes Timer/Counter 0 and/or Timer/Counter 2 modules on hardware level, based on beforehand
+  * set configuration and module handler.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_0_and_timer_2_hw_init_pwm_mode_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Initialize Timer/Counter 0 and Timer/Counter 2 on hardware level (channel B).
+  *
+  * Initializes Timer/Counter 0 and/or Timer/Counter 2 modules on hardware level, based on beforehand
+  * set configuration and module handler.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_0_and_timer_2_hw_init_pwm_mode_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Initialize Timer/Counter 1 and Timer/Counter 3 on hardware level (channel A).
+  *
+  * Initializes Timer/Counter 1 and/or Timer/Counter 3 modules on hardware level, based on beforehand
+  * set configuration and module handler.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_1_and_timer_3_hw_init_pwm_mode_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Initialize Timer/Counter 1 and Timer/Counter 3 on hardware level (channel B).
+  *
+  * Initializes Timer/Counter 1 and/or Timer/Counter 3 modules on hardware level, based on beforehand
+  * set configuration and module handler.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_1_and_timer_3_hw_init_pwm_mode_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS
+hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, uint8_t *hal_module_id ) {
+    uint8_t pin_check_result;
+    uint8_t index;
+
+    if ( HAL_LL_PIN_NC == ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) ) {
+        return HAL_LL_TIM_WRONG_PIN;
+    }
+
+    if ( ( hal_ll_tim_hw_specifics_map[ pin_check_result ].pin != pin ) ) {
+        _hal_ll_tim_map_pin( pin_check_result, index );
+
+        handle_map[ pin_check_result ]->init_ll_state = false;
+
+        hal_ll_module_state[ pin_check_result ].init_ll_state = false;
+    }
+
+    *hal_module_id = pin_check_result;
+
+    hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base;
+
+    handle_map[ pin_check_result ]->hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle;
+
+    return HAL_LL_TIM_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) {
+    uint8_t pin_check_result;
+    uint8_t index;
+
+    low_level_handle = hal_ll_tim_get_handle;
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    if ( HAL_LL_PIN_NC == ( pin_check_result = _hal_ll_tim_check_pin( hal_ll_tim_hw_specifics_map_local->pin, &index, (void *)0 ) ) ) {
+        return HAL_LL_TIM_WRONG_PIN;
+    }
+
+    _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local );
+
+    hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base;
+
+    return HAL_LL_TIM_SUCCESS;
+}
+
+uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) {
+    low_level_handle = hal_ll_tim_get_handle;
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base );
+
+    low_level_handle->init_ll_state = false;
+
+    hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz;
+
+    _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local );
+
+    // Configure PWM prescaler value (via function pointers).
+    ( hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_set_prescaler )
+    ( hal_ll_tim_hw_specifics_map_local->base );
+
+    low_level_handle->init_ll_state = true;
+
+    return hal_ll_tim_hw_specifics_map_local->max_period;
+}
+
+hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) {
+    low_level_handle = hal_ll_tim_get_handle;
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base );
+
+    if ( low_level_handle->init_ll_state == false ) {
+        _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local );
+        low_level_handle->init_ll_state = true;
+    }
+
+    // Set appropriate PWM duty cycle (via function pointers).
+    ( hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_set_duty )
+    ( hal_ll_tim_hw_specifics_map_local->base, duty_ratio );
+
+    return HAL_LL_TIM_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_tim_start( handle_t *handle ) {
+    low_level_handle = hal_ll_tim_get_handle;
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base );
+
+    // Enable PWM driver circuit, non-inverting submode (via function pointers).
+    ( hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_signal_start )
+    ( hal_ll_tim_hw_specifics_map_local->base );
+
+    return HAL_LL_TIM_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) {
+    low_level_handle = hal_ll_tim_get_handle;
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base );
+
+    // Disconnect PWM driver circuit (via function pointers).
+    ( hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_signal_stop )
+    ( hal_ll_tim_hw_specifics_map_local->base );
+
+    return HAL_LL_TIM_SUCCESS;
+}
+
+void hal_ll_tim_close( handle_t *handle ) {
+    low_level_handle = hal_ll_tim_get_handle;
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    if( NULL != low_level_handle->hal_ll_tim_handle ) {
+
+        low_level_handle->hal_ll_tim_handle = NULL;
+        low_level_handle->hal_drv_tim_handle = NULL;
+        low_level_handle->init_ll_state = false;
+
+        _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, false );
+        _hal_ll_tim_set_module_state( hal_ll_tim_hw_specifics_map_local->module_index, false );
+
+        hal_ll_tim_hw_specifics_map_local->freq_hz = 0;
+        hal_ll_tim_hw_specifics_map_local->max_period = 0;
+        hal_ll_tim_hw_specifics_map_local->pin = HAL_LL_PIN_NC;
+        hal_ll_tim_hw_specifics_map_local->channel = HAL_LL_TIM_CH_DEFAULT;
+    }
+}
+
+// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS
+static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) {
+    uint8_t pin_num;
+    uint8_t index_counter = 0;
+    uint8_t hal_ll_module_id = 0;
+    static uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) );
+
+    if ( HAL_LL_PIN_NC == pin ) {
+        return HAL_LL_PIN_NC;
+    }
+
+    // Check if the selected pin is valid.
+    for ( pin_num = 0; pin_num < map_size; pin_num++ ) {
+        if ( _tim_map[ pin_num ].pin == pin ) {
+            // Get module number
+            hal_ll_module_id = _tim_map[ pin_num ].module_index;
+            map_pointer_functions( hal_ll_module_id, _tim_map[ pin_num ].channel );
+            if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) {
+                *index = pin_num;
+                return hal_ll_module_id;
+            } else if ( TIM_MODULE_COUNT == ++index_counter ) {
+                return --index_counter;
+            }
+        }
+    }
+    // By default return last error msg.
+    if ( index_counter ) {
+        return hal_ll_module_id;
+    } else {
+        return HAL_LL_PIN_NC;
+    }
+}
+
+static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) {
+    uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) );
+    static uint8_t hal_ll_module_error = hal_ll_module_count;
+
+    while( hal_ll_module_count-- ) {
+        if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map[ hal_ll_module_count ].base ) {
+            return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ];
+        }
+    }
+
+    return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ];
+}
+
+static void _hal_ll_tim_set_module_state( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) {
+    switch ( hal_ll_tim_hw_specifics_map_local->module_index ) {
+        #ifdef TIM_MODULE_0
+            case ( hal_ll_tim_module_num(TIM_MODULE_0) ):
+                if ( hal_ll_state ){
+                    clear_reg_bit( HAL_LL_PRR0_REG_ADDRESS, HAL_LL_TIM_MODULE_PRTIM0_BIT );
+                } else {
+                    set_reg_bit( HAL_LL_PRR0_REG_ADDRESS, HAL_LL_TIM_MODULE_PRTIM0_BIT );
+                }
+                break;
+        #endif
+        #ifdef TIM_MODULE_1
+            case ( hal_ll_tim_module_num(TIM_MODULE_1) ):
+                if ( hal_ll_state ){
+                    clear_reg_bit( HAL_LL_PRR0_REG_ADDRESS, HAL_LL_TIM_MODULE_PRTIM1_BIT );
+                } else {
+                    set_reg_bit( HAL_LL_PRR0_REG_ADDRESS, HAL_LL_TIM_MODULE_PRTIM1_BIT );
+                }
+                break;
+        #endif
+        #ifdef TIM_MODULE_2
+            case ( hal_ll_tim_module_num(TIM_MODULE_2) ):
+                if ( hal_ll_state ){
+                    clear_reg_bit( HAL_LL_PRR0_REG_ADDRESS, HAL_LL_TIM_MODULE_PRTIM2_BIT );
+                } else {
+                    set_reg_bit( HAL_LL_PRR0_REG_ADDRESS, HAL_LL_TIM_MODULE_PRTIM2_BIT );
+                }
+                break;
+        #endif
+        #ifdef TIM_MODULE_3
+            case ( hal_ll_tim_module_num(TIM_MODULE_3) ):
+                if ( hal_ll_state ){
+                    clear_reg_bit( HAL_LL_PRR1_REG_ADDRESS, HAL_LL_TIM_MODULE_PRTIM3_BIT );
+                } else {
+                    set_reg_bit( HAL_LL_PRR1_REG_ADDRESS, HAL_LL_TIM_MODULE_PRTIM3_BIT );
+                }
+                break;
+        #endif
+
+        default:
+            break;
+    }
+}
+
+static void _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) {
+    hal_ll_gpio_pin_t pin;
+    hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base );
+
+    if ( hal_ll_state ) {
+        hal_ll_gpio_configure_pin( &pin, map->pin, HAL_LL_GPIO_DIGITAL_OUTPUT );
+    } else {
+        hal_ll_gpio_configure_pin( &pin, map->pin, HAL_LL_GPIO_DIGITAL_INPUT );
+    }
+}
+
+static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) {
+    // Memorize PWM pin.
+    hal_ll_tim_hw_specifics_map[ module_index ].pin = _tim_map[ index ].pin;
+
+    // Memorize PWM pin channel.
+    hal_ll_tim_hw_specifics_map[ module_index ].channel = _tim_map[ index ].channel;
+}
+
+static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) {
+    _hal_ll_tim_set_module_state( map, true );
+
+    _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, true );
+
+    // Hardware initialization of a Timer/Counter (PWM) module (via function pointers).
+    ( hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_hw_init_pwm_mode )
+    ( hal_ll_tim_hw_specifics_map_local->base );
+}
+
+// ---------------------------------------------------- STATIC POINTER FUNCTIONS
+static inline void map_pointer_functions( uint8_t hal_ll_module_id, uint8_t channel ) {
+    if ( ( HAL_LL_TIM_8_BIT_MODULE_0 == hal_ll_module_id ) || ( HAL_LL_TIM_8_BIT_MODULE_2 == hal_ll_module_id ) ) {
+        switch ( channel ) {
+            case ( HAL_LL_TIM_CH_A ):
+                hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_hw_init_pwm_mode = &ptr_function_timer_0_and_timer_2_hw_init_pwm_mode_ch_a;
+                hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_set_duty = &ptr_function_timer_0_and_timer_2_set_duty_ch_a;
+                break;
+            case ( HAL_LL_TIM_CH_B ):
+                hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_hw_init_pwm_mode = &ptr_function_timer_0_and_timer_2_hw_init_pwm_mode_ch_b;
+                hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_set_duty = &ptr_function_timer_0_and_timer_2_set_duty_ch_b;
+                break;
+        }
+
+        if ( HAL_LL_TIM_8_BIT_MODULE_0 == hal_ll_module_id ) {
+            hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_set_prescaler = &ptr_function_timer_0_set_prescaler;
+        } else {
+            hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_set_prescaler = &ptr_function_timer_2_set_prescaler;
+        }
+    } else {
+        switch ( channel ) {
+            case ( HAL_LL_TIM_CH_A ):
+                hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_hw_init_pwm_mode = &ptr_function_timer_1_and_timer_3_hw_init_pwm_mode_ch_a;
+                hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_set_duty = &ptr_function_timers_1_3_4_5_set_duty_ch_a;
+                break;
+            case ( HAL_LL_TIM_CH_B ):
+                hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_hw_init_pwm_mode = &ptr_function_timer_1_and_timer_3_hw_init_pwm_mode_ch_b;
+                hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_set_duty = &ptr_function_timers_1_3_4_5_set_duty_ch_b;
+                break;
+        }
+        hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_set_prescaler = &ptr_function_timer_1_and_timer_3_set_prescaler;
+    }
+
+    switch ( channel ) {
+        case ( HAL_LL_TIM_CH_A ):
+            hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_signal_start = &ptr_function_timer_start_ch_a;
+            hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_signal_stop = &ptr_function_timer_stop_ch_a;
+            break;
+        case ( HAL_LL_TIM_CH_B ):
+            hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_signal_start = &ptr_function_timer_start_ch_b;
+            hal_ll_tim_hw_specifics_map[hal_ll_module_id]->mapped_functions.mapped_function_signal_stop = &ptr_function_timer_stop_ch_b;
+            break;
+    }
+}
+
+static inline void ptr_function_timer_start_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg ){
+   // PWM driver enabled, non-inverting submode.
+   clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_2 );
+   set_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_3 );
+}
+
+static inline void ptr_function_timer_start_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg ){
+    // PWM driver enabled, non-inverting submode.
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_0 );
+    set_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_1 );
+}
+
+static inline void ptr_function_timer_stop_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg ){
+    // PWM driver disconnected.
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_2 );
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_3 );
+
+    // Timer/Counter stopped (no clock source).
+    clear_reg_bits( hal_ll_hw_reg->pwm_tccrxb_reg_addr, HAL_LL_TIM_TIMER_STOPPED );
+}
+
+static inline void ptr_function_timer_stop_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg ){
+    // PWM driver disconnected.
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_0 );
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_1 );
+
+    // Timer/Counter stopped (no clock source).
+    clear_reg_bits( hal_ll_hw_reg->pwm_tccrxb_reg_addr, HAL_LL_TIM_TIMER_STOPPED );
+}
+
+static inline void ptr_function_timer_0_and_timer_2_set_duty_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg, float user_defined_duty ) {
+    if ( user_defined_duty >= HAL_LL_TIM_DUTY_RATIO_MAX ) {
+        write_reg( hal_ll_hw_reg->pwm_ocrxal_reg_addr, HAL_LL_TIM_8_BIT_MASK );
+    } else if ( user_defined_duty <= HAL_LL_TIM_DUTY_RATIO_MIN ) {
+        clear_reg( hal_ll_hw_reg->pwm_ocrxal_reg_addr );
+    } else {
+        write_reg( hal_ll_hw_reg->pwm_ocrxal_reg_addr, (uint8_t)( user_defined_duty * HAL_LL_TIM_8_BIT_RESOLUTION ) );
+    }
+}
+
+static inline void ptr_function_timer_0_and_timer_2_set_duty_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg, float user_defined_duty ) {
+    if ( user_defined_duty >= HAL_LL_TIM_DUTY_RATIO_MAX ) {
+        write_reg( hal_ll_hw_reg->pwm_ocrxbl_reg_addr, HAL_LL_TIM_8_BIT_MASK );
+    } else if ( user_defined_duty <= HAL_LL_TIM_DUTY_RATIO_MIN ) {
+        clear_reg( hal_ll_hw_reg->pwm_ocrxbl_reg_addr );
+    } else {
+        write_reg( hal_ll_hw_reg->pwm_ocrxbl_reg_addr, (uint8_t)( user_defined_duty * HAL_LL_TIM_8_BIT_RESOLUTION ) );
+    }
+}
+
+static inline void ptr_function_timers_1_3_4_5_set_duty_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg, float user_defined_duty ) {
+    if ( user_defined_duty >= HAL_LL_TIM_DUTY_RATIO_MAX ) {
+        _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, true );
+        write_reg( hal_ll_hw_reg->pwm_ocrxah_reg_addr, HAL_LL_TIM_10_BIT_PWM_RESOLUTION_MASK );
+        write_reg( hal_ll_hw_reg->pwm_ocrxal_reg_addr, HAL_LL_TIM_8_BIT_MASK );
+    } else if ( user_defined_duty <= HAL_LL_TIM_DUTY_RATIO_MIN ) {
+        _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, false );
+        clear_reg( hal_ll_hw_reg->pwm_ocrxah_reg_addr );
+        clear_reg( hal_ll_hw_reg->pwm_ocrxal_reg_addr );
+    } else {
+        _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, true );
+        clear_reg( hal_ll_hw_reg->pwm_tcntxh_reg_addr );
+        clear_reg( hal_ll_hw_reg->pwm_tcntxl_reg_addr );
+        uint16_t test_var = user_defined_duty * HAL_LL_TIM_10_BIT_RESOLUTION;
+
+        write_reg( hal_ll_hw_reg->pwm_ocrxah_reg_addr, test_var >> HAL_LL_TIM_8_BIT_SHIFT );
+        write_reg( hal_ll_hw_reg->pwm_ocrxal_reg_addr, (uint8_t)test_var );
+    }
+}
+
+static inline void ptr_function_timers_1_3_4_5_set_duty_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg, float user_defined_duty ) {
+    if ( user_defined_duty >= HAL_LL_TIM_DUTY_RATIO_MAX ) {
+        _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, true );
+        write_reg( hal_ll_hw_reg->pwm_ocrxbh_reg_addr, HAL_LL_TIM_10_BIT_PWM_RESOLUTION_MASK );
+        write_reg( hal_ll_hw_reg->pwm_ocrxbl_reg_addr, HAL_LL_TIM_8_BIT_MASK );
+    } else if ( user_defined_duty <= HAL_LL_TIM_DUTY_RATIO_MIN ) {
+        _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, false );
+        clear_reg( hal_ll_hw_reg->pwm_ocrxbh_reg_addr );
+        clear_reg( hal_ll_hw_reg->pwm_ocrxbl_reg_addr );
+    } else {
+        _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, true );
+        clear_reg( hal_ll_hw_reg->pwm_tcntxh_reg_addr );
+        clear_reg( hal_ll_hw_reg->pwm_tcntxl_reg_addr );
+        uint16_t test_var = user_defined_duty * HAL_LL_TIM_10_BIT_RESOLUTION;
+
+        write_reg( hal_ll_hw_reg->pwm_ocrxbh_reg_addr, test_var >> HAL_LL_TIM_8_BIT_SHIFT );
+        write_reg( hal_ll_hw_reg->pwm_ocrxbl_reg_addr, (uint8_t)test_var );
+    }
+}
+
+static inline void ptr_function_timer_0_set_prescaler( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    uint8_t local_loop_counter = 0;
+    uint8_t prescaler_value = 0;
+
+    // Prescaler divider array for Timer/Counter modules 0 and 1.
+    const volatile uint8_t prescaler_divider_array_0[HAL_LL_TIM_PRESCALER_REG_VALUE_5] = { 1, 8, 64, 256, 1024 };
+
+    // By default, set minimal PWM frequency available.
+    prescaler_value = HAL_LL_TIM_PRESCALER_REG_VALUE_5;
+    // prescaler_value = HAL_LL_TIM_PRESCALER_REG_VALUE_1;
+    hal_ll_tim_hw_specifics_map_local->max_period = ( _fosc / ( ( prescaler_divider_array_0[sizeof(prescaler_divider_array_0) - 1] ) * HAL_LL_TIM_8_BIT_RESOLUTION_MASK ) );
+
+    // Check if better PWM frequency can be achieved.
+    for ( local_loop_counter = 0; local_loop_counter < sizeof(prescaler_divider_array_0); local_loop_counter++ ) {
+        if ( hal_ll_tim_hw_specifics_map_local->freq_hz >= ( _fosc / ( prescaler_divider_array_0[local_loop_counter] * HAL_LL_TIM_8_BIT_RESOLUTION_MASK ) ) ) {
+            prescaler_value = local_loop_counter + 1;
+            hal_ll_tim_hw_specifics_map_local->max_period = (_fosc / ( prescaler_divider_array_0[local_loop_counter] * HAL_LL_TIM_8_BIT_RESOLUTION_MASK ) );
+            break;
+        }
+    }
+
+    // Finally, configure register according to computed prescaler bits.
+    set_reg_bits( hal_ll_hw_reg->pwm_tccrxb_reg_addr, prescaler_value );
+}
+
+static inline void ptr_function_timer_2_set_prescaler( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    uint8_t local_loop_counter = 0;
+    uint8_t prescaler_value = 0;
+
+    // Prescaler divider array for Timer/Counter module 2.
+    const volatile uint8_t prescaler_divider_array_1[HAL_LL_TIM_PRESCALER_REG_VALUE_7] = { 1, 8, 32, 64, 128, 256, 1024 };
+
+    // By default, set minimal PWM frequency available.
+    prescaler_value = HAL_LL_TIM_PRESCALER_REG_VALUE_7;
+    hal_ll_tim_hw_specifics_map_local->max_period = ( _fosc / ( prescaler_divider_array_1[sizeof(prescaler_divider_array_1) - 1] * HAL_LL_TIM_8_BIT_RESOLUTION_MASK ) );
+
+    // Check if better PWM frequency can be achieved.
+    for ( local_loop_counter = 0; local_loop_counter < sizeof(prescaler_divider_array_1); local_loop_counter++ ) {
+        if ( hal_ll_tim_hw_specifics_map_local->freq_hz >= ( _fosc / ( prescaler_divider_array_1[local_loop_counter] * HAL_LL_TIM_8_BIT_RESOLUTION_MASK ) ) ) {
+            prescaler_value = local_loop_counter + 1;
+            hal_ll_tim_hw_specifics_map_local->max_period = (_fosc / ( prescaler_divider_array_1[local_loop_counter] * HAL_LL_TIM_8_BIT_RESOLUTION_MASK ) );
+            break;
+        }
+    }
+
+    // Finally, configure register according to computed prescaler bits.
+    set_reg_bits( hal_ll_hw_reg->pwm_tccrxb_reg_addr, prescaler_value );
+}
+
+static inline void ptr_function_timer_1_and_timer_3_set_prescaler( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    uint8_t local_loop_counter = 0;
+    uint8_t prescaler_value = 0;
+
+    // Prescaler divider array for Timer/Counter modules 0 and 1.
+    const volatile uint8_t prescaler_divider_array_0[HAL_LL_TIM_PRESCALER_REG_VALUE_5] = { 1, 8, 64, 256, 1024 };
+
+    // By default, set max PWM frequency available.
+    prescaler_value = HAL_LL_TIM_PRESCALER_REG_VALUE_1;
+    hal_ll_tim_hw_specifics_map_local->max_period = ( _fosc / ( prescaler_divider_array_0[sizeof(prescaler_divider_array_0) - 1] * HAL_LL_TIM_10_BIT_RESOLUTION ) );
+
+    // Check if better PWM frequency can be achieved.
+    for ( local_loop_counter = 0; local_loop_counter < sizeof(prescaler_divider_array_0); local_loop_counter++ ) {
+        if ( hal_ll_tim_hw_specifics_map_local->freq_hz >= _fosc / ( ( prescaler_divider_array_0[local_loop_counter] ) * HAL_LL_TIM_10_BIT_RESOLUTION ) ) {
+            prescaler_value = local_loop_counter + 1;
+            hal_ll_tim_hw_specifics_map_local->max_period = _fosc / ( ( prescaler_divider_array_0[local_loop_counter] ) * HAL_LL_TIM_10_BIT_RESOLUTION );
+            break;
+        }
+    }
+
+    // Finally, configure register according to computed prescaler bits.
+    set_reg_bits( hal_ll_hw_reg->pwm_tccrxb_reg_addr, prescaler_value );
+}
+
+static inline void ptr_function_timer_0_and_timer_2_hw_init_pwm_mode_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxb_reg_addr, HAL_LL_TIM_FORCE_OUTPUT_COMPARE_MATCH_BIT_CH_A );
+
+    // Set Waveform Generation Mode to Fast PWM.
+    set_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_FAST_PWM_8_BIT_RESOLUTION_BIT_0 );
+    set_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_FAST_PWM_8_BIT_RESOLUTION_BIT_1 );
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxb_reg_addr, HAL_LL_TIM_FAST_PWM_8_BIT_RESOLUTION_BIT_2 );
+
+    // PWM driver disconnected.
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_3 );
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_2 );
+
+    // Timer/Counter stopped (no clock source).
+    clear_reg_bits( hal_ll_hw_reg->pwm_tccrxb_reg_addr, HAL_LL_TIM_TIMER_STOPPED );
+}
+
+static inline void ptr_function_timer_0_and_timer_2_hw_init_pwm_mode_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxb_reg_addr, HAL_LL_TIM_FORCE_OUTPUT_COMPARE_MATCH_BIT_CH_B );
+
+    // Set Waveform Generation Mode to Fast PWM.
+    set_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_FAST_PWM_8_BIT_RESOLUTION_BIT_0 );
+    set_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_FAST_PWM_8_BIT_RESOLUTION_BIT_1 );
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxb_reg_addr, HAL_LL_TIM_FAST_PWM_8_BIT_RESOLUTION_BIT_2 );
+
+    // PWM driver disconnected.
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_1 );
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_0 );
+
+}
+
+static inline void ptr_function_timer_1_and_timer_3_hw_init_pwm_mode_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    // Set Waveform Generation Mode to Fast PWM, 10-bit, for controlling the duty.
+    set_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_FAST_PWM_8_BIT_RESOLUTION_BIT_0 );
+    set_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_FAST_PWM_8_BIT_RESOLUTION_BIT_1 );
+
+    // PWM driver disconnected.
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_3 );
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_2 );
+
+    // Timer/Counter stopped (no clock source).
+    clear_reg_bits( hal_ll_hw_reg->pwm_tccrxb_reg_addr, HAL_LL_TIM_TIMER_STOPPED );
+}
+
+static inline void ptr_function_timer_1_and_timer_3_hw_init_pwm_mode_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    // Set Waveform Generation Mode to Fast PWM, 10-bit, for controlling the duty.
+    set_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_FAST_PWM_8_BIT_RESOLUTION_BIT_0 );
+    set_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_FAST_PWM_8_BIT_RESOLUTION_BIT_1 );
+
+    // PWM driver disconnected.
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_1 );
+    clear_reg_bit( hal_ll_hw_reg->pwm_tccrxa_reg_addr, HAL_LL_TIM_PWM_NON_INVERTING_MODE_BIT_0 );
+
+    // Timer/Counter stopped (no clock source).
+    clear_reg_bits( hal_ll_hw_reg->pwm_tccrxb_reg_addr, HAL_LL_TIM_TIMER_STOPPED );
+}
+
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/src/tim/implementation_3/hal_ll_tim.c b/targets/avr_8bit/mikroe/avr/src/tim/implementation_3/hal_ll_tim.c
new file mode 100644
index 000000000..20ade2e7a
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/tim/implementation_3/hal_ll_tim.c
@@ -0,0 +1,903 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_tim.c
+ * @brief TIMER HAL LOW LEVEL layer implementation.
+ */
+
+#include "hal_ll_tim.h"
+#include "hal_ll_gpio.h"
+#include "hal_ll_tim_pin_map.h"
+
+/*!< @brief Local handle list */
+static volatile hal_ll_tim_handle_register_t hal_ll_module_state[ TIM_MODULE_COUNT ] = { (handle_t *)NULL, (handle_t *)NULL, false };
+
+// ------------------------------------------------------------- PRIVATE MACROS
+/*!< @brief Helper macro for getting module specific control register structure */
+#define hal_ll_tim_get_base_struct(_handle) ((hal_ll_tim_base_handle_t *)_handle)
+
+/*!< @brief Helper macro for getting hal_ll_module_state address */
+#define hal_ll_tim_get_module_state_address ((hal_ll_tim_handle_register_t *)*handle)
+
+/*!< @brief Helper macro for getting module specific control register structure base address // first register address */
+#define hal_ll_tim_get_handle ( hal_ll_tim_handle_register_t * )hal_ll_tim_get_module_state_address->hal_ll_tim_handle
+
+/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */
+#define hal_ll_tim_get_base_from_hal_handle ((hal_ll_tim_hw_specifics_map_t *)((hal_ll_tim_handle_register_t *)\
+                                            (((hal_ll_tim_handle_register_t *)(handle))->hal_ll_tim_handle))->hal_ll_tim_handle)->base
+
+/*!< @brief Helper macro for TIM module sync time. */
+#define hal_ll_tim_wait_for_sync(_hal_sync_val) while( _hal_sync_val-- ){asm nop;}
+
+/*!< @brief Helper macros for setting or clearing th Wave Generator's output compare value. */
+#define HAL_LL_TIM_CMPA_BIT (0)
+#define HAL_LL_TIM_CMPB_BIT (1)
+#define HAL_LL_TIM_CMPC_BIT (2)
+#define HAL_LL_TIM_CMPD_BIT (3)
+
+/*!< @brief Helper macro for selecting PWM clock. */
+#define HAL_LL_TIM_NO_PRESCALER (0)
+
+/*!< @brief Helper macro for configuring Waveform Generator for "Single-Slope PWM". */
+#define HAL_LL_TIM_SET_SINGLE_SLOPE_PWM (0x3)
+
+/*!< @brief Helper macro for clearing Waveform Generator. */
+#define HAL_LL_TIM_RESET_WAFEFORM_GENERATOR (0x7)
+
+/*!< @brief Helper macro for enabling PWM channels. */
+#define HAL_LL_TIM_OUTPUT_COMPARE_CH_A (4)
+#define HAL_LL_TIM_OUTPUT_COMPARE_CH_A_ATXMEGA_E5_SERIES (0)
+#define HAL_LL_TIM_OUTPUT_COMPARE_CH_B (5)
+#define HAL_LL_TIM_OUTPUT_COMPARE_CH_B_ATXMEGA_E5_SERIES (2)
+#define HAL_LL_TIM_OUTPUT_COMPARE_CH_C (6)
+#define HAL_LL_TIM_OUTPUT_COMPARE_CH_C_ATXMEGA_E5_SERIES (4)
+#define HAL_LL_TIM_OUTPUT_COMPARE_CH_D (7)
+#define HAL_LL_TIM_OUTPUT_COMPARE_CH_D_ATXMEGA_E5_SERIES (6)
+
+/*!< @brief Helper macro for configuring Timer/Counter (PWM) operation mode. */
+#define HAL_LL_TIM_BYTE_MODE_NORMAL (0)
+
+/*!< @brief Helper macro for retrieving MCU clock in Hz. */
+#define _fosc (Get_Fosc_kHz()*1000)
+
+// -------------------------------------------------------------- PRIVATE TYPES
+typedef struct{
+    uint16_t hal_ll_pwm_ctrla_reg_address;
+    uint16_t hal_ll_pwm_ctrlb_reg_address;
+    uint16_t hal_ll_pwm_ctrlc_reg_address;
+    uint16_t hal_ll_pwm_ctrld_reg_address;
+    uint16_t hal_ll_pwm_ctrle_reg_address;
+    uint16_t hal_ll_pwm_ccabuf_reg_address;
+    uint16_t hal_ll_pwm_ccbbuf_reg_address;
+    uint16_t hal_ll_pwm_cccbuf_reg_address;
+    uint16_t hal_ll_pwm_ccdbuf_reg_address;
+    uint16_t hal_ll_pwm_perl_reg_address;
+    uint16_t hal_ll_pwm_perh_reg_address;
+} hal_ll_tim_base_handle_t;
+
+/*!< @brief TIM hw specific pointers to functions. */
+typedef struct {
+    void ( *mapped_function_signal_start )( hal_ll_tim_base_handle_t * );
+    void ( *mapped_function_signal_stop )( hal_ll_tim_base_handle_t * );
+    void ( *mapped_function_hw_init_pwm_mode )( hal_ll_tim_base_handle_t * );
+    void ( *mapped_function_set_duty )( hal_ll_tim_base_handle_t *, uint16_t );
+} hal_ll_tim_functions;
+
+/*!< @brief TIM hw specific structure */
+typedef struct {
+    hal_ll_tim_base_handle_t *base;
+    hal_ll_pin_name_t pin;
+    uint32_t max_period;
+    uint32_t freq_hz;
+    uint8_t module_index;
+    uint8_t channel;
+    hal_ll_tim_functions mapped_functions;
+} hal_ll_tim_hw_specifics_map_t;
+
+/*!< @brief TIM hw specific error values */
+typedef enum {
+    HAL_LL_TIM_SUCCESS = 0,
+    HAL_LL_TIM_MODULE_ERROR,
+    HAL_LL_TIM_WRONG_PIN,
+
+    HAL_LL_TIM_ERROR = (-1)
+} hal_ll_tim_err_t;
+
+// ------------------------------------------------------------------ CONSTANTS
+/*!< @brief PWM array */
+static hal_ll_tim_base_handle_t tim_ll_reg_offsets[ TIM_MODULE_COUNT + 1 ] = {
+    #ifdef TIM_MODULE_0
+    { HAL_LL_TIM0_CTRLA_REG_ADDRESS, HAL_LL_TIM0_CTRLB_REG_ADDRESS, HAL_LL_TIM0_CTRLC_REG_ADDRESS,
+      HAL_LL_TIM0_CTRLD_REG_ADDRESS, HAL_LL_TIM0_CTRLE_REG_ADDRESS, HAL_LL_TIM0_CCABUF_REG_ADDRESS,
+      HAL_LL_TIM0_CCBBUF_REG_ADDRESS, HAL_LL_TIM0_CCCBUF_REG_ADDRESS, HAL_LL_TIM0_CCDBUF_REG_ADDRESS,
+      HAL_LL_TIM0_PERL_REG_ADDRESS, HAL_LL_TIM0_PERH_REG_ADDRESS },
+    #endif
+
+    #ifdef TIM_MODULE_1
+    { HAL_LL_TIM1_CTRLA_REG_ADDRESS, HAL_LL_TIM1_CTRLB_REG_ADDRESS, HAL_LL_TIM1_CTRLC_REG_ADDRESS,
+      HAL_LL_TIM1_CTRLD_REG_ADDRESS, HAL_LL_TIM1_CTRLE_REG_ADDRESS, HAL_LL_TIM1_CCABUF_REG_ADDRESS,
+      HAL_LL_TIM1_CCBBUF_REG_ADDRESS, HAL_LL_TIM1_CCCBUF_REG_ADDRESS, HAL_LL_TIM1_CCDBUF_REG_ADDRESS,
+      HAL_LL_TIM1_PERL_REG_ADDRESS, HAL_LL_TIM1_PERH_REG_ADDRESS },
+    #endif
+
+    #ifdef TIM_MODULE_2
+    { HAL_LL_TIM2_CTRLA_REG_ADDRESS, HAL_LL_TIM2_CTRLB_REG_ADDRESS, HAL_LL_TIM2_CTRLC_REG_ADDRESS,
+      HAL_LL_TIM2_CTRLD_REG_ADDRESS, HAL_LL_TIM2_CTRLE_REG_ADDRESS, HAL_LL_TIM2_CCABUF_REG_ADDRESS,
+      HAL_LL_TIM2_CCBBUF_REG_ADDRESS, HAL_LL_TIM2_CCCBUF_REG_ADDRESS, HAL_LL_TIM2_CCDBUF_REG_ADDRESS,
+      HAL_LL_TIM2_PERL_REG_ADDRESS, HAL_LL_TIM2_PERH_REG_ADDRESS },
+    #endif
+
+    #ifdef TIM_MODULE_3
+    { HAL_LL_TIM3_CTRLA_REG_ADDRESS, HAL_LL_TIM3_CTRLB_REG_ADDRESS, HAL_LL_TIM3_CTRLC_REG_ADDRESS,
+      HAL_LL_TIM3_CTRLD_REG_ADDRESS, HAL_LL_TIM3_CTRLE_REG_ADDRESS, HAL_LL_TIM3_CCABUF_REG_ADDRESS,
+      HAL_LL_TIM3_CCBBUF_REG_ADDRESS, HAL_LL_TIM3_CCCBUF_REG_ADDRESS, HAL_LL_TIM3_CCDBUF_REG_ADDRESS,
+      HAL_LL_TIM3_PERL_REG_ADDRESS, HAL_LL_TIM3_PERH_REG_ADDRESS },
+    #endif
+
+    #ifdef TIM_MODULE_4
+    { HAL_LL_TIM4_CTRLA_REG_ADDRESS, HAL_LL_TIM4_CTRLB_REG_ADDRESS, HAL_LL_TIM4_CTRLC_REG_ADDRESS,
+      HAL_LL_TIM4_CTRLD_REG_ADDRESS, HAL_LL_TIM4_CTRLE_REG_ADDRESS, HAL_LL_TIM4_CCABUF_REG_ADDRESS,
+      HAL_LL_TIM4_CCBBUF_REG_ADDRESS, HAL_LL_TIM4_CCCBUF_REG_ADDRESS, HAL_LL_TIM4_CCDBUF_REG_ADDRESS,
+      HAL_LL_TIM4_PERL_REG_ADDRESS, HAL_LL_TIM4_PERH_REG_ADDRESS },
+    #endif
+
+    #ifdef TIM_MODULE_5
+    { HAL_LL_TIM5_CTRLA_REG_ADDRESS, HAL_LL_TIM5_CTRLB_REG_ADDRESS, HAL_LL_TIM5_CTRLC_REG_ADDRESS,
+      HAL_LL_TIM5_CTRLD_REG_ADDRESS, HAL_LL_TIM5_CTRLE_REG_ADDRESS, HAL_LL_TIM5_CCABUF_REG_ADDRESS,
+      HAL_LL_TIM5_CCBBUF_REG_ADDRESS, HAL_LL_TIM5_CCCBUF_REG_ADDRESS, HAL_LL_TIM5_CCDBUF_REG_ADDRESS,
+      HAL_LL_TIM5_PERL_REG_ADDRESS, HAL_LL_TIM5_PERH_REG_ADDRESS },
+    #endif
+
+    #ifdef TIM_MODULE_6
+    { HAL_LL_TIM6_CTRLA_REG_ADDRESS, HAL_LL_TIM6_CTRLB_REG_ADDRESS, HAL_LL_TIM6_CTRLC_REG_ADDRESS,
+      HAL_LL_TIM6_CTRLD_REG_ADDRESS, HAL_LL_TIM6_CTRLE_REG_ADDRESS, HAL_LL_TIM6_CCABUF_REG_ADDRESS,
+      HAL_LL_TIM6_CCBBUF_REG_ADDRESS, HAL_LL_TIM6_CCCBUF_REG_ADDRESS, HAL_LL_TIM6_CCDBUF_REG_ADDRESS,
+      HAL_LL_TIM6_PERL_REG_ADDRESS, HAL_LL_TIM6_PERH_REG_ADDRESS },
+    #endif
+
+    #ifdef TIM_MODULE_7
+    { HAL_LL_TIM7_CTRLA_REG_ADDRESS, HAL_LL_TIM7_CTRLB_REG_ADDRESS, HAL_LL_TIM7_CTRLC_REG_ADDRESS,
+      HAL_LL_TIM7_CTRLD_REG_ADDRESS, HAL_LL_TIM7_CTRLE_REG_ADDRESS, HAL_LL_TIM7_CCABUF_REG_ADDRESS,
+      HAL_LL_TIM7_CCBBUF_REG_ADDRESS, HAL_LL_TIM7_CCCBUF_REG_ADDRESS, HAL_LL_TIM7_CCDBUF_REG_ADDRESS,
+      HAL_LL_TIM7_PERL_REG_ADDRESS, HAL_LL_TIM7_PERH_REG_ADDRESS },
+    #endif
+
+    { HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC,
+      HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC }
+};
+
+// ------------------------------------------------------------------ VARIABLES
+/*!< @brief TIM specific info */
+static hal_ll_tim_hw_specifics_map_t hal_ll_tim_hw_specifics_map[ TIM_MODULE_COUNT + 1 ] = {
+    #ifdef TIM_MODULE_0
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_0) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+
+    #ifdef TIM_MODULE_1
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_1) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+
+    #ifdef TIM_MODULE_2
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_2) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+
+    #ifdef TIM_MODULE_3
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_3) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+
+    #ifdef TIM_MODULE_4
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_4) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+
+    #ifdef TIM_MODULE_5
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_5) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_5), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+
+    #ifdef TIM_MODULE_6
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_6) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_6), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+
+    #ifdef TIM_MODULE_7
+    { &tim_ll_reg_offsets[ hal_ll_tim_module_num(TIM_MODULE_7) ], HAL_LL_PIN_NC, 0, 0, hal_ll_tim_module_num(TIM_MODULE_7), HAL_LL_TIM_CH_DEFAULT, NULL },
+    #endif
+
+    { &tim_ll_reg_offsets[ TIM_MODULE_COUNT ], HAL_LL_PIN_NC, 0, 0, HAL_LL_MODULE_ERROR, HAL_LL_TIM_CH_DEFAULT, NULL }
+};
+
+/*!< @brief Global handle variables used in functions */
+static volatile hal_ll_tim_handle_register_t  *low_level_handle;
+static volatile hal_ll_tim_hw_specifics_map_t *hal_ll_tim_hw_specifics_map_local;
+
+// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS
+/**
+  * @brief Get local hardware specific map.
+  *
+  * Checks handle value and returns address of adequate
+  * hal_ll_tim_hw_specifics_map array index.
+  *
+  * @param[in] handle - Object specific context handler.
+  * @return hal_ll_tim_hw_specifics_map_t Map address.
+  *
+  * Returns pre-defined map index address based on handle value,
+  * if handle is adequate.
+  */
+static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle );
+
+/**
+  * @brief Initialize TIM module on hardware level.
+  *
+  * Initializes TIM module on hardware level, based on beforehand
+  * set configuration and module handler.
+  *
+  * @param[in] *map - Object specific context handler.
+  * @return none
+  *
+  */
+static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map );
+
+/**
+  * @brief  Full TIM module initialization procedure.
+  *
+  * Initializes TIM module on hardware level, based on beforehand
+  * set configuration and module handler. Sets adequate pin alternate functions.
+  * Initializes module clock.
+  *
+  * @param[in] *map - Object specific context handler.
+  * @return none
+  *
+  */
+static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map );
+
+/**
+ * @brief Maps new-found module specific values.
+ *
+ * Maps pin name and channel function values for TIM pin.
+ *
+ * @param[in] module_index TIM HW module index -- 0,1,2...
+ * @param[in] index_list  Array with TIM pin map index values.
+ *
+ * @return  None
+ */
+static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index );
+
+/**
+  * @brief Check if pin is adequate.
+  *
+  * Checks tim pin the user has passed with pre-defined
+  * pin in tim map.
+  *
+  * @param[in] pin - TIM pre-defined pin name.
+  * @param[in] *index_list - Array with TIM pin map index values.
+  * @param[in] *handle_map - Local TIM handle list.
+  * @return hal_ll_pin_name_t - Module index based on pin.
+  *
+  * Returns pre-defined module index from pin maps, if pin
+  * is adequate.
+  */
+static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map );
+
+/**
+ * @brief Set GPIO state.
+ *
+ * Sets adequate TRISx register
+ * values for adequate functionality.
+ *
+ * @param[in] *map - Object specific context handler.
+ * @param[in] hal_ll_state - init or deinit
+ *
+ * @return  none.
+ *
+ * @note AVR specific.
+ */
+static void _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state );
+
+/**
+  * @brief Map adequate function addresses.
+  *
+  * Function maps adequate function addresses.
+  *
+  * @param[in] hal_ll_module_id - Module index.
+  *
+  * @return none
+  *
+  */
+static inline void map_pointer_functions( uint8_t hal_ll_module_id, uint8_t channel );
+
+/**
+  * @brief Timer/Counter module start function (channel A).
+  *
+  * Function starts generating PWM signal on Timer/Counter PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_counter_start_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter module start function (channel B).
+  *
+  * Function starts generating PWM signal on Timer/Counter PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_counter_start_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter module start function (channel C).
+  *
+  * Function starts generating PWM signal on Timer/Counter PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_counter_start_ch_c( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter module start function (channel D).
+  *
+  * Function starts generating PWM signal on Timer/Counter PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_counter_start_ch_d( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter module stop function (channel A).
+  *
+  * Function stops generating PWM signal on Timer/Counter PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_counter_stop_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter module stop function (channel B).
+  *
+  * Function stops generating PWM signal on Timer/Counter PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_counter_stop_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter module stop function (channel C).
+  *
+  * Function stops generating PWM signal on Timer/Counter PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_counter_stop_ch_c( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Timer/Counter module stop function (channel D).
+  *
+  * Function stops generating PWM signal on Timer/Counter PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_counter_stop_ch_d( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Clears any electronic driver output leftovers (channel A).
+  *
+  * Clears any output leftovers from the Waveform Generator for channel A.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_counter_hw_init_pwm_mode_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Clears any electronic driver output leftovers (channel B).
+  *
+  * Clears any output leftovers from the Waveform Generator for channel B.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_counter_hw_init_pwm_mode_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Clears any electronic driver output leftovers (channel C).
+  *
+  * Clears any output leftovers from the Waveform Generator for channel C.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_counter_hw_init_pwm_mode_ch_c( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Clears any electronic driver output leftovers (channel D).
+  *
+  * Clears any output leftovers from the Waveform Generator for channel D.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_counter_hw_init_pwm_mode_ch_d( hal_ll_tim_base_handle_t *hal_ll_hw_reg );
+
+/**
+  * @brief Initialize Timer/Counter set duty function (channel A).
+  *
+  * Function configures duty cycle on Timer/Counter PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  * @param[in] duty_cycle_value - Calculated duty cycle.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_counter_set_duty_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg, uint16_t duty_cycle_value );
+
+/**
+  * @brief Initialize Timer/Counter set duty function (channel B).
+  *
+  * Function configures duty cycle on Timer/Counter PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  * @param[in] duty_cycle_value - Calculated duty cycle.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_counter_set_duty_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg, uint16_t duty_cycle_value );
+
+/**
+  * @brief Initialize Timer/Counter set duty function (channel C).
+  *
+  * Function configures duty cycle on Timer/Counter PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  * @param[in] duty_cycle_value - Calculated duty cycle.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_counter_set_duty_ch_c( hal_ll_tim_base_handle_t *hal_ll_hw_reg, uint16_t duty_cycle_value );
+
+/**
+  * @brief Initialize Timer/Counter set duty function (channel A).
+  *
+  * Function configures duty cycle on Timer/Counter PWM pin.
+  *
+  * @param[in] *hal_ll_hw_reg - Set of registers used for proper usage of Timer/Counter module.
+  * @param[in] duty_cycle_value - Calculated duty cycle.
+  *
+  * @return none
+  *
+  */
+static inline void ptr_function_timer_counter_set_duty_ch_d( hal_ll_tim_base_handle_t *hal_ll_hw_reg, uint16_t duty_cycle_value );
+
+// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS
+hal_ll_err_t hal_ll_tim_register_handle( hal_ll_pin_name_t pin, hal_ll_tim_handle_register_t *handle_map, uint8_t *hal_module_id ) {
+    uint8_t pin_check_result;
+    uint8_t index;
+
+    if (  HAL_LL_PIN_NC == ( pin_check_result = _hal_ll_tim_check_pin( pin, &index, handle_map ) ) ) {
+        return HAL_LL_TIM_WRONG_PIN;
+    }
+
+    if ( ( hal_ll_tim_hw_specifics_map[ pin_check_result ].pin != pin ) ) {
+        _hal_ll_tim_map_pin( pin_check_result, index );
+
+        handle_map[ pin_check_result ]->init_ll_state = false;
+
+        hal_ll_module_state[ pin_check_result ].init_ll_state = false;
+    }
+
+    *hal_module_id = pin_check_result;
+
+    hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = ( handle_t * )&hal_ll_tim_hw_specifics_map[ pin_check_result ].base;
+
+    handle_map[ pin_check_result ]->hal_ll_tim_handle = ( handle_t *)&hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle;
+
+    return HAL_LL_TIM_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_module_configure_tim( handle_t *handle ) {
+    uint8_t pin_check_result;
+    uint8_t index;
+
+    low_level_handle = hal_ll_tim_get_handle;
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    if ( HAL_LL_PIN_NC == ( pin_check_result = _hal_ll_tim_check_pin( hal_ll_tim_hw_specifics_map_local->pin, &index, (void *)0 ) ) ) {
+        return HAL_LL_TIM_WRONG_PIN;
+    }
+
+    _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local );
+
+    hal_ll_module_state[ pin_check_result ].hal_ll_tim_handle = (handle_t *)&hal_ll_tim_hw_specifics_map[ pin_check_result ].base;
+
+    return HAL_LL_TIM_SUCCESS;
+}
+
+uint32_t hal_ll_tim_set_freq( handle_t *handle, uint32_t freq_hz ) {
+    uint16_t local_freq = 0;
+    low_level_handle = hal_ll_tim_get_handle;
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base );
+
+    low_level_handle->init_ll_state = false;
+
+    hal_ll_tim_hw_specifics_map_local->freq_hz = freq_hz;
+
+    _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local );
+
+    low_level_handle->init_ll_state = true;
+
+    // Calculate PWM frequency.
+    local_freq = ( ( _fosc / hal_ll_tim_hw_specifics_map_local->freq_hz ) - 1 );
+
+    // Populate appropriate registers.
+    write_reg( hal_ll_hw_reg->hal_ll_pwm_perl_reg_address, ( (uint8_t)local_freq ) );
+    write_reg( hal_ll_hw_reg->hal_ll_pwm_perh_reg_address, ( local_freq >> 8 ) );
+
+    // Memorize information about the max period available (PWM duty cycle is dependant of this information).
+    return ( hal_ll_tim_hw_specifics_map_local->max_period = local_freq ) ;
+}
+
+hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) {
+    uint16_t local_duty_cycle_value = 0;
+    low_level_handle = hal_ll_tim_get_handle;
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base );
+
+    if ( low_level_handle->init_ll_state == false ) {
+        _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_local );
+        low_level_handle->init_ll_state = true;
+    }
+
+    // Calculate duty cycle value in accordance to max period available.
+    local_duty_cycle_value = ( duty_ratio * hal_ll_tim_hw_specifics_map_local->max_period );
+
+    // Insert duty cycle value into appropriate register (via function pointers).
+    ( hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_set_duty )
+    ( hal_ll_tim_hw_specifics_map_local->base, local_duty_cycle_value );
+
+    return HAL_LL_TIM_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_tim_start( handle_t *handle ) {
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base );
+
+    // Configure Waveform Generator for "Single-Slope PWM".
+    set_reg_bits( hal_ll_hw_reg->hal_ll_pwm_ctrlb_reg_address, HAL_LL_TIM_SET_SINGLE_SLOPE_PWM );
+
+    // Enable Compare mode for appropriate PWM driver channel (via function pointers).
+    ( hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_signal_start )
+    ( hal_ll_tim_hw_specifics_map_local->base );
+
+    return HAL_LL_TIM_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) {
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( hal_ll_tim_hw_specifics_map_local->base );
+
+    // Detach PWM driver circuit from PWM pin (via function pointers).
+    ( hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_signal_stop )
+    ( hal_ll_tim_hw_specifics_map_local->base );
+
+    // Reset Waveform Generator.
+    clear_reg_bits( hal_ll_hw_reg->hal_ll_pwm_ctrlb_reg_address, HAL_LL_TIM_RESET_WAFEFORM_GENERATOR );
+
+    // Timer/Counter in OFF state.
+    clear_reg( hal_ll_hw_reg->hal_ll_pwm_ctrla_reg_address );
+
+    return HAL_LL_TIM_SUCCESS;
+}
+
+void hal_ll_tim_close( handle_t *handle ) {
+    low_level_handle = hal_ll_tim_get_handle;
+    hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_tim_get_module_state_address );
+
+    if( low_level_handle->hal_ll_tim_handle != NULL ) {
+
+        low_level_handle->hal_ll_tim_handle = NULL;
+        low_level_handle->hal_drv_tim_handle = NULL;
+        low_level_handle->init_ll_state = false;
+
+        _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, false );
+
+        hal_ll_tim_hw_specifics_map_local->freq_hz = 0;
+        hal_ll_tim_hw_specifics_map_local->max_period = 0;
+        hal_ll_tim_hw_specifics_map_local->pin = HAL_LL_PIN_NC;
+        hal_ll_tim_hw_specifics_map_local->channel = HAL_LL_TIM_CH_DEFAULT;
+    }
+}
+
+// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS
+static hal_ll_pin_name_t _hal_ll_tim_check_pin( hal_ll_pin_name_t pin, uint8_t *index, hal_ll_tim_handle_register_t *handle_map ) {
+    uint8_t pin_num;
+    uint8_t index_counter = 0;
+    uint8_t hal_ll_module_id = 0;
+    static uint16_t map_size = ( sizeof( _tim_map ) / sizeof( hal_ll_tim_pin_map_t ) );
+
+    if ( HAL_LL_PIN_NC == pin ) {
+        return HAL_LL_PIN_NC;
+    }
+
+    // Check if the selected pin is valid.
+    for ( pin_num = 0; pin_num < map_size; pin_num++ ) {
+        if ( _tim_map[ pin_num ].pin == pin ) {
+            // Get module number
+            hal_ll_module_id = _tim_map[ pin_num ].module_index;
+            map_pointer_functions( hal_ll_module_id, _tim_map[ pin_num ].channel );
+            if ( NULL == handle_map[hal_ll_module_id].hal_drv_tim_handle ) {
+                *index = pin_num;
+                return hal_ll_module_id;
+            } else if ( TIM_MODULE_COUNT == ++index_counter ) {
+                return --index_counter;
+            }
+        }
+    }
+    // By default return last error msg.
+    if ( index_counter ) {
+        return hal_ll_module_id;
+    } else {
+        return HAL_LL_PIN_NC;
+    }
+}
+
+static hal_ll_tim_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) {
+    uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_tim_handle_register_t ) );
+    static uint8_t hal_ll_module_error = hal_ll_module_count;
+
+    while( hal_ll_module_count-- ) {
+        if ( hal_ll_tim_get_base_from_hal_handle == hal_ll_tim_hw_specifics_map [ hal_ll_module_count ].base ) {
+                return &hal_ll_tim_hw_specifics_map[ hal_ll_module_count ];
+            }
+        }
+
+    return &hal_ll_tim_hw_specifics_map[ hal_ll_module_error ];
+}
+
+static void _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_t *map, bool hal_ll_state ) {
+    hal_ll_gpio_pin_t pin;
+
+    if ( hal_ll_state ) {
+        hal_ll_gpio_configure_pin( &pin, map->pin, HAL_LL_GPIO_DIGITAL_OUTPUT );
+    } else {
+        hal_ll_gpio_configure_pin( &pin, map->pin, HAL_LL_GPIO_DIGITAL_INPUT );
+    }
+}
+
+static void _hal_ll_tim_map_pin( uint8_t module_index, uint8_t index ) {
+    // Memorize PWM pin.
+    hal_ll_tim_hw_specifics_map[ module_index ].pin = _tim_map[ index ].pin;
+
+    // Memorize PWM pin channel.
+    hal_ll_tim_hw_specifics_map[ module_index ].channel = _tim_map[ index ].channel;
+}
+
+static void _hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) {
+    /*!< @brief Static, because clock doesn't change during runtime. */
+    static uint32_t hal_ll_clock_value = Get_Fosc_kHz() * 2;
+
+    // Get hardware register list for user-defined PWM pin.
+    hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base );
+
+    // Set Clock source.
+    set_reg_bit( hal_ll_hw_reg->hal_ll_pwm_ctrla_reg_address, HAL_LL_TIM_NO_PRESCALER );
+
+    // Clear any output leftovers from the Waveform Generator (via function pointers).
+    ( hal_ll_tim_hw_specifics_map_local->mapped_functions.mapped_function_hw_init_pwm_mode )
+    ( hal_ll_tim_hw_specifics_map_local->base );
+
+    // Disable Event Action Engine.
+    clear_reg( hal_ll_hw_reg->hal_ll_pwm_ctrld_reg_address );
+
+    // Give it some time to stabilize.
+    hal_ll_tim_wait_for_sync( hal_ll_clock_value );
+}
+
+static void _hal_ll_tim_init( hal_ll_tim_hw_specifics_map_t *map ) {
+    // Configure PWM pin.
+    _hal_ll_tim_configure_pin( hal_ll_tim_hw_specifics_map_local, true );
+
+    // Finally, configure Timer/Counter (PWM) registers.
+    _hal_ll_tim_hw_init( map );
+}
+
+// ---------------------------------------------------- STATIC POINTER FUNCTIONS
+static inline void map_pointer_functions( uint8_t hal_ll_module_id, uint8_t channel ) {
+    switch ( channel ) {
+        case ( HAL_LL_TIM_CH_A ):
+            hal_ll_tim_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_signal_start = &ptr_function_timer_counter_start_ch_a;
+            hal_ll_tim_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_signal_stop = &ptr_function_timer_counter_stop_ch_a;
+            hal_ll_tim_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_hw_init_pwm_mode = &ptr_function_timer_counter_hw_init_pwm_mode_ch_a;
+            hal_ll_tim_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_set_duty = &ptr_function_timer_counter_set_duty_ch_a;
+            break;
+        case ( HAL_LL_TIM_CH_B ):
+            hal_ll_tim_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_signal_start = &ptr_function_timer_counter_start_ch_b;
+            hal_ll_tim_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_signal_stop = &ptr_function_timer_counter_stop_ch_b;
+            hal_ll_tim_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_hw_init_pwm_mode = &ptr_function_timer_counter_hw_init_pwm_mode_ch_b;
+            hal_ll_tim_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_set_duty = &ptr_function_timer_counter_set_duty_ch_b;
+            break;
+        case ( HAL_LL_TIM_CH_C ):
+            hal_ll_tim_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_signal_start = &ptr_function_timer_counter_start_ch_c;
+            hal_ll_tim_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_signal_stop = &ptr_function_timer_counter_stop_ch_c;
+            hal_ll_tim_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_hw_init_pwm_mode = &ptr_function_timer_counter_hw_init_pwm_mode_ch_c;
+            hal_ll_tim_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_set_duty = &ptr_function_timer_counter_set_duty_ch_c;
+            break;
+        case ( HAL_LL_TIM_CH_D ):
+            hal_ll_tim_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_signal_start = &ptr_function_timer_counter_start_ch_d;
+            hal_ll_tim_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_signal_stop = &ptr_function_timer_counter_stop_ch_d;
+            hal_ll_tim_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_hw_init_pwm_mode = &ptr_function_timer_counter_hw_init_pwm_mode_ch_d;
+            hal_ll_tim_hw_specifics_map[ hal_ll_module_id ]->mapped_functions.mapped_function_set_duty = &ptr_function_timer_counter_set_duty_ch_d;
+            break;
+    }
+}
+
+static inline void ptr_function_timer_counter_start_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    #ifndef __hal_ll_tim_subset_atxmega_e5_series__
+        // Set Byte Mode to be NORMAL.
+        write_reg( hal_ll_hw_reg->hal_ll_pwm_ctrle_reg_address, HAL_LL_TIM_BYTE_MODE_NORMAL );
+
+        // Enable Output Compare channel A.
+        set_reg_bit( hal_ll_hw_reg->hal_ll_pwm_ctrlb_reg_address, HAL_LL_TIM_OUTPUT_COMPARE_CH_A );
+    #else
+        set_reg_bit( hal_ll_hw_reg->hal_ll_pwm_ctrle_reg_address, HAL_LL_TIM_OUTPUT_COMPARE_CH_A_ATXMEGA_E5_SERIES );
+    #endif
+}
+
+static inline void ptr_function_timer_counter_start_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    #ifndef __hal_ll_tim_subset_atxmega_e5_series__
+        // Set Byte Mode to be NORMAL.
+        write_reg( hal_ll_hw_reg->hal_ll_pwm_ctrle_reg_address, HAL_LL_TIM_BYTE_MODE_NORMAL );
+
+        // Enable Output Compare channel B.
+        set_reg_bit( hal_ll_hw_reg->hal_ll_pwm_ctrlb_reg_address, HAL_LL_TIM_OUTPUT_COMPARE_CH_B );
+    #else
+        // Enable Output Compare channel B.
+        set_reg_bit( hal_ll_hw_reg->hal_ll_pwm_ctrle_reg_address, HAL_LL_TIM_OUTPUT_COMPARE_CH_B_ATXMEGA_E5_SERIES );
+    #endif
+}
+
+static inline void ptr_function_timer_counter_start_ch_c( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    #ifndef __hal_ll_tim_subset_atxmega_e5_series__
+        // Set Byte Mode to be NORMAL.
+        write_reg( hal_ll_hw_reg->hal_ll_pwm_ctrle_reg_address, HAL_LL_TIM_BYTE_MODE_NORMAL );
+
+        // Enable Output Compare channel C.
+        set_reg_bit( hal_ll_hw_reg->hal_ll_pwm_ctrlb_reg_address, HAL_LL_TIM_OUTPUT_COMPARE_CH_C );
+    #else
+        // Enable Output Compare channel C.
+        set_reg_bit( hal_ll_hw_reg->hal_ll_pwm_ctrle_reg_address, HAL_LL_TIM_OUTPUT_COMPARE_CH_C_ATXMEGA_E5_SERIES );
+    #endif
+}
+
+static inline void ptr_function_timer_counter_start_ch_d( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    #ifndef __hal_ll_tim_subset_atxmega_e5_series__
+        // Set Byte Mode to be NORMAL.
+        write_reg( hal_ll_hw_reg->hal_ll_pwm_ctrle_reg_address, HAL_LL_TIM_BYTE_MODE_NORMAL );
+
+        // Enable Output Compare channel D.
+        set_reg_bit( hal_ll_hw_reg->hal_ll_pwm_ctrlb_reg_address, HAL_LL_TIM_OUTPUT_COMPARE_CH_D );
+    #else
+        // Enable Output Compare channel D.
+        set_reg_bit( hal_ll_hw_reg->hal_ll_pwm_ctrle_reg_address, HAL_LL_TIM_OUTPUT_COMPARE_CH_D_ATXMEGA_E5_SERIES );
+    #endif
+}
+
+static inline void ptr_function_timer_counter_stop_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    clear_reg_bit( hal_ll_hw_reg->hal_ll_pwm_ctrlb_reg_address, HAL_LL_TIM_OUTPUT_COMPARE_CH_A );
+}
+
+static inline void ptr_function_timer_counter_stop_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    clear_reg_bit( hal_ll_hw_reg->hal_ll_pwm_ctrlb_reg_address, HAL_LL_TIM_OUTPUT_COMPARE_CH_B );
+}
+
+static inline void ptr_function_timer_counter_stop_ch_c( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    clear_reg_bit( hal_ll_hw_reg->hal_ll_pwm_ctrlb_reg_address, HAL_LL_TIM_OUTPUT_COMPARE_CH_C );
+}
+
+static inline void ptr_function_timer_counter_stop_ch_d( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    clear_reg_bit( hal_ll_hw_reg->hal_ll_pwm_ctrlb_reg_address, HAL_LL_TIM_OUTPUT_COMPARE_CH_D );
+}
+
+static inline void ptr_function_timer_counter_hw_init_pwm_mode_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    clear_reg_bit( hal_ll_hw_reg->hal_ll_pwm_ctrlc_reg_address, HAL_LL_TIM_CMPA_BIT );
+}
+
+static inline void ptr_function_timer_counter_hw_init_pwm_mode_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    clear_reg_bit( hal_ll_hw_reg->hal_ll_pwm_ctrlc_reg_address, HAL_LL_TIM_CMPB_BIT );
+}
+
+static inline void ptr_function_timer_counter_hw_init_pwm_mode_ch_c( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    clear_reg_bit( hal_ll_hw_reg->hal_ll_pwm_ctrlc_reg_address, HAL_LL_TIM_CMPC_BIT );
+}
+
+static inline void ptr_function_timer_counter_hw_init_pwm_mode_ch_d( hal_ll_tim_base_handle_t *hal_ll_hw_reg ) {
+    clear_reg_bit( hal_ll_hw_reg->hal_ll_pwm_ctrlc_reg_address, HAL_LL_TIM_CMPD_BIT );
+}
+
+static inline void ptr_function_timer_counter_set_duty_ch_a( hal_ll_tim_base_handle_t *hal_ll_hw_reg, uint16_t duty_cycle_value ) {
+    *(uint16_t *)hal_ll_hw_reg->hal_ll_pwm_ccabuf_reg_address = duty_cycle_value;
+}
+
+static inline void ptr_function_timer_counter_set_duty_ch_b( hal_ll_tim_base_handle_t *hal_ll_hw_reg, uint16_t duty_cycle_value ) {
+    *(uint16_t *)hal_ll_hw_reg->hal_ll_pwm_ccbbuf_reg_address = duty_cycle_value;
+}
+
+static inline void ptr_function_timer_counter_set_duty_ch_c( hal_ll_tim_base_handle_t *hal_ll_hw_reg, uint16_t duty_cycle_value ) {
+    *(uint16_t *)hal_ll_hw_reg->hal_ll_pwm_cccbuf_reg_address = duty_cycle_value;
+}
+
+static inline void ptr_function_timer_counter_set_duty_ch_d( hal_ll_tim_base_handle_t *hal_ll_hw_reg, uint16_t duty_cycle_value ) {
+    *(uint16_t *)hal_ll_hw_reg->hal_ll_pwm_ccdbuf_reg_address = duty_cycle_value;
+}
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/src/uart/CMakeLists.txt b/targets/avr_8bit/mikroe/avr/src/uart/CMakeLists.txt
new file mode 100644
index 000000000..9b5e101ba
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/uart/CMakeLists.txt
@@ -0,0 +1,67 @@
+set(hal_ll_def_list "")
+if((${CORE_NAME} MATCHES "GT64K") OR (${CORE_NAME} MATCHES "LTE64K"))
+    list(APPEND hal_ll_def_list "__avr_8_bit__")
+else()
+    list(APPEND hal_ll_def_list "__family_not_supported__")
+endif()
+
+list(APPEND hal_ll_def_list ${MCU_NAME})
+
+string(LENGTH ${MCU_NAME} MEMAKE_MCU_NAME_LENGTH)
+MATH(EXPR BEGIN_INDEX "${MEMAKE_MCU_NAME_LENGTH}-3")
+string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3)
+
+## BEGIN UART
+if ( (${MCU_NAME} MATCHES "^ATXMEGA(.+)$") )
+    set(uart_implementation "implementation_2")
+elseif (${MCU_NAME} MATCHES "^AT(.+)$")
+    set(uart_implementation "implementation_1")
+else()
+    set(uart_implementation "__mcu_not_supported__")
+endif()
+## END UART
+
+mikrosdk_add_library(lib_hal_ll_uart MikroSDK.HalLowLevel.UART
+    ${uart_implementation}/hal_ll_uart.c
+
+    ../../include/hal_ll_target.h
+    ../../include/uart/hal_ll_uart.h
+    ../../include/uart/hal_ll_uart_pin_map.h
+)
+
+target_compile_definitions(lib_hal_ll_uart PUBLIC
+    ${hal_ll_def_list}
+)
+
+target_link_libraries(lib_hal_ll_uart PUBLIC
+    MikroC.Core
+    MikroSDK.HalLowLevelCore
+    MikroSDK.HalLowLevelCommon
+)
+string(TOLOWER ${MCU_NAME} MCU_NAME_LOWER)
+target_include_directories(lib_hal_ll_uart
+    PRIVATE
+    ../../include
+    ../../include/gpio
+#  BEGIN UART
+    ../../include/uart
+    ../../include/uart/${uart_pin_map}
+#  END UART
+
+    INTERFACE
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include>
+        $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/../../include/uart>
+        $<INSTALL_INTERFACE:include/hal_ll_port>
+        $<INSTALL_INTERFACE:include/${MCU_NAME_LOWER}>
+)
+list(APPEND hal_ll_def_list "MACRO_USAGE_UART")
+
+mikrosdk_install(MikroSDK.HalLowLevel.UART)
+
+install(
+    FILES
+        ../../include/uart/hal_ll_uart.h
+        ../../include/uart/hal_ll_uart_pin_map.h
+    DESTINATION
+        ${CMAKE_INSTALL_PREFIX}/include/hal_ll_port
+)
diff --git a/targets/avr_8bit/mikroe/avr/src/uart/implementation_1/hal_ll_uart.c b/targets/avr_8bit/mikroe/avr/src/uart/implementation_1/hal_ll_uart.c
new file mode 100644
index 000000000..6a43df0a3
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/uart/implementation_1/hal_ll_uart.c
@@ -0,0 +1,1132 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_uart.c
+ * @brief UART HAL LOW LEVEL layer implementation.
+ */
+
+#include "hal_ll_gpio.h"
+#include "hal_ll_core.h"
+#include "hal_ll_uart.h"
+#include "hal_ll_uart_pin_map.h"
+
+/*!< @brief Local handle list */
+static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false };
+
+// ------------------------------------------------------------- PRIVATE MACROS
+/*!< @brief Helper macro for getting hal_ll_module_state address */
+#define hal_ll_uart_get_module_state_address ((hal_ll_uart_handle_register_t *)*handle)
+/*!< @brief Helper macro for getting module specific control register structure base address // first register address */
+#define hal_ll_uart_get_handle (hal_ll_uart_handle_register_t *)hal_ll_uart_get_module_state_address->hal_ll_uart_handle
+/*!< @brief Helper macro for getting module specific control register structure */
+#define hal_ll_uart_get_base_struct(_handle) ((const hal_ll_uart_base_handle_t *)_handle)
+/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */
+#define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\
+                                             (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base
+/*!< @brief Helper macro for getting module specific base address structure directly from HAL layer handle */
+#define hal_ll_uart_get_base_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_get_handle)->hal_ll_uart_handle))->base
+
+/*!< @brief Helper macro for current Clock value (Hertz). */
+#define _fosc (Get_Fosc_kHz()*1000)
+
+/*!< @brief Helper macro for UART module sync time. */
+#define hal_ll_uart_wait_for_sync(_hal_sync_val) while( _hal_sync_val-- ){asm nop;}
+
+/*!< @brief Power module macros. */
+#define HAL_LL_PRR_PRUSART0_BIT (1)
+#define HAL_LL_PRR_PRUSART3_BIT (2)
+
+/*!< @brief Helper macros for enabling/disabling transmitter/receiver hardware drivers. */
+#define HAL_LL_UART_CREN_BIT (4)
+#define HAL_LL_UART_TXEN_BIT (3)
+
+/*!< @brief Macros defining USART Data bits values. */
+#define HAL_LL_UART_DATA_BITS_9_USCRB_REGISTER_BIT (2)
+#define HAL_LL_UART_DATA_BITS_MASK_USCRC_REGISTER (1)
+#define HAL_LL_UART_DATA_BITS_5_MASK (3)
+#define HAL_LL_UART_DATA_BITS_7_MASK (2)
+#define HAL_LL_UART_DATA_BITS_8_MASK (3)
+
+/*!< @brief Macros defining USART Parity bits values. */
+#define HAL_LL_UART_PARITY_MASK (4)
+#define HAL_LL_UART_PARITY_NONE_MASK (0)
+#define HAL_LL_UART_PARITY_EVEN_MASK (2)
+#define HAL_LL_UART_PARITY_ODD_MASK (3)
+
+/*!< @brief Macros defining USART Stop bit values and mask. */
+#define HAL_LL_UART_STOP_BIT (3)
+#define HAL_LL_UART_STOP_BITS_TWO_MASK (0x08)
+
+/*!< @brief Macro defining USART async mode clock divider. */
+#define HAL_LL_UART_ASYNCHRONOUS_MODE_CLOCK_DIVIDER (16.0)
+#define HAL_LL_UART_ASYNCHRONOUS_MODE_CLOCK_DIVIDER_U2Xn (8.0)
+
+/*!< @brief Macro defining length of Baud Rate Low register. */
+#define HAL_LL_UART_BAUD_RATE_REG_LOW_LENGTH (255)
+
+/*!< @brief Helper macros for getting appropriate Baud rate prescaler value. */
+#define HAL_LL_UART_CONTROL_AND_STATUS_REGISTER_SELECTED (0x80)
+#define HAL_LL_UART_BAUD_RATE_REGISTER_SELECTED (0x3F)
+#define HAL_LL_UART_THIRD_NIBBLE_MASK (0x0F00)
+#define HAL_LL_UART_FLOOR_OR_CEILING_MASK (0.5)
+
+/*!< @brief Helper macros for triggering UART interrupt. */
+#define HAL_LL_UART_TRIGGER_INTERRUPT (0x0)
+#define HAL_LL_UART_TXIF_BIT (6)
+#define HAL_LL_UART_RXIF_BIT (7)
+
+/*!< @brief Helper macro for retaining Control and Status Register bits. */
+#define HAL_LL_UART_FIRST_NIBBLE_MASK (0xF)
+
+/*!< @brief Helper macro for enabling double transmission speed mode. */
+#define HAL_LL_UART_DOUBLE_SPEED (1)
+
+/*!< @brief Macro used for status register flag check.
+ * Used in interrupt handlers.
+ */
+#define hal_ll_uart_get_status_flags(module_num) ( read_reg( hal_ll_uart_regs[ module_num ].uart_ucsra_reg_addr ))
+
+/*!< @brief Macro used for module interrupt enabling.
+ * Used in interrupt handlers.
+ */
+#if defined(UART_MODULE_0) && defined(UART_MODULE_1) && defined(UART_MODULE_2) && defined(UART_MODULE_3)
+#define __HAL_LL_UART_ENABLE_IT(_num,_int) (_num==hal_ll_uart_module_num(UART_MODULE_0))?(set_reg_bit(HAL_LL_USART0_UCSR0B_REG_ADDRESS,_int)): \
+                                           (_num==hal_ll_uart_module_num(UART_MODULE_1))?(set_reg_bit(HAL_LL_USART1_UCSR1B_REG_ADDRESS,_int)): \
+                                           (_num==hal_ll_uart_module_num(UART_MODULE_2))?(set_reg_bit(HAL_LL_USART2_UCSR2B_REG_ADDRESS,_int)): \
+                                           (set_reg_bit(HAL_LL_USART3_UCSR3B_REG_ADDRESS,_int))
+#elif defined(UART_MODULE_0) && defined(UART_MODULE_1) && defined(UART_MODULE_2)
+#define __HAL_LL_UART_ENABLE_IT(_num,_int) (_num==hal_ll_uart_module_num(UART_MODULE_0))?(set_reg_bit(HAL_LL_USART0_UCSR0B_REG_ADDRESS,_int)): \
+                                           (_num==hal_ll_uart_module_num(UART_MODULE_1))?(set_reg_bit(HAL_LL_USART1_UCSR1B_REG_ADDRESS,_int)): \
+                                           (set_reg_bit(HAL_LL_USART2_UCSR2B_REG_ADDRESS,_int))
+#elif defined(UART_MODULE_0) && defined(UART_MODULE_1)
+#define __HAL_LL_UART_ENABLE_IT(_num,_int) (_num==hal_ll_uart_module_num(UART_MODULE_0))?(set_reg_bit(HAL_LL_USART0_UCSR0B_REG_ADDRESS,_int)): \
+                                           (set_reg_bit(HAL_LL_USART1_UCSR1B_REG_ADDRESS,_int))
+#elif defined(UART_MODULE_1)
+#define __HAL_LL_UART_ENABLE_IT(_num,_int) (set_reg_bit(HAL_LL_USART1_UCSR1B_REG_ADDRESS,_int))
+#elif defined(UART_MODULE_0)
+#define __HAL_LL_UART_ENABLE_IT(_num,_int) (set_reg_bit(HAL_LL_USART0_UCSR0B_REG_ADDRESS,_int))
+#endif
+
+/*!< @brief Macro used for module interrupt disabling.
+ * Used in interrupt handlers.
+ */
+#if defined(UART_MODULE_0) && defined(UART_MODULE_1) && defined(UART_MODULE_2) && defined(UART_MODULE_3)
+#define __HAL_LL_UART_DISABLE_IT(_num,_int) (_num==hal_ll_uart_module_num(UART_MODULE_0))?(clear_reg_bit(HAL_LL_USART0_UCSR0B_REG_ADDRESS,_int)): \
+                                           (_num==hal_ll_uart_module_num(UART_MODULE_1))?(clear_reg_bit(HAL_LL_USART1_UCSR1B_REG_ADDRESS,_int)): \
+                                           (_num==hal_ll_uart_module_num(UART_MODULE_2))?(clear_reg_bit(HAL_LL_USART2_UCSR2B_REG_ADDRESS,_int)): \
+                                           (clear_reg_bit(HAL_LL_USART3_UCSR3B_REG_ADDRESS,_int))
+#elif defined(UART_MODULE_0) && defined(UART_MODULE_1) && defined(UART_MODULE_2)
+#define __HAL_LL_UART_DISABLE_IT(_num,_int) (_num==hal_ll_uart_module_num(UART_MODULE_0))?(clear_reg_bit(HAL_LL_USART0_UCSR0B_REG_ADDRESS,_int)): \
+                                           (_num==hal_ll_uart_module_num(UART_MODULE_1))?(clear_reg_bit(HAL_LL_USART1_UCSR1B_REG_ADDRESS,_int)): \
+                                           (clear_reg_bit(HAL_LL_USART2_UCSR2B_REG_ADDRESS,_int))
+#elif defined(UART_MODULE_0) && defined(UART_MODULE_1)
+#define __HAL_LL_UART_DISABLE_IT(_num,_int) (_num==hal_ll_uart_module_num(UART_MODULE_0))?(clear_reg_bit(HAL_LL_USART0_UCSR0B_REG_ADDRESS,_int)): \
+                                           (clear_reg_bit(HAL_LL_USART1_UCSR1B_REG_ADDRESS,_int))
+#elif defined(UART_MODULE_1)
+#define __HAL_LL_UART_DISABLE_IT(_num,_int) (clear_reg_bit(HAL_LL_USART1_UCSR1B_REG_ADDRESS,_int))
+#elif defined(UART_MODULE_0)
+#define __HAL_LL_UART_DISABLE_IT(_num,_int) (clear_reg_bit(HAL_LL_USART0_UCSR0B_REG_ADDRESS,_int))
+#endif
+
+/*!< @brief Macro used for module interrupt source check.
+ * Used in interrupt handlers.
+ */
+#define __HAL_LL_UART_GET_IT_SOURCE(_num,_int) read_reg_bits(hal_ll_uart_regs[_num].uart_ucsrb_reg_addr,(1<<_int))
+
+// ------------------------------------------------------------------ TYPEDEFS
+/*!< @brief UART HW register structure */
+typedef struct {
+    hal_ll_base_addr_t uart_udr_reg_addr; // USART I/O Data register.
+    hal_ll_base_addr_t uart_ucsra_reg_addr; // USART Control and Status register A.
+    hal_ll_base_addr_t uart_ucsrb_reg_addr; // USART Control and Status register B.
+    hal_ll_base_addr_t uart_ucsrc_reg_addr; // USART Control and Status register C.
+    hal_ll_base_addr_t uart_ubrrh_reg_addr; // USART Baud Rate High register.
+    hal_ll_base_addr_t uart_ubrrl_reg_addr; // USART Baud Rate Low register.
+} hal_ll_uart_base_handle_t;
+
+/*!< @brief UART baud rate structure */
+typedef struct {
+    uint32_t baud;
+    uint32_t real_baud;
+} hal_ll_uart_baud_t;
+
+/*!< @brief UART hw specific structure */
+typedef struct {
+    const hal_ll_uart_base_handle_t *base;
+    hal_ll_pin_name_t module_index;
+    hal_ll_uart_pins_t pins;
+    hal_ll_uart_baud_t baud_rate;
+    hal_ll_uart_parity_t parity;
+    hal_ll_uart_stop_bits_t stop_bit;
+    hal_ll_uart_data_bits_t data_bit;
+} hal_ll_uart_hw_specifics_map_t;
+
+/*!< @brief UART hw specific module values */
+typedef struct {
+    hal_ll_pin_name_t pin_tx;
+    hal_ll_pin_name_t pin_rx;
+} hal_ll_uart_pin_id;
+
+/*!< @brief UART hw specific error values */
+typedef enum {
+    HAL_LL_UART_SUCCESS = 0,
+    HAL_LL_UART_WRONG_PINS,
+    HAL_LL_UART_MODULE_ERROR,
+
+    HAL_LL_UART_ERROR = (-1)
+} hal_ll_uart_err_t;
+
+/*!< @brief UART module state selection */
+typedef enum {
+    HAL_LL_UART_DISABLE = 0,
+    HAL_LL_UART_ENABLE
+} hal_ll_uart_state_t;
+
+// ------------------------------------------------------------------ CONSTANTS
+/*!< @brief UART modules register array */
+static const hal_ll_uart_base_handle_t hal_ll_uart_regs[ UART_MODULE_COUNT + 1 ] = {
+    #ifdef UART_MODULE_0
+    { HAL_LL_USART0_UDR0_REG_ADDRESS, HAL_LL_USART0_UCSR0A_REG_ADDRESS, HAL_LL_USART0_UCSR0B_REG_ADDRESS,
+      HAL_LL_USART0_UCSR0C_REG_ADDRESS, HAL_LL_USART0_UBRR0H_REG_ADDRESS, HAL_LL_USART0_UBRR0L_REG_ADDRESS },
+    #endif
+    #ifdef UART_MODULE_1
+    { HAL_LL_USART1_UDR1_REG_ADDRESS, HAL_LL_USART1_UCSR1A_REG_ADDRESS, HAL_LL_USART1_UCSR1B_REG_ADDRESS,
+      HAL_LL_USART1_UCSR1C_REG_ADDRESS, HAL_LL_USART1_UBRR1H_REG_ADDRESS, HAL_LL_USART1_UBRR1L_REG_ADDRESS },
+    #endif
+    #ifdef UART_MODULE_2
+    { HAL_LL_USART2_UDR2_REG_ADDRESS, HAL_LL_USART2_UCSR2A_REG_ADDRESS, HAL_LL_USART2_UCSR2B_REG_ADDRESS,
+      HAL_LL_USART2_UCSR2C_REG_ADDRESS, HAL_LL_USART2_UBRR2H_REG_ADDRESS, HAL_LL_USART2_UBRR2L_REG_ADDRESS },
+    #endif
+    #ifdef UART_MODULE_3
+    { HAL_LL_USART3_UDR3_REG_ADDRESS, HAL_LL_USART3_UCSR3A_REG_ADDRESS, HAL_LL_USART3_UCSR3B_REG_ADDRESS,
+      HAL_LL_USART3_UCSR3C_REG_ADDRESS, HAL_LL_USART3_UBRR3H_REG_ADDRESS, HAL_LL_USART3_UBRR3L_REG_ADDRESS },
+    #endif
+
+    { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR,
+      HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR }
+};
+
+// ------------------------------------------------------------------ VARIABLES
+/*!< @brief Global handle variables used in functions */
+static volatile hal_ll_uart_handle_register_t *low_level_handle;
+static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local;
+
+/*!< @brief Global interrupt handlers used in functions */
+static hal_ll_uart_isr_t irq_handler;
+static handle_t objects[UART_MODULE_COUNT] = { NULL };
+
+/*!< @brief UART hardware specific info */
+static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[ UART_MODULE_COUNT + 1 ] = {
+    #ifdef UART_MODULE_0
+    { &hal_ll_uart_regs[ hal_ll_uart_module_num(UART_MODULE_0) ], hal_ll_uart_module_num(UART_MODULE_0),
+    { HAL_LL_PIN_NC, HAL_LL_UART_TXIF_BIT, HAL_LL_PIN_NC, HAL_LL_UART_RXIF_BIT },
+    { 115200, 0 }, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT },
+    #endif
+    #ifdef UART_MODULE_1
+    { &hal_ll_uart_regs[ hal_ll_uart_module_num(UART_MODULE_1) ], hal_ll_uart_module_num(UART_MODULE_1),
+    { HAL_LL_PIN_NC, HAL_LL_UART_TXIF_BIT, HAL_LL_PIN_NC, HAL_LL_UART_RXIF_BIT },
+    { 115200, 0 }, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT },
+    #endif
+    #ifdef UART_MODULE_2
+    { &hal_ll_uart_regs[ hal_ll_uart_module_num(UART_MODULE_2) ], hal_ll_uart_module_num(UART_MODULE_2),
+    { HAL_LL_PIN_NC, HAL_LL_UART_TXIF_BIT, HAL_LL_PIN_NC, HAL_LL_UART_RXIF_BIT },
+    { 115200, 0 }, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT },
+    #endif
+    #ifdef UART_MODULE_3
+    { &hal_ll_uart_regs[ hal_ll_uart_module_num(UART_MODULE_3) ], hal_ll_uart_module_num(UART_MODULE_3),
+    { HAL_LL_PIN_NC, HAL_LL_UART_TXIF_BIT, HAL_LL_PIN_NC, HAL_LL_UART_RXIF_BIT },
+    { 115200, 0 }, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT },
+    #endif
+
+    { &hal_ll_uart_regs[ hal_ll_uart_module_num(UART_MODULE_COUNT) ], HAL_LL_MODULE_ERROR,
+    { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 }, { 0, 0 }, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR }
+};
+
+// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS
+/**
+  * @brief Check if pins are adequate.
+  *
+  * Checks tx and rx pins the user has passed with pre-defined
+  * pins in tx and rx maps. Take into consideration that module
+  * index numbers have to be the same for both pins.
+  *
+  * @param[in] tx_pin - TX pre-defined pin name.
+  * @param[in] rx_pin - RX pre-defined pin name.
+  * @param[in] *index_list - Array containing pin map index numbers.
+  * @param[in] *handle_map - Map containing UART HAL low level and Driver handles.
+  * @return hal_ll_pin_name_t Module index based on pins.
+  *
+  * Returns pre-defined module index from pin maps, if pins
+  * are adequate.
+  */
+static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin,
+                                                 hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map );
+
+/**
+  * @brief Get local hardware specific map.
+  *
+  * Checks handle value and returns address of adequate
+  * hal_ll_uart_hw_specifics_map array index.
+  *
+  * @param[in] handle - Object specific context handler.
+  * @return hal_ll_uart_hw_specifics_map_t Map address.
+  *
+  * Returns pre-defined map index address based on handle value,
+  * if handle is adequate.
+  */
+static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle );
+
+/**
+  * @brief Enable clock for UART module on hardware level.
+  *
+  * Initializes UART module clock on hardware level, based on beforehand
+  * set configuration and module handler.
+  *
+  * @param[in] *map - Object specific context handler.
+  * @param[in] hal_ll_stat - True(enable clock)/False(disable clock).
+  *
+  * @return void None.
+  */
+static void hal_ll_uart_set_module_power( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state );
+
+/**
+ * @brief Maps new-found module specific values.
+ *
+ * Maps pin names and PPS values for
+ * TX and RX pins.
+ *
+ * @param[in]  module_index UART HW module index -- 0,1,2...
+ * @param[in]  *index_list  Array with TX and RX map index values
+ *
+ * @return  None
+ */
+static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list );
+
+/**
+  * @brief Sets UART pin alternate function state.
+  *
+  * Sets adequate value for alternate function settings.
+  * This function must be called if UART is to work.
+  * Based on value of hal_ll_state, alternate functions can be
+  * set or cleared.
+  *
+  * @param[in] *map - Object specific context handler.
+  * @param[in] hal_ll_state - Init/De-init
+  *
+  * @return void None.
+  */
+static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state );
+
+/**
+  * @brief Finds UART module index.
+  *
+  * Finds UART index(module number) based on
+  * handle value.
+  *
+  * @param[in] *handle - Object specific context handler.
+  *
+  * @return uint8_t Module number.
+  * Returns values from 0 to 9.
+  */
+static uint8_t hal_ll_uart_find_index( handle_t *handle );
+
+/**
+  * @brief Clears UART registers.
+  *
+  * Clears UART module configuration
+  * registers, effectively disabling the module itself.
+  * Take into consideration that any IRQ bits
+  * are not cleared.
+  *
+  * @param[in] *hal_ll_hw_reg - UART HW register structure.
+  *
+  * @return void None.
+  */
+static void hal_ll_uart_clear_regs( const hal_ll_uart_base_handle_t *hal_ll_hw_reg );
+
+/**
+ * @brief Sets desired baud rate on hardware level.
+ *
+ * Initializes module with specified baud rate value.
+ * Take into consideration that if the difference
+ * between desired baud rate and actual baud
+ * rate the hw was initialized to is greater than
+ * 1%, baud rate shall not be set.
+ * If this occurs, return value shall be
+ * the error percentage.
+ *
+ * @param[in] *map - Object specific context handler.
+ *
+ * @return void None.
+ */
+static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map );
+
+/**
+ * @brief Sets desired data bits.
+ *
+ * Initializes module on hardware level
+ * with specified data bit bit value.
+ *
+ * @param[in] *map - Object specific context handler.
+ *
+ * @return void None.
+ */
+static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map );
+
+/**
+ * @brief Sets desired parity.
+ *
+ * Initializes module on hardware level
+ * with specified parity value.
+ *
+ * @param[in] *map - Object specific context handler.
+ *
+ * @return void None.
+ */
+static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map );
+
+/**
+ * @brief Sets desired stop bits.
+ *
+ * Initializes module on hardware level
+ * with specified stop bit value.
+ *
+ * @param[in] *map - Object specific context handler.
+ *
+ * @return void None.
+ */
+static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map );
+
+/**
+ * @brief Sets module TX line state.
+ *
+ * Enables/disables specific UART module
+ * TX pin state
+ *
+ * @param[in] *hal_ll_hw_reg - UART HW register structure.
+ * @param[in] pin_state - true(enable transmitter pin) / false(disable transmitter pin)
+ *
+ * @return void None.
+ */
+static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state );
+
+/**
+ * @brief Sets module RX line state.
+ *
+ * Enables/disables specific UART module
+ * RX pin state
+ *
+ * @param[in] *hal_ll_hw_reg - UART HW register structure.
+ * @param[in] pin_state - true(enable receive pin) / false(disable receive pin)
+ *
+ * @return void None.
+ */
+static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state );
+
+/**
+ * @brief Initialize UART module.
+ *
+ * Enables UART module clogk gate first.
+ * Sets pin alternate function state.
+ * Initializes specific UART module.
+ *
+ * @param[in] *map - Object specific context handler.
+ *
+ * @return void None.
+ */
+static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map );
+
+/**
+ * @brief Initialize UART module on the hardware level.
+ *
+ * Performs UART module initialization on
+ * the hardware level.
+ *
+ * Procedure:
+ * 1. Clears control registers
+ * 2. Sets baud rate value
+ * 3. Enables transmit pin
+ * 4. Enables receive pin
+ * 5. Enables power for specific module
+ *
+ * @param[in] *map - Object specific context handler.
+ *
+ * @return void None.
+ */
+static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map );
+// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS
+hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin,
+                                          hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) {
+    hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = { HAL_LL_PIN_NC, HAL_LL_PIN_NC };
+    uint8_t pin_check_result;
+
+    // Check if pins are valid
+    if ( HAL_LL_PIN_NC == ( pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map ) ) ) {
+        return HAL_LL_UART_WRONG_PINS;
+    }
+
+    if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) ||
+         (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) {
+            hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false );
+
+            hal_ll_uart_map_pins( pin_check_result, &index_list );
+
+            hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true );
+
+            handle_map[pin_check_result]->init_ll_state = false;
+    }
+
+    *hal_module_id = pin_check_result;
+
+    hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base;
+
+    handle_map[pin_check_result]->hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle;
+
+    return HAL_LL_UART_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) {
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address );
+    hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC};
+    uint8_t pin_check_result;
+
+    if ( HAL_LL_PIN_NC  == ( pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name,
+        hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) ) {
+        return HAL_LL_UART_WRONG_PINS;
+    };
+
+    hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local );
+
+    hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base;
+    hal_ll_module_state[pin_check_result].init_ll_state = true;
+
+    return HAL_LL_UART_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) {
+    low_level_handle = hal_ll_uart_get_handle;
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address );
+
+    low_level_handle->init_ll_state = false;
+
+    hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud;
+
+    hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local );
+
+    low_level_handle->init_ll_state = true;
+
+    return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud;
+}
+
+hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) {
+    low_level_handle = hal_ll_uart_get_handle;
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address );
+
+    low_level_handle->init_ll_state = false;
+
+    hal_ll_uart_hw_specifics_map_local->parity = parity;
+
+    hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local );
+
+    low_level_handle->init_ll_state = true;
+
+    return HAL_LL_UART_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) {
+    low_level_handle = hal_ll_uart_get_handle;
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address );
+
+    //------------------------------------------------
+    /// @note: AVR microcontrollers do not utilize
+    // half stop bit and one and a half bit.
+    //------------------------------------------------
+    if ( ( HAL_LL_UART_STOP_BITS_HALF == stop_bit ) || ( HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF == stop_bit ) ) {
+        return HAL_LL_UART_MODULE_ERROR;
+    }
+
+    low_level_handle->init_ll_state = false;
+
+    hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit;
+
+    hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local );
+
+    low_level_handle->init_ll_state = true;
+
+    return HAL_LL_UART_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) {
+    low_level_handle = hal_ll_uart_get_handle;
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address );
+
+    low_level_handle->init_ll_state = false;
+
+    hal_ll_uart_hw_specifics_map_local->data_bit = data_bit;
+
+    hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local );
+
+    low_level_handle->init_ll_state = true;
+
+    return HAL_LL_UART_SUCCESS;
+}
+
+void hal_ll_uart_close( handle_t *handle ) {
+    low_level_handle = hal_ll_uart_get_handle;
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address );
+
+    if( NULL != low_level_handle->hal_ll_uart_handle ) {
+        hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false );
+
+        hal_ll_uart_irq_disable( handle, HAL_LL_UART_IRQ_RX );
+        hal_ll_uart_irq_disable( handle, HAL_LL_UART_IRQ_TX );
+
+        hal_ll_uart_clear_regs( hal_ll_uart_hw_specifics_map_local->base );
+
+        // Power-down appropriate UART module via Power Reduction Register (if available).
+        #if HAL_LL_POWER_REDUCTION
+        hal_ll_uart_set_module_power( hal_ll_uart_hw_specifics_map_local, false );
+        #endif
+
+        hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC;
+        hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC;
+
+        hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL;
+        hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0;
+
+        irq_handler = NULL;
+        objects[ hal_ll_uart_find_index( handle ) ] = NULL;
+
+        low_level_handle->hal_ll_uart_handle = NULL;
+        low_level_handle->hal_drv_uart_handle = NULL;
+
+        low_level_handle->init_ll_state = false;
+    }
+}
+
+void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) {
+    irq_handler = handler;
+    objects[ hal_ll_uart_find_index( handle ) ] = obj;
+}
+
+void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) {
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address);
+
+    switch ( irq ) {
+        case HAL_LL_UART_IRQ_RX:
+            __HAL_LL_UART_ENABLE_IT( hal_ll_uart_hw_specifics_map_local->module_index,
+                                     hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pir_num );
+            break;
+
+        case HAL_LL_UART_IRQ_TX:
+            __HAL_LL_UART_ENABLE_IT( hal_ll_uart_hw_specifics_map_local->module_index,
+                                     hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pir_num );
+            break;
+
+        default:
+            break;
+    }
+}
+
+void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) {
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address);
+
+    switch ( irq ) {
+        case HAL_LL_UART_IRQ_RX:
+            __HAL_LL_UART_DISABLE_IT( hal_ll_uart_hw_specifics_map_local->module_index,
+                                      hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pir_num );
+            break;
+
+        case HAL_LL_UART_IRQ_TX:
+            __HAL_LL_UART_DISABLE_IT( hal_ll_uart_hw_specifics_map_local->module_index,
+                                      hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pir_num );
+            break;
+
+        default:
+            break;
+    }
+
+    if ( ( check_reg_bit( hal_ll_uart_regs[ hal_ll_uart_hw_specifics_map_local->module_index ].uart_ucsra_reg_addr, HAL_LL_UART_TXIF_BIT ) ) &&
+         ( check_reg_bit( hal_ll_uart_regs[ hal_ll_uart_hw_specifics_map_local->module_index ].uart_ucsra_reg_addr, HAL_LL_UART_RXIF_BIT ) ) ) {
+        switch ( hal_ll_uart_hw_specifics_map_local->module_index ) {
+            #ifdef UART_MODULE_0
+            case hal_ll_uart_module_num(UART_MODULE_0):
+                hal_ll_core_disable_irq( HAL_LL_USART0_RX_IVT_ADDRESS );
+                break;
+            #endif
+            #ifdef UART_MODULE_1
+            case hal_ll_uart_module_num(UART_MODULE_1):
+                hal_ll_core_disable_irq( HAL_LL_USART1_RX_IVT_ADDRESS );
+                break;
+            #endif
+            #ifdef UART_MODULE_2
+            case hal_ll_uart_module_num(UART_MODULE_2):
+                hal_ll_core_disable_irq( HAL_LL_USART2_RX_IVT_ADDRESS );
+                break;
+            #endif
+            #ifdef UART_MODULE_3
+            case hal_ll_uart_module_num(UART_MODULE_3):
+                hal_ll_core_disable_irq( HAL_LL_USART3_RX_IVT_ADDRESS );
+                break;
+            #endif
+
+            default:
+                break;
+        }
+    }
+}
+
+void hal_ll_uart_write( handle_t *handle, uint8_t wr_data ) {
+    const hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_handle;
+    write_reg( hal_ll_hw_reg->uart_udr_reg_addr, wr_data );
+}
+
+uint16_t hal_ll_uart_read( handle_t *handle ) {
+    const hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_handle;
+    return ( read_reg( hal_ll_hw_reg->uart_udr_reg_addr ));
+}
+
+// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS
+/*!< @brief Link handler from HAL layer */
+void hal_uart_irq_handler(handle_t obj, hal_ll_uart_irq_t event);
+
+/*!< @brief Instruct the linker which functions can be called indirectly from the "hal_uart_irq_handler" function. */
+#pragma funcall UART_RX_IRQHandler, UART_TX_IRQHandler, UART1_RX_IRQHandler, UART1_TX_IRQHandler, \
+                UART2_RX_IRQHandler, UART2_TX_IRQHandler, UART3_RX_IRQHandler, UART3_TX_IRQHandler hal_uart_irq_handler
+
+#if defined (UART_MODULE_0)
+void UART_RX_IRQHandler(void) MIKROC_IV(HAL_LL_USART0_RX_IVT_ADDRESS) {
+    if( hal_ll_uart_get_status_flags( hal_ll_uart_module_num(UART_MODULE_0) ) & ( 1 << HAL_LL_UART_RXIF_BIT ) ) {
+        if( 0 != ( __HAL_LL_UART_GET_IT_SOURCE( hal_ll_uart_module_num(UART_MODULE_0), HAL_LL_UART_RXIF_BIT ) ) ) {
+            irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_0) ], HAL_LL_UART_IRQ_RX );
+        }
+    }
+}
+
+void UART_TX_IRQHandler(void) MIKROC_IV(HAL_LL_USART0_TX_IVT_ADDRESS) {
+    if( 0 != ( __HAL_LL_UART_GET_IT_SOURCE( hal_ll_uart_module_num(UART_MODULE_0), HAL_LL_UART_TXIF_BIT ) ) ) {
+        irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_0) ], HAL_LL_UART_IRQ_TX );
+    }
+}
+#endif
+
+#if defined (UART_MODULE_1)
+void UART1_RX_IRQHandler(void) MIKROC_IV(HAL_LL_USART1_RX_IVT_ADDRESS) {
+    if( hal_ll_uart_get_status_flags( hal_ll_uart_module_num(UART_MODULE_1) ) & ( 1 << HAL_LL_UART_RXIF_BIT ) ) {
+        if( 0 != ( __HAL_LL_UART_GET_IT_SOURCE( hal_ll_uart_module_num(UART_MODULE_1), HAL_LL_UART_RXIF_BIT ) ) ) {
+            irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_1) ], HAL_LL_UART_IRQ_RX );
+        }
+    }
+}
+
+void UART1_TX_IRQHandler(void) MIKROC_IV(HAL_LL_USART1_TX_IVT_ADDRESS) {
+    if( 0 != ( __HAL_LL_UART_GET_IT_SOURCE( hal_ll_uart_module_num(UART_MODULE_1), HAL_LL_UART_TXIF_BIT ) ) ) {
+        irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_1) ], HAL_LL_UART_IRQ_TX );
+    }
+}
+#endif
+
+#if defined (UART_MODULE_2)
+void UART2_RX_IRQHandler(void) MIKROC_IV(HAL_LL_USART2_RX_IVT_ADDRESS) {
+    if( hal_ll_uart_get_status_flags( hal_ll_uart_module_num(UART_MODULE_2) ) & ( 1 << HAL_LL_UART_RXIF_BIT ) ) {
+        if( 0 != ( __HAL_LL_UART_GET_IT_SOURCE( hal_ll_uart_module_num(UART_MODULE_2), HAL_LL_UART_RXIF_BIT ) ) ) {
+            irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_2) ], HAL_LL_UART_IRQ_RX );
+        }
+    }
+}
+
+void UART2_TX_IRQHandler(void) MIKROC_IV(HAL_LL_USART2_TX_IVT_ADDRESS) {
+    if( 0 != ( __HAL_LL_UART_GET_IT_SOURCE( hal_ll_uart_module_num(UART_MODULE_2), HAL_LL_UART_TXIF_BIT ) ) ) {
+        irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_2) ], HAL_LL_UART_IRQ_TX );
+    }
+}
+#endif
+
+#if defined (UART_MODULE_3)
+void UART3_RX_IRQHandler(void) MIKROC_IV(HAL_LL_USART3_RX_IVT_ADDRESS) {
+    if( hal_ll_uart_get_status_flags( hal_ll_uart_module_num(UART_MODULE_3) ) & ( 1 << HAL_LL_UART_RXIF_BIT ) ) {
+        if( 0 != ( __HAL_LL_UART_GET_IT_SOURCE( hal_ll_uart_module_num(UART_MODULE_3), HAL_LL_UART_RXIF_BIT ) ) ) {
+            irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_3) ], HAL_LL_UART_IRQ_RX );
+        }
+    }
+}
+
+void UART3_TX_IRQHandler(void) MIKROC_IV(HAL_LL_USART3_TX_IVT_ADDRESS) {
+    if( 0 != ( __HAL_LL_UART_GET_IT_SOURCE( hal_ll_uart_module_num(UART_MODULE_3), HAL_LL_UART_TXIF_BIT ) ) ) {
+        irq_handler( objects[ hal_ll_uart_module_num(UART_MODULE_3) ], HAL_LL_UART_IRQ_TX );
+    }
+}
+#endif
+
+// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS
+static uint8_t hal_ll_uart_find_index( handle_t *handle ) {
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address);
+
+    if( hal_ll_uart_hw_specifics_map_local->base->uart_udr_reg_addr != HAL_LL_MODULE_ERROR ) {
+        return hal_ll_uart_hw_specifics_map_local->module_index;
+    } else {
+        return NULL;
+    }
+}
+
+static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin,
+                                                 hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) {
+    static const uint8_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) );
+    static const uint8_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) );
+    uint8_t hal_ll_module_id = 0;
+    uint8_t index_counter = 0;
+    uint8_t tx_index;
+    uint8_t rx_index;
+
+    if ( (HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin) ) {
+        return HAL_LL_PIN_NC;
+    }
+
+    for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) {
+        if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) {
+            for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) {
+                if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) {
+                    if ( hal_ll_uart_tx_map[ tx_index ].module_index == hal_ll_uart_rx_map[ rx_index ].module_index ) {
+                        // Get module number
+                        hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index;
+
+                        // Map pin names
+                        index_list[hal_ll_module_id]->pin_tx = tx_index;
+                        index_list[hal_ll_module_id]->pin_rx = rx_index;
+
+                        // Check if module is taken
+                        if ( NULL == handle_map[hal_ll_module_id]->hal_drv_uart_handle ) {
+                            return hal_ll_module_id;
+                        } else if ( UART_MODULE_COUNT == ++index_counter ) {
+                            return --index_counter;
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    if ( index_counter ) {
+        return hal_ll_module_id;
+    } else {
+        return HAL_LL_PIN_NC;
+    }
+}
+
+static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) {
+    uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t));
+    static uint8_t hal_ll_module_error = hal_ll_module_count;
+
+    while( hal_ll_module_count-- ) {
+        if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) {
+            return &hal_ll_uart_hw_specifics_map[hal_ll_module_count];
+        }
+    }
+
+    return &hal_ll_uart_hw_specifics_map[hal_ll_module_error];
+}
+
+static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) {
+    // Map new pins.
+    hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[module_index]->pin_tx ].pin;
+    hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[module_index]->pin_rx ].pin;
+}
+
+static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) {
+    hal_ll_gpio_pin_t local_pin;
+    if ( ( HAL_LL_PIN_NC != map->pins.tx_pin.pin_name ) && ( HAL_LL_PIN_NC != map->pins.rx_pin.pin_name ) ) {
+        if (hal_ll_state) {
+            hal_ll_gpio_configure_pin( &local_pin, map->pins.tx_pin.pin_name, HAL_LL_GPIO_DIGITAL_OUTPUT );
+            hal_ll_gpio_configure_pin( &local_pin, map->pins.rx_pin.pin_name, HAL_LL_GPIO_DIGITAL_INPUT );
+        } else {
+            hal_ll_gpio_configure_pin( &local_pin, map->pins.tx_pin.pin_name, HAL_LL_GPIO_DIGITAL_INPUT );
+            hal_ll_gpio_configure_pin( &local_pin, map->pins.rx_pin.pin_name, HAL_LL_GPIO_DIGITAL_INPUT );
+        }
+    }
+}
+
+static void hal_ll_uart_set_module_power( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) {
+    switch ( map->module_index ) {
+        #ifdef UART_MODULE_0
+        #ifdef HAL_LL_PRR0_REG_ADDRESS
+        case hal_ll_uart_module_num(UART_MODULE_0):
+            ( hal_ll_state == true )?(clear_reg_bit( HAL_LL_PRR0_REG_ADDRESS, HAL_LL_PRR_PRUSART0_BIT )):(set_reg_bit( HAL_LL_PRR0_REG_ADDRESS, HAL_LL_PRR_PRUSART0_BIT ));
+            break;
+        #endif
+        #endif
+        #ifdef UART_MODULE_3
+        #ifdef HAL_LL_PRR1_REG_ADDRESS
+        case hal_ll_uart_module_num(UART_MODULE_3):
+            ( hal_ll_state == true )?(clear_reg_bit( HAL_LL_PRR1_REG_ADDRESS, HAL_LL_PRR_PRUSART3_BIT )):(set_reg_bit( HAL_LL_PRR1_REG_ADDRESS, HAL_LL_PRR_PRUSART3_BIT ));
+            break;
+        #endif
+        #endif
+
+        default:
+            break;
+    }
+}
+
+static void hal_ll_uart_set_baud_bare_metal(hal_ll_uart_hw_specifics_map_t *map) {
+    const hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base);
+
+    uint16_t baud_rate_prescaler_int = 0;
+    float baud_rate_prescaler_remainder = 0.0;
+    float baud_rate_prescaler_raw = 0.0;
+
+    float divider = ( check_reg_bit( hal_ll_hw_reg->uart_ucsra_reg_addr, HAL_LL_UART_DOUBLE_SPEED )) ? HAL_LL_UART_ASYNCHRONOUS_MODE_CLOCK_DIVIDER_U2Xn : HAL_LL_UART_ASYNCHRONOUS_MODE_CLOCK_DIVIDER;
+
+    // Calculate baud rate prescaler value.
+    baud_rate_prescaler_raw = ( _fosc / ( divider * map->baud_rate.baud ) ) - 1.0;
+
+    // Get the integer part of the baud rate prescaler.
+    baud_rate_prescaler_int = baud_rate_prescaler_raw;
+
+    // Get the remainder part of the baud rate prescaler.
+    baud_rate_prescaler_remainder = baud_rate_prescaler_raw - (float)baud_rate_prescaler_int;
+
+    // Apply "floor" or "ceiling" logic.
+    if ( HAL_LL_UART_FLOOR_OR_CEILING_MASK < baud_rate_prescaler_remainder ) {
+        ++baud_rate_prescaler_int;
+    }
+
+    // If prescaler value is greater than 255, populate HIGH register in first place.
+    if ( HAL_LL_UART_BAUD_RATE_REG_LOW_LENGTH < baud_rate_prescaler_int ) {
+        #ifdef REGISTERS_WITH_SHARED_IO_LOCATION
+        write_reg( hal_ll_hw_reg->uart_ubrrh_reg_addr, ( ( ( baud_rate_prescaler_int & HAL_LL_UART_THIRD_NIBBLE_MASK ) >> 8 ) &
+        HAL_LL_UART_BAUD_RATE_REGISTER_SELECTED ) );
+        #else
+        write_reg( hal_ll_hw_reg->uart_ubrrh_reg_addr, ( ( baud_rate_prescaler_int & HAL_LL_UART_THIRD_NIBBLE_MASK ) >> 8 ) );
+        #endif
+    }
+
+    // Populate LOW register with lower eight bits of baud rate value.
+    write_reg( hal_ll_hw_reg->uart_ubrrl_reg_addr, (uint8_t)baud_rate_prescaler_int );
+
+    // Memorize actual baud rate.
+    map->baud_rate.real_baud = ( _fosc / ( divider * ( baud_rate_prescaler_int + 1 ) ) );
+}
+
+static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) {
+    const hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base);
+
+    switch ( map->stop_bit ) {
+        case HAL_LL_UART_STOP_BITS_ONE:
+            clear_reg_bit( hal_ll_hw_reg->uart_ucsrc_reg_addr, HAL_LL_UART_STOP_BIT );
+            break;
+        case HAL_LL_UART_STOP_BITS_TWO:
+            #ifdef REGISTERS_WITH_SHARED_IO_LOCATION
+            *(uint8_t *)hal_ll_hw_reg->uart_ucsrc_reg_addr &= ( HAL_LL_UART_CONTROL_AND_STATUS_REGISTER_SELECTED |
+            HAL_LL_UART_STOP_BITS_TWO_MASK );
+            #else
+            set_reg_bit( hal_ll_hw_reg->uart_ucsrc_reg_addr, HAL_LL_UART_STOP_BIT );
+            #endif
+            break;
+
+        default:
+            //------------------------------------------------
+            /// @note: AVR microcontrollers do not utilize
+            // half stop bit and one and a half stop bit.
+            //------------------------------------------------
+            break;
+    }
+}
+
+static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) {
+    const hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base);
+
+    switch ( map->data_bit ) {
+        case HAL_LL_UART_DATA_BITS_7:
+            #ifdef REGISTERS_WITH_SHARED_IO_LOCATION
+            write_reg( hal_ll_hw_reg->uart_ucsrc_reg_addr, HAL_LL_UART_CONTROL_AND_STATUS_REGISTER_SELECTED |
+            ( HAL_LL_UART_DATA_BITS_7_MASK << HAL_LL_UART_DATA_BITS_MASK_USCRC_REGISTER ) );
+            #else
+            set_reg_bit( hal_ll_hw_reg->uart_ucsrc_reg_addr, HAL_LL_UART_DATA_BITS_7_MASK << HAL_LL_UART_DATA_BITS_MASK_USCRC_REGISTER );
+            clear_reg_bit( hal_ll_hw_reg->uart_ucsrb_reg_addr, HAL_LL_UART_DATA_BITS_9_USCRB_REGISTER_BIT );
+            #endif
+            break;
+        case HAL_LL_UART_DATA_BITS_8:
+            #ifdef REGISTERS_WITH_SHARED_IO_LOCATION
+            write_reg( hal_ll_hw_reg->uart_ucsrc_reg_addr, HAL_LL_UART_CONTROL_AND_STATUS_REGISTER_SELECTED |
+            ( HAL_LL_UART_DATA_BITS_8_MASK << HAL_LL_UART_DATA_BITS_MASK_USCRC_REGISTER ) );
+            #else
+            set_reg_bits( hal_ll_hw_reg->uart_ucsrc_reg_addr, HAL_LL_UART_DATA_BITS_8_MASK << HAL_LL_UART_DATA_BITS_MASK_USCRC_REGISTER );
+            clear_reg_bit( hal_ll_hw_reg->uart_ucsrb_reg_addr, HAL_LL_UART_DATA_BITS_9_USCRB_REGISTER_BIT );
+            #endif
+            break;
+        case HAL_LL_UART_DATA_BITS_9:
+            #ifdef REGISTERS_WITH_SHARED_IO_LOCATION
+            write_reg( hal_ll_hw_reg->uart_ucsrc_reg_addr, HAL_LL_UART_CONTROL_AND_STATUS_REGISTER_SELECTED |
+            ( HAL_LL_UART_DATA_BITS_8_MASK << HAL_LL_UART_DATA_BITS_MASK_USCRC_REGISTER ) );
+            #else
+            set_reg_bits( hal_ll_hw_reg->uart_ucsrc_reg_addr, HAL_LL_UART_DATA_BITS_8_MASK << HAL_LL_UART_DATA_BITS_MASK_USCRC_REGISTER );
+            #endif
+            set_reg_bit( hal_ll_hw_reg->uart_ucsrb_reg_addr, HAL_LL_UART_DATA_BITS_9_USCRB_REGISTER_BIT );
+            break;
+
+        default:
+            break;
+    }
+}
+
+static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) {
+const hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base );
+
+    switch( map->parity ) {
+        case HAL_LL_UART_PARITY_NONE:
+            #ifdef REGISTERS_WITH_SHARED_IO_LOCATION
+            *(uint8_t *)hal_ll_hw_reg->uart_ucsrc_reg_addr &= HAL_LL_UART_CONTROL_AND_STATUS_REGISTER_SELECTED |
+            HAL_LL_UART_FIRST_NIBBLE_MASK;
+            #else
+            clear_reg_bits( hal_ll_hw_reg->uart_ucsrc_reg_addr, HAL_LL_UART_PARITY_NONE_MASK << HAL_LL_UART_PARITY_MASK );
+            #endif
+            break;
+        case HAL_LL_UART_PARITY_EVEN:
+            #ifdef REGISTERS_WITH_SHARED_IO_LOCATION
+            set_reg_bits( hal_ll_hw_reg->uart_ucsrc_reg_addr, HAL_LL_UART_CONTROL_AND_STATUS_REGISTER_SELECTED |
+            ( HAL_LL_UART_PARITY_ODD_MASK << HAL_LL_UART_PARITY_MASK ) );
+            #else
+            set_reg_bits( hal_ll_hw_reg->uart_ucsrc_reg_addr, HAL_LL_UART_PARITY_EVEN_MASK << HAL_LL_UART_PARITY_MASK );
+            #endif
+            break;
+        case HAL_LL_UART_PARITY_ODD:
+            #ifdef REGISTERS_WITH_SHARED_IO_LOCATION
+            set_reg_bits( hal_ll_hw_reg->uart_ucsrc_reg_addr, HAL_LL_UART_CONTROL_AND_STATUS_REGISTER_SELECTED |
+            ( HAL_LL_UART_PARITY_ODD_MASK << HAL_LL_UART_PARITY_MASK ) );
+            #else
+            set_reg_bits( hal_ll_hw_reg->uart_ucsrc_reg_addr, HAL_LL_UART_PARITY_ODD_MASK << HAL_LL_UART_PARITY_MASK );
+            #endif
+            break;
+
+        default:
+            break;
+    }
+}
+
+static void hal_ll_uart_set_transmitter( const hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) {
+    switch ( pin_state ) {
+        case HAL_LL_UART_DISABLE:
+            clear_reg_bit( hal_ll_hw_reg->uart_ucsrb_reg_addr, HAL_LL_UART_TXEN_BIT );
+            break;
+
+        case HAL_LL_UART_ENABLE:
+            set_reg_bit( hal_ll_hw_reg->uart_ucsrb_reg_addr, HAL_LL_UART_TXEN_BIT );
+            break;
+
+        default:
+            break;
+    }
+}
+
+static void hal_ll_uart_set_receiver( const hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) {
+    switch ( pin_state ) {
+        case HAL_LL_UART_DISABLE:
+            clear_reg_bit( hal_ll_hw_reg->uart_ucsrb_reg_addr, HAL_LL_UART_CREN_BIT );
+            break;
+
+        case HAL_LL_UART_ENABLE:
+            set_reg_bit( hal_ll_hw_reg->uart_ucsrb_reg_addr, HAL_LL_UART_CREN_BIT );
+            break;
+
+        default:
+            break;
+    }
+}
+
+static void hal_ll_uart_clear_regs( const hal_ll_uart_base_handle_t *hal_ll_hw_reg ) {
+    clear_reg( hal_ll_hw_reg->uart_ucsrc_reg_addr );
+    #ifdef REGISTERS_WITH_SHARED_IO_LOCATION
+    write_reg( hal_ll_hw_reg->uart_ucsrc_reg_addr, HAL_LL_UART_CONTROL_AND_STATUS_REGISTER_SELECTED );
+    #endif
+}
+
+static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) {
+    const hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base );
+
+    // Clear USART Control and Status register C.
+    hal_ll_uart_clear_regs( map->base );
+
+    // Set USART data bits.
+    hal_ll_uart_set_data_bits_bare_metal( map );
+
+    // Set USART parity bits.
+    hal_ll_uart_set_parity_bare_metal( map );
+
+    // Set USART stop bits.
+    hal_ll_uart_set_stop_bits_bare_metal( map );
+
+    // Set U2Xn bit to double transfer rate.
+    set_reg_bit( hal_ll_hw_reg->uart_ucsra_reg_addr, HAL_LL_UART_DOUBLE_SPEED );
+
+    // Set USART Baud rate.
+    hal_ll_uart_set_baud_bare_metal( map );
+
+    /* In order for UART Transmit interrupt to
+     * be triggered, initial dummy data write is
+     * required. Writing to the register here is
+     * harmless as we have disabled TX/RX pins and the
+     * whole UART module in `hal_ll_uart_clear_regs`
+     * function.
+     */
+    write_reg( hal_ll_hw_reg->uart_udr_reg_addr, HAL_LL_UART_TRIGGER_INTERRUPT );
+
+    // Enable Transmitter driver.
+    hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE );
+
+    // Enable Receiver driver.
+    hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE );
+}
+
+static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) {
+    /*!< @brief Static, because clock doesn't change during runtime. */
+    static const uint32_t hal_ll_clock_value = Get_Fosc_kHz();
+
+    // Power-up appropriate UART module via Power Reduction Register (if available).
+    #if HAL_LL_POWER_REDUCTION == true
+    hal_ll_uart_set_module_power( map, true );
+    #endif
+
+    // Finally, write user-defined settings into hardware registers.
+    hal_ll_uart_hw_init( map );
+
+    // Give it some time to stabilize.
+    hal_ll_uart_wait_for_sync( hal_ll_clock_value );
+}
+
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/avr/src/uart/implementation_2/hal_ll_uart.c b/targets/avr_8bit/mikroe/avr/src/uart/implementation_2/hal_ll_uart.c
new file mode 100644
index 000000000..749b9ec7c
--- /dev/null
+++ b/targets/avr_8bit/mikroe/avr/src/uart/implementation_2/hal_ll_uart.c
@@ -0,0 +1,1146 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_uart.c
+ * @brief UART HAL LOW LEVEL layer implementation.
+ */
+
+#include "hal_ll_gpio.h"
+#include "hal_ll_core.h"
+#include "hal_ll_uart.h"
+#include "hal_ll_uart_pin_map.h"
+
+/*!< @brief Macros defining control register values */
+#define HAL_LL_UART_CTRLB_RXEN_BIT        (4)
+#define HAL_LL_UART_CTRLB_TXEN_BIT        (3)
+#define HAL_LL_UART_CTRLA_RXCINTLVL_SHIFT (4)
+#define HAL_LL_UART_CTRLA_TXCINTLVL_SHIFT (2)
+
+/*!< @brief Macros defining interrupt level values. */
+#define HAL_LL_UART_INTERRUPT_LEVEL_OFF   (0x0)
+#define HAL_LL_UART_INTERRUPT_LEVEL_LO    (0x1)
+#define HAL_LL_UART_INTERRUPT_LEVEL_MED   (0x2)
+#define HAL_LL_UART_INTERRUPT_LEVEL_HI    (0x3)
+
+/*!< @brief Macros defining USART baud rate values. */
+#define HAL_LL_UART_BAUD_RATE_MUL         (16)
+#define HAL_LL_UART_BAUD_RATE_MUL_CLK2X   (8)
+#define HAL_LL_UART_CTRLB_CLK2X_BIT       (2)
+
+/*!< @brief Macros defining USART Stop bits values. */
+#define HAL_LL_UART_SBMODE_SHIFT          (3)
+#define HAL_LL_UART_SBMODE_ONE            (0)
+#define HAL_LL_UART_SBMODE_TWO            (1)
+
+/*!< @brief Macros defining USART Parity bits values. */
+#define HAL_LL_UART_PMODE_SHIFT           (4)
+#define HAL_LL_UART_PARITY_NONE           (0)
+#define HAL_LL_UART_PARITY_EVEN           (2)
+#define HAL_LL_UART_PARITY_ODD            (3)
+
+/*!< @brief Macros defining USART Data bits values. */
+#define HAL_LL_UART_CHSIZE_5BIT           (0)
+#define HAL_LL_UART_CHSIZE_6BIT           (1)
+#define HAL_LL_UART_CHSIZE_7BIT           (2)
+#define HAL_LL_UART_CHSIZE_8BIT           (3)
+#define HAL_LL_UART_CHSIZE_9BIT           (7)
+
+/*!< @brief Helper macros for triggering UART interrupt. */
+#define ASCII_START_OF_TEXT               (2)
+#define HAL_LL_UART_TRIGGER_INTERRUPT     (ASCII_START_OF_TEXT)
+#define HAL_LL_UART_STATUS_RXCIF_BIT      (7)
+#define HAL_LL_UART_STATUS_TXCIF_BIT      (6)
+#define HAL_LL_UART_STATUS_DREIF_BIT      (5)
+
+/*!< @brief Helper macros for enabling interrupts. */
+#define HAL_LL_PMIC_CTRL_HILVLEN          (0x4)
+#define HAL_LL_PMIC_CTRL_MEDLVLEN         (0x2)
+#define HAL_LL_PMIC_CTRL_LOLVLEN          (0x1)
+
+/*!< @brief Macro defining USART0 remap bit position. */
+#define HAL_LL_USART0_REMAP_BIT           (4)
+
+/*!< @brief Macro defining Power reduction register values. */
+#define HAL_LL_PRPn_USART0_MODULE_ENABLE  (4)
+#define HAL_LL_PRPn_USART1_MODULE_ENABLE  (5)
+
+/*!< @brief Macro used for calculating actual baud rate value and error value */
+#define hal_ll_uart_get_baud_error( _baud_real,_baud ) ( (float)abs( _baud_real/_baud - 1 ) * 100 )
+
+/*!< @brief Macros used for status register flag check */
+#define hal_ll_uart_get_status_flags( module_num ) ( read_reg( hal_ll_uart_regs[ module_num ].status ))
+
+/*!< @brief Macros used for enabling and disabling interrupts */
+#define __HAL_LL_UART_ENABLE_IT( _num,_int ) ( set_reg_bits( hal_ll_uart_regs[_num].ctrla, ( HAL_LL_UART_INTERRUPT_LEVEL_HI<<_int )))
+#define __HAL_LL_UART_DISABLE_IT( _num,_int ) ( clear_reg_bits( hal_ll_uart_regs[_num].ctrla, ( HAL_LL_UART_INTERRUPT_LEVEL_HI<<_int )))
+
+/*!< @brief Local handle list */
+static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t *)NULL, (handle_t *)NULL, false };
+
+// ------------------------------------------------------------- PRIVATE MACROS
+/*!< @brief Helper macro for getting hal_ll_module_state address */
+#define hal_ll_uart_get_module_state_address (( hal_ll_uart_handle_register_t *)*handle )
+/*!< @brief Helper macro for getting module specific control register structure base address // first register address */
+#define hal_ll_uart_get_handle ( hal_ll_uart_handle_register_t * )hal_ll_uart_get_module_state_address->hal_ll_uart_handle
+/*!< @brief Helper macro for getting module specific control register structure */
+#define hal_ll_uart_get_base_struct(_handle) (( const hal_ll_uart_base_handle_t * )_handle )
+/*!< @brief Helper macro for getting module specific base address directly from HAL layer handle */
+#define hal_ll_uart_get_base_from_hal_handle (( hal_ll_uart_hw_specifics_map_t * )(( hal_ll_uart_handle_register_t * )\
+                                             ((( hal_ll_uart_handle_register_t * )(handle))->hal_ll_uart_handle ))->hal_ll_uart_handle )->base
+/*!< @brief Helper macro for getting module specific base address structure directly from HAL layer handle */
+#define hal_ll_uart_get_base_handle (( hal_ll_uart_hw_specifics_map_t * )(( hal_ll_uart_get_handle )->hal_ll_uart_handle ))->base
+
+// ------------------------------------------------------------------ TYPEDEFS
+/*!< @brief UART HW register structure */
+typedef struct {
+    hal_ll_base_addr_t dat;
+    hal_ll_base_addr_t status;
+    hal_ll_base_addr_t ctrla;
+    hal_ll_base_addr_t ctrlb;
+    hal_ll_base_addr_t ctrlc;
+    hal_ll_base_addr_t baudctrla;
+    hal_ll_base_addr_t baudctrlb;
+} hal_ll_uart_base_handle_t;
+
+/*!< @brief UART baud rate structure */
+typedef struct {
+    uint32_t baud;
+    uint32_t real_baud;
+} hal_ll_uart_baud_t;
+
+/*!< @brief UART hw specific structure */
+typedef struct {
+    const hal_ll_uart_base_handle_t *base;
+    hal_ll_pin_name_t module_index;
+    hal_ll_uart_pins_t pins;
+    hal_ll_uart_baud_t baud_rate;
+    hal_ll_uart_parity_t parity;
+    hal_ll_uart_stop_bits_t stop_bit;
+    hal_ll_uart_data_bits_t data_bit;
+    bool alternate;
+} hal_ll_uart_hw_specifics_map_t;
+
+/*!< @brief UART hw specific module values */
+typedef struct {
+    hal_ll_pin_name_t pin_tx;
+    hal_ll_pin_name_t pin_rx;
+} hal_ll_uart_pin_id;
+
+/*!< @brief UART hw specific error values */
+typedef enum {
+    HAL_LL_UART_SUCCESS = 0,
+    HAL_LL_UART_WRONG_PINS,
+    HAL_LL_UART_MODULE_ERROR,
+
+    HAL_LL_UART_ERROR = (-1)
+} hal_ll_uart_err_t;
+
+/*!< @brief UART module state selection */
+typedef enum {
+    HAL_LL_UART_DISABLE = 0,
+    HAL_LL_UART_ENABLE
+} hal_ll_uart_state_t;
+
+// ------------------------------------------------------------------ CONSTANTS
+/*!< @brief UART modules register array */
+static const hal_ll_uart_base_handle_t hal_ll_uart_regs[ UART_MODULE_COUNT + 1 ] = {
+    #ifdef UART_MODULE_C0
+    { HAL_LL_USARTC0_DATA_REG_ADDRESS, HAL_LL_USARTC0_STATUS_REG_ADDRESS, HAL_LL_USARTC0_CTRLA_REG_ADDRESS, HAL_LL_USARTC0_CTRLB_REG_ADDRESS,
+      HAL_LL_USARTC0_CTRLC_REG_ADDRESS, HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS, HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS },
+    #endif
+    #ifdef UART_MODULE_C1
+    { HAL_LL_USARTC1_DATA_REG_ADDRESS, HAL_LL_USARTC1_STATUS_REG_ADDRESS, HAL_LL_USARTC1_CTRLA_REG_ADDRESS, HAL_LL_USARTC1_CTRLB_REG_ADDRESS,
+      HAL_LL_USARTC1_CTRLC_REG_ADDRESS, HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS, HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS },
+    #endif
+    #ifdef UART_MODULE_D0
+    { HAL_LL_USARTD0_DATA_REG_ADDRESS, HAL_LL_USARTD0_STATUS_REG_ADDRESS, HAL_LL_USARTD0_CTRLA_REG_ADDRESS, HAL_LL_USARTD0_CTRLB_REG_ADDRESS,
+      HAL_LL_USARTD0_CTRLC_REG_ADDRESS, HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS, HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS },
+    #endif
+    #ifdef UART_MODULE_D1
+    { HAL_LL_USARTD1_DATA_REG_ADDRESS, HAL_LL_USARTD1_STATUS_REG_ADDRESS, HAL_LL_USARTD1_CTRLA_REG_ADDRESS, HAL_LL_USARTD1_CTRLB_REG_ADDRESS,
+      HAL_LL_USARTD1_CTRLC_REG_ADDRESS, HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS, HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS },
+    #endif
+    #ifdef UART_MODULE_E0
+    { HAL_LL_USARTE0_DATA_REG_ADDRESS, HAL_LL_USARTE0_STATUS_REG_ADDRESS, HAL_LL_USARTE0_CTRLA_REG_ADDRESS, HAL_LL_USARTE0_CTRLB_REG_ADDRESS,
+      HAL_LL_USARTE0_CTRLC_REG_ADDRESS, HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS, HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS },
+    #endif
+    #ifdef UART_MODULE_E1
+    { HAL_LL_USARTE1_DATA_REG_ADDRESS, HAL_LL_USARTE1_STATUS_REG_ADDRESS, HAL_LL_USARTE1_CTRLA_REG_ADDRESS, HAL_LL_USARTE1_CTRLB_REG_ADDRESS,
+      HAL_LL_USARTE1_CTRLC_REG_ADDRESS, HAL_LL_USARTE1_BAUDCTRLA_REG_ADDRESS, HAL_LL_USARTE1_BAUDCTRLB_REG_ADDRESS },
+    #endif
+    #ifdef UART_MODULE_F0
+    { HAL_LL_USARTF0_DATA_REG_ADDRESS, HAL_LL_USARTF0_STATUS_REG_ADDRESS, HAL_LL_USARTF0_CTRLA_REG_ADDRESS, HAL_LL_USARTF0_CTRLB_REG_ADDRESS,
+      HAL_LL_USARTF0_CTRLC_REG_ADDRESS, HAL_LL_USARTF0_BAUDCTRLA_REG_ADDRESS, HAL_LL_USARTF0_BAUDCTRLB_REG_ADDRESS },
+    #endif
+    #ifdef UART_MODULE_F1
+    { HAL_LL_USARTF1_DATA_REG_ADDRESS, HAL_LL_USARTF1_STATUS_REG_ADDRESS, HAL_LL_USARTF1_CTRLA_REG_ADDRESS, HAL_LL_USARTF1_CTRLB_REG_ADDRESS,
+      HAL_LL_USARTF1_CTRLC_REG_ADDRESS, HAL_LL_USARTF1_BAUDCTRLA_REG_ADDRESS, HAL_LL_USARTF1_BAUDCTRLB_REG_ADDRESS },
+    #endif
+
+    { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR }
+};
+
+// ------------------------------------------------------------------ VARIABLES
+/*!< @brief Global handle variables used in functions */
+static volatile hal_ll_uart_handle_register_t *low_level_handle;
+static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local;
+
+/*!< @brief Global interrupt handlers used in functions */
+static hal_ll_uart_isr_t irq_handler;
+static handle_t objects[UART_MODULE_COUNT] = { NULL };
+
+/*!< @brief UART hardware specific info */
+static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[ UART_MODULE_COUNT + 1 ] = {
+    #ifdef UART_MODULE_C0
+    { &hal_ll_uart_regs[hal_ll_uart_module_num( UART_MODULE_C0 )], hal_ll_uart_module_num( UART_MODULE_C0 ),
+      { HAL_LL_PIN_NC, HAL_LL_UART_STATUS_TXCIF_BIT, HAL_LL_PIN_NC, HAL_LL_UART_STATUS_RXCIF_BIT },
+      {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT, false },
+    #endif
+    #ifdef UART_MODULE_C1
+    { &hal_ll_uart_regs[hal_ll_uart_module_num( UART_MODULE_C1 )], hal_ll_uart_module_num( UART_MODULE_C1 ),
+      { HAL_LL_PIN_NC, HAL_LL_UART_STATUS_TXCIF_BIT, HAL_LL_PIN_NC, HAL_LL_UART_STATUS_RXCIF_BIT },
+      {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT, false },
+    #endif
+    #ifdef UART_MODULE_D0
+    { &hal_ll_uart_regs[hal_ll_uart_module_num( UART_MODULE_D0 )], hal_ll_uart_module_num( UART_MODULE_D0 ),
+      { HAL_LL_PIN_NC, HAL_LL_UART_STATUS_TXCIF_BIT, HAL_LL_PIN_NC, HAL_LL_UART_STATUS_RXCIF_BIT },
+      {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT, false },
+    #endif
+    #ifdef UART_MODULE_D1
+    { &hal_ll_uart_regs[hal_ll_uart_module_num( UART_MODULE_D1 )], hal_ll_uart_module_num( UART_MODULE_D1 ),
+      { HAL_LL_PIN_NC, HAL_LL_UART_STATUS_TXCIF_BIT, HAL_LL_PIN_NC, HAL_LL_UART_STATUS_RXCIF_BIT },
+      {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT, false },
+    #endif
+    #ifdef UART_MODULE_E0
+    { &hal_ll_uart_regs[hal_ll_uart_module_num( UART_MODULE_E0 )], hal_ll_uart_module_num( UART_MODULE_E0 ),
+      { HAL_LL_PIN_NC, HAL_LL_UART_STATUS_TXCIF_BIT, HAL_LL_PIN_NC, HAL_LL_UART_STATUS_RXCIF_BIT },
+      {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT, false },
+    #endif
+    #ifdef UART_MODULE_E1
+    { &hal_ll_uart_regs[hal_ll_uart_module_num( UART_MODULE_E1 )], hal_ll_uart_module_num( UART_MODULE_E1 ),
+      { HAL_LL_PIN_NC, HAL_LL_UART_STATUS_TXCIF_BIT, HAL_LL_PIN_NC, HAL_LL_UART_STATUS_RXCIF_BIT },
+      {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT, false },
+    #endif
+    #ifdef UART_MODULE_F0
+    { &hal_ll_uart_regs[hal_ll_uart_module_num( UART_MODULE_F0 )], hal_ll_uart_module_num( UART_MODULE_F0 ),
+      { HAL_LL_PIN_NC, HAL_LL_UART_STATUS_TXCIF_BIT, HAL_LL_PIN_NC, HAL_LL_UART_STATUS_RXCIF_BIT },
+      {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT, false },
+    #endif
+    #ifdef UART_MODULE_F1
+    { &hal_ll_uart_regs[hal_ll_uart_module_num( UART_MODULE_F1 )], hal_ll_uart_module_num( UART_MODULE_F1 ),
+      { HAL_LL_PIN_NC, HAL_LL_UART_STATUS_TXCIF_BIT, HAL_LL_PIN_NC, HAL_LL_UART_STATUS_RXCIF_BIT },
+      {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT, false },
+    #endif
+
+    { &hal_ll_uart_regs[hal_ll_uart_module_num( UART_MODULE_COUNT)], HAL_LL_MODULE_ERROR,
+      { HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0 },
+      {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, false }
+};
+
+// ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS
+/**
+  * @brief  Check if pins are adequate.
+  *
+  * Checks tx and rx pins the user has passed with pre-defined
+  * pins in tx and rx maps. Take into consideration that module
+  * index numbers have to be the same for both pins.
+  *
+  * @param[in]  tx_pin - TX pre-defined pin name.
+  * @param[in]  rx_pin - RX pre-defined pin name.
+  * @param[in]  *index_list - Array containing pin map index numbers.
+  * @param[in]  *handle_map - Map containing UART HAL low level and Driver handles.
+  * @return hal_ll_pin_name_t Module index based on pins.
+  *
+  * Returns pre-defined module index from pin maps, if pins
+  * are adequate.
+  */
+static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map );
+
+/**
+  * @brief  Get local hardware specific map.
+  *
+  * Checks handle value and returns address of adequate
+  * hal_ll_uart_hw_specifics_map array index.
+  *
+  * @param[in]  handle - Object specific context handler.
+  * @return hal_ll_uart_hw_specifics_map_t Map address.
+  *
+  * Returns pre-defined map index address based on handle value,
+  * if handle is adequate.
+  */
+static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle );
+
+/**
+  * @brief Enable or disable clock for UART module on hardware level.
+  *
+  * Initializes UART module clock on hardware level, based on beforehand
+  * set configuration and module handler.
+  *
+  * @param[in] module_num - Number of UART module.
+  * @param[in] hal_ll_stat - True(enable clock)/False(disable clock).
+  *
+  * @return void None.
+  */
+static void hal_ll_uart_power_reduction_enable( uint8_t module_num, bool hal_ll_state );
+
+/**
+ * @brief  Maps new-found module specific values.
+ *
+ * Maps pin names and PPS values for
+ * TX and RX pins.
+ *
+ * @param[in]  module_index UART HW module index -- 0,1,2...
+ * @param[in]  *index_list  Array with TX and RX map index values
+ *
+ * @return  None
+ */
+static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list );
+
+/**
+  * @brief  Sets UART pin alternate function state.
+  *
+  * Sets adequate value for alternate function settings.
+  * This function must be called if UART is to work.
+  * Based on value of hal_ll_state, alternate functions can be
+  * set or cleared.
+  *
+  * @param[in]  map - Object specific context handler.
+  * @param[in]  hal_ll_state - Init/De-init
+  *
+  * @return void None.
+  */
+static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state );
+
+/**
+  * @brief  Finds UART module index.
+  *
+  * Finds UART index(module number) based on
+  * handle value.
+  *
+  * @param[in]  handle - Object specific context handler.
+  *
+  * @return uint8_t Module number.
+  * Returns values from 0 to 9.
+  */
+static uint8_t hal_ll_uart_find_index( handle_t *handle );
+
+/**
+  * @brief  Clears UART registers.
+  *
+  * Clears UART module configuration
+  * registers, effectively disabling the module itself.
+  * Take into consideration that any IRQ bits
+  * are not cleared.
+  *
+  * @param[in]  hal_ll_hw_reg - UART HW register structure.
+  *
+  * @return void None.
+  */
+static void hal_ll_uart_clear_regs( const hal_ll_uart_base_handle_t *hal_ll_hw_reg );
+
+/**
+ * @brief  Sets desired baud rate on hardware level.
+ *
+ * Initializes module with specified baud rate value.
+ * Take into consideration that if the difference
+ * between desired baud rate and actual baud
+ * rate the hw was initialized to is greater than
+ * 1%, baud rate shall not be set.
+ * If this occurs, return value shall be
+ * the error percentage.
+ *
+ * @param[in]  map - Object specific context handler.
+ *
+ * @return void None.
+ */
+static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map );
+
+/**
+ * @brief  Sets desired data bits.
+ *
+ * Initializes module on hardware level
+ * with specified data bit bit value.
+ *
+ * @param[in]  map - Object specific context handler.
+ *
+ * @return void None.
+ */
+static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map );
+
+/**
+ * @brief  Sets desired parity.
+ *
+ * Initializes module on hardware level
+ * with specified parity value.
+ *
+ * @param[in]  map - Object specific context handler.
+ *
+ * @return void None.
+ */
+static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map );
+
+/**
+ * @brief  Sets desired stop bits.
+ *
+ * Initializes module on hardware level
+ * with specified stop bit value.
+ *
+ * @param[in]  map - Object specific context handler.
+ *
+ * @return void None.
+ */
+static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map );
+
+/**
+ * @brief  Sets module TX line state.
+ *
+ * Enables/disables specific UART module
+ * TX pin state
+ *
+ * @param[in]  hal_ll_hw_reg - UART HW register structure.
+ * @param[in]  pin_state - true(enable transmitter pin) / false(disable transmitter pin)
+ *
+ * @return void None.
+ */
+static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state );
+
+/**
+ * @brief  Sets module RX line state.
+ *
+ * Enables/disables specific UART module
+ * RX pin state
+ *
+ * @param[in]  hal_ll_hw_reg - UART HW register structure.
+ * @param[in]  pin_state - true(enable receive pin) / false(disable receive pin)
+ *
+ * @return void None.
+ */
+static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state );
+
+/**
+ * @brief  Initialize UART module.
+ *
+ * Initializes specific UART module.
+ *
+ * @param[in]  map - Object specific context handler.
+ *
+ * @return void None.
+ */
+static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map );
+
+/**
+ * @brief  Initialize UART module on the hardware level.
+ *
+ * Performs UART module initialization on
+ * the hardware level.
+ *
+ * Procedure:
+ * 1. Clears control registers
+ * 2. Sets baud rate value
+ * 3. Enables transmit pin
+ * 4. Enables receive pin
+ * 5. Enables power for specific module
+ *
+ * @param[in]  map - Object specific context handler.
+ *
+ * @return void None.
+ */
+static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map );
+
+// ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS
+hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) {
+    hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = { HAL_LL_PIN_NC, HAL_LL_PIN_NC };
+    uint8_t pin_check_result;
+
+    // Check if pins are valid
+    if ( HAL_LL_PIN_NC == ( pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map ) ) ) {
+        return HAL_LL_UART_WRONG_PINS;
+    }
+
+    if ( ( hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin ) ||
+         ( hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin ) ) {
+            hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false );
+
+            hal_ll_uart_map_pins( pin_check_result, &index_list );
+
+            hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true );
+
+            handle_map[pin_check_result]->init_ll_state = false;
+    }
+
+    *hal_module_id = pin_check_result;
+
+    hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base;
+
+    handle_map[pin_check_result]->hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle;
+
+    return HAL_LL_UART_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) {
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address );
+    hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC};
+    uint8_t pin_check_result;
+
+    if ( HAL_LL_PIN_NC == ( pin_check_result = hal_ll_uart_check_pins( hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name,
+        hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name, &index_list, (void *)0 ) ) ) {
+        return HAL_LL_UART_WRONG_PINS;
+    };
+
+    hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local );
+
+    hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base;
+    hal_ll_module_state[pin_check_result].init_ll_state = true;
+
+    return HAL_LL_UART_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) {
+    low_level_handle = hal_ll_uart_get_handle;
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address );
+
+    low_level_handle->init_ll_state = false;
+
+    hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud;
+
+    hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local );
+
+    low_level_handle->init_ll_state = true;
+
+    return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud;
+}
+
+hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) {
+    low_level_handle = hal_ll_uart_get_handle;
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address );
+
+    low_level_handle->init_ll_state = false;
+
+    hal_ll_uart_hw_specifics_map_local->parity = parity;
+
+    hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local );
+
+    low_level_handle->init_ll_state = true;
+
+    return HAL_LL_UART_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) {
+    low_level_handle = hal_ll_uart_get_handle;
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address );
+
+    //------------------------------------------------
+    // @note: AVR microcontrollers do not utilize
+    // half stop bit and one and a half bit.
+    //------------------------------------------------
+    if (( HAL_LL_UART_STOP_BITS_HALF == stop_bit ) || ( HAL_LL_UART_STOP_BITS_ONE_AND_A_HALF == stop_bit )) {
+        return HAL_LL_UART_MODULE_ERROR;
+    }
+
+    low_level_handle->init_ll_state = false;
+
+    hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit;
+
+    hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local );
+
+    low_level_handle->init_ll_state = true;
+
+    return HAL_LL_UART_SUCCESS;
+}
+
+hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) {
+    low_level_handle = hal_ll_uart_get_handle;
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address );
+
+    low_level_handle->init_ll_state = false;
+
+    hal_ll_uart_hw_specifics_map_local->data_bit = data_bit;
+
+    hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local );
+
+    low_level_handle->init_ll_state = true;
+
+    return HAL_LL_UART_SUCCESS;
+}
+
+void hal_ll_uart_close( handle_t *handle ) {
+    low_level_handle = hal_ll_uart_get_handle;
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address );
+
+    if( NULL != low_level_handle->hal_ll_uart_handle ) {
+        hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false );
+
+        hal_ll_uart_irq_disable( handle, HAL_LL_UART_IRQ_RX );
+        hal_ll_uart_irq_disable( handle, HAL_LL_UART_IRQ_TX );
+
+        hal_ll_uart_clear_regs( hal_ll_uart_hw_specifics_map_local->base );
+
+        // Power-down appropriate UART module via Power Reduction Register (if available).
+        #if HAL_LL_POWER_REDUCTION
+        hal_ll_uart_power_reduction_enable( hal_ll_uart_hw_specifics_map_local->module_index, true );
+        #endif
+
+        hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC;
+        hal_ll_uart_hw_specifics_map_local->pins.rx_pin.pin_name = HAL_LL_PIN_NC;
+
+        hal_ll_uart_hw_specifics_map_local->baud_rate.baud = 115200UL;
+        hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0;
+
+        irq_handler = NULL;
+        objects[ hal_ll_uart_find_index( handle ) ] = NULL;
+
+        low_level_handle->hal_ll_uart_handle = NULL;
+        low_level_handle->hal_drv_uart_handle = NULL;
+
+        low_level_handle->init_ll_state = false;
+    }
+}
+
+void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ) {
+    irq_handler = handler;
+    objects[ hal_ll_uart_find_index( handle ) ] = obj;
+}
+
+void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) {
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address );
+
+    switch ( irq ) {
+        case HAL_LL_UART_IRQ_RX:
+            __HAL_LL_UART_ENABLE_IT( hal_ll_uart_hw_specifics_map_local->module_index, HAL_LL_UART_CTRLA_RXCINTLVL_SHIFT );
+            break;
+
+        case HAL_LL_UART_IRQ_TX:
+            __HAL_LL_UART_ENABLE_IT( hal_ll_uart_hw_specifics_map_local->module_index, HAL_LL_UART_CTRLA_TXCINTLVL_SHIFT );
+            break;
+
+        default:
+            break;
+    }
+
+}
+
+void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) {
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address );
+
+    switch ( irq ) {
+        case HAL_LL_UART_IRQ_RX:
+            __HAL_LL_UART_DISABLE_IT( hal_ll_uart_hw_specifics_map_local->module_index, HAL_LL_UART_CTRLA_RXCINTLVL_SHIFT );
+            break;
+
+        case HAL_LL_UART_IRQ_TX:
+            __HAL_LL_UART_DISABLE_IT( hal_ll_uart_hw_specifics_map_local->module_index, HAL_LL_UART_CTRLA_TXCINTLVL_SHIFT );
+            break;
+
+        default:
+            break;
+    }
+}
+
+void hal_ll_uart_write( handle_t *handle, uint8_t wr_data ) {
+    const hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_handle;
+    write_reg( hal_ll_hw_reg->dat, wr_data );
+}
+
+uint16_t hal_ll_uart_read( handle_t *handle ) {
+    const hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_handle;
+    return read_reg( hal_ll_hw_reg->dat );
+}
+
+// ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS
+/*!< @brief Link handler from HAL layer */
+void hal_uart_irq_handler( handle_t obj, hal_ll_uart_irq_t event );
+
+#if defined ( UART_MODULE_C0 )
+void UART0_RX_IRQHandler( void ) MIKROC_IV( HAL_LL_USARTC0_RXC_IVT_ADDRESS ) {
+    irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_C0 ) ], HAL_LL_UART_IRQ_RX );
+}
+
+void UART0_TX_IRQHandler( void ) MIKROC_IV( HAL_LL_USARTC0_TXC_IVT_ADDRESS ) {
+    if( hal_ll_uart_get_status_flags( hal_ll_uart_module_num( UART_MODULE_C0 )) & ( 1 <<  HAL_LL_UART_STATUS_DREIF_BIT )) {
+        irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_C0 ) ], HAL_LL_UART_IRQ_TX );
+        write_reg( hal_ll_uart_regs[ hal_ll_uart_module_num( UART_MODULE_C0 ) ].status, HAL_LL_UART_STATUS_TXCIF_BIT );
+    }
+}
+#endif
+
+#if defined ( UART_MODULE_C1 )
+void UART1_RX_IRQHandler( void ) MIKROC_IV( HAL_LL_USARTC1_RXC_IVT_ADDRESS ) {
+    irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_C1 ) ], HAL_LL_UART_IRQ_RX );
+}
+
+void UART1_TX_IRQHandler( void ) MIKROC_IV( HAL_LL_USARTC1_TXC_IVT_ADDRESS ) {
+    if( hal_ll_uart_get_status_flags( hal_ll_uart_module_num( UART_MODULE_C1 )) & ( 1 <<  HAL_LL_UART_STATUS_DREIF_BIT )) {
+        irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_C1 ) ], HAL_LL_UART_IRQ_TX );
+        write_reg( hal_ll_uart_regs[ hal_ll_uart_module_num( UART_MODULE_C1 ) ].status, HAL_LL_UART_STATUS_TXCIF_BIT );
+    }
+}
+#endif
+
+#if defined ( UART_MODULE_D0 )
+void UART2_RX_IRQHandler( void ) MIKROC_IV( HAL_LL_USARTD0_RXC_IVT_ADDRESS ) {
+    irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_D0 ) ], HAL_LL_UART_IRQ_RX );
+}
+
+void UART2_TX_IRQHandler( void ) MIKROC_IV( HAL_LL_USARTD0_TXC_IVT_ADDRESS ) {
+    if( hal_ll_uart_get_status_flags( hal_ll_uart_module_num( UART_MODULE_D0 )) & ( 1 <<  HAL_LL_UART_STATUS_DREIF_BIT )) {
+        irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_D0 ) ], HAL_LL_UART_IRQ_TX );
+        write_reg( hal_ll_uart_regs[ hal_ll_uart_module_num( UART_MODULE_D0 ) ].status, HAL_LL_UART_STATUS_TXCIF_BIT );
+    }
+}
+#endif
+
+#if defined ( UART_MODULE_D1 )
+void UART3_RX_IRQHandler( void ) MIKROC_IV( HAL_LL_USARTD1_RXC_IVT_ADDRESS ) {
+    irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_D1 ) ], HAL_LL_UART_IRQ_RX );
+}
+
+void UART3_TX_IRQHandler( void ) MIKROC_IV( HAL_LL_USARTD1_TXC_IVT_ADDRESS ) {
+    if( hal_ll_uart_get_status_flags( hal_ll_uart_module_num( UART_MODULE_D1 )) & ( 1 <<  HAL_LL_UART_STATUS_DREIF_BIT )) {
+        irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_D1 ) ], HAL_LL_UART_IRQ_TX );
+        write_reg( hal_ll_uart_regs[ hal_ll_uart_module_num( UART_MODULE_D1 ) ].status, HAL_LL_UART_STATUS_TXCIF_BIT );
+    }
+}
+#endif
+
+#if defined ( UART_MODULE_E0 )
+void UART4_RX_IRQHandler( void ) MIKROC_IV( HAL_LL_USARTE0_RXC_IVT_ADDRESS ) {
+    irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_E0 ) ], HAL_LL_UART_IRQ_RX );
+}
+
+void UART4_TX_IRQHandler( void ) MIKROC_IV( HAL_LL_USARTE0_TXC_IVT_ADDRESS ) {
+    if( hal_ll_uart_get_status_flags( hal_ll_uart_module_num( UART_MODULE_E0 )) & ( 1 <<  HAL_LL_UART_STATUS_DREIF_BIT )) {
+        irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_E0 ) ], HAL_LL_UART_IRQ_TX );
+        write_reg( hal_ll_uart_regs[ hal_ll_uart_module_num( UART_MODULE_E0 ) ].status, HAL_LL_UART_STATUS_TXCIF_BIT );
+    }
+}
+#endif
+
+#if defined ( UART_MODULE_E1 )
+void UART5_RX_IRQHandler( void ) MIKROC_IV( HAL_LL_USARTE1_RXC_IVT_ADDRESS ) {
+    irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_E1 ) ], HAL_LL_UART_IRQ_RX );
+}
+
+void UART5_TX_IRQHandler( void ) MIKROC_IV( HAL_LL_USARTE1_TXC_IVT_ADDRESS ) {
+    if( hal_ll_uart_get_status_flags( hal_ll_uart_module_num( UART_MODULE_E1 )) & ( 1 <<  HAL_LL_UART_STATUS_DREIF_BIT )) {
+        irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_E1 ) ], HAL_LL_UART_IRQ_TX );
+        write_reg( hal_ll_uart_regs[ hal_ll_uart_module_num( UART_MODULE_E1 ) ].status, HAL_LL_UART_STATUS_TXCIF_BIT );
+    }
+}
+#endif
+
+#if defined ( UART_MODULE_F0 )
+void UART6_RX_IRQHandler( void ) MIKROC_IV( HAL_LL_USARTF0_RXC_IVT_ADDRESS ) {
+    irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_F0 ) ], HAL_LL_UART_IRQ_RX );
+}
+
+void UART6_TX_IRQHandler( void ) MIKROC_IV( HAL_LL_USARTF0_TXC_IVT_ADDRESS ) {
+    if( hal_ll_uart_get_status_flags( hal_ll_uart_module_num( UART_MODULE_F0 )) & ( 1 <<  HAL_LL_UART_STATUS_DREIF_BIT )) {
+        irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_F0 ) ], HAL_LL_UART_IRQ_TX );
+        write_reg( hal_ll_uart_regs[ hal_ll_uart_module_num( UART_MODULE_F0 ) ].status, HAL_LL_UART_STATUS_TXCIF_BIT );
+    }
+}
+#endif
+
+#if defined ( UART_MODULE_F1 )
+void UART7_RX_IRQHandler( void ) MIKROC_IV( HAL_LL_USARTF1_RXC_IVT_ADDRESS ) {
+    irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_F1 ) ], HAL_LL_UART_IRQ_RX );
+}
+
+void UART7_TX_IRQHandler( void ) MIKROC_IV( HAL_LL_USARTF1_TXC_IVT_ADDRESS ) {
+    if( hal_ll_uart_get_status_flags( hal_ll_uart_module_num( UART_MODULE_F1 )) & ( 1 <<  HAL_LL_UART_STATUS_DREIF_BIT )) {
+        irq_handler( objects[ hal_ll_uart_module_num( UART_MODULE_F1 ) ], HAL_LL_UART_IRQ_TX );
+        write_reg( hal_ll_uart_regs[ hal_ll_uart_module_num( UART_MODULE_F1 ) ].status, HAL_LL_UART_STATUS_TXCIF_BIT );
+    }
+}
+#endif
+
+// ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS
+static uint8_t hal_ll_uart_find_index( handle_t *handle ) {
+    hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address );
+
+    if( HAL_LL_MODULE_ERROR != hal_ll_uart_hw_specifics_map_local->base->dat ) {
+        return hal_ll_uart_hw_specifics_map_local->module_index;
+    } else {
+        return NULL;
+    }
+}
+
+static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) {
+    static const uint8_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) );
+    static const uint8_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) );
+    uint8_t hal_ll_module_id = 0;
+    uint8_t index_counter = 0;
+    uint8_t tx_index;
+    uint8_t rx_index;
+
+    if ( ( HAL_LL_PIN_NC == tx_pin) || ( HAL_LL_PIN_NC == rx_pin) ) {
+        return HAL_LL_PIN_NC;
+    }
+
+    for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) {
+        if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) {
+            for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) {
+                if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) {
+                    if ( hal_ll_uart_tx_map[ tx_index ].module_index == hal_ll_uart_rx_map[ rx_index ].module_index ) {
+                        if ( hal_ll_uart_tx_map[ tx_index ].alternate == hal_ll_uart_rx_map[ rx_index ].alternate ) {
+                            // Get module number
+                            hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index;
+
+                            // Map pin names
+                            index_list[hal_ll_module_id]->pin_tx = tx_index;
+                            index_list[hal_ll_module_id]->pin_rx = rx_index;
+
+                            // Check if module is taken
+                            if ( NULL == handle_map[hal_ll_module_id]->hal_drv_uart_handle ) {
+                                return hal_ll_module_id;
+                            } else if ( UART_MODULE_COUNT == ++index_counter ) {
+                                return --index_counter;
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    if ( index_counter ) {
+        return hal_ll_module_id;
+    } else {
+        return HAL_LL_PIN_NC;
+    }
+}
+
+static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) {
+    uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_uart_handle_register_t ));
+    static uint8_t hal_ll_module_error = hal_ll_module_count;
+
+    while( hal_ll_module_count-- ) {
+        if ( hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[ hal_ll_module_count ].base) {
+            return &hal_ll_uart_hw_specifics_map[ hal_ll_module_count ];
+        }
+    }
+
+    return &hal_ll_uart_hw_specifics_map[hal_ll_module_error];
+}
+
+static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) {
+    hal_ll_uart_hw_specifics_map[ module_index ].pins.tx_pin.pin_name = hal_ll_uart_tx_map[ index_list[ module_index ]->pin_tx ].pin;
+    hal_ll_uart_hw_specifics_map[ module_index ].pins.rx_pin.pin_name = hal_ll_uart_rx_map[ index_list[ module_index ]->pin_rx ].pin;
+    hal_ll_uart_hw_specifics_map[ module_index ].alternate = hal_ll_uart_rx_map[ index_list[ module_index ]->pin_rx ].alternate;
+}
+
+static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) {
+    hal_ll_gpio_pin_t local_pin;
+    if (( HAL_LL_PIN_NC != map->pins.tx_pin.pin_name ) && ( HAL_LL_PIN_NC != map->pins.rx_pin.pin_name )) {
+        if ( hal_ll_state) {
+            hal_ll_gpio_configure_pin( &local_pin, map->pins.tx_pin.pin_name, HAL_LL_GPIO_DIGITAL_OUTPUT );
+            hal_ll_gpio_configure_pin( &local_pin, map->pins.rx_pin.pin_name, HAL_LL_GPIO_DIGITAL_INPUT );
+        } else {
+            hal_ll_gpio_configure_pin( &local_pin, map->pins.tx_pin.pin_name, HAL_LL_GPIO_DIGITAL_INPUT );
+            hal_ll_gpio_configure_pin( &local_pin, map->pins.rx_pin.pin_name, HAL_LL_GPIO_DIGITAL_INPUT );
+        }
+    }
+    #if ( HAL_LL_MODULE_REMAP == true )
+    if( true == map->alternate ) {
+        #ifdef UART_MODULE_C0
+        if( hal_ll_uart_module_num( UART_MODULE_C0 ) == map->module_index ) {
+            set_reg_bit( PORTC_REMAP_REG_ADDRESS, HAL_LL_USART0_REMAP_BIT );
+        }
+        #endif
+        #ifdef UART_MODULE_D0
+        if( hal_ll_uart_module_num( UART_MODULE_D0 ) == map->module_index ) {
+            set_reg_bit( PORTD_REMAP_REG_ADDRESS, HAL_LL_USART0_REMAP_BIT );
+        }
+        #endif
+        #ifdef UART_MODULE_E0
+        if( hal_ll_uart_module_num( UART_MODULE_E0 ) == map->module_index ) {
+            set_reg_bit( PORTE_REMAP_REG_ADDRESS, HAL_LL_USART0_REMAP_BIT );
+        }
+        #endif
+        #ifdef UART_MODULE_F0
+        if( hal_ll_uart_module_num( UART_MODULE_F0 ) == map->module_index ) {
+            set_reg_bit( PORTF_REMAP_REG_ADDRESS, HAL_LL_USART0_REMAP_BIT );
+        }
+        #endif
+    }
+    #endif
+}
+
+static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) {
+    const hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base );
+    static uint32_t peripheral_clock = Get_Fosc_kHz()*1000;
+    volatile int8_t bscale, i, baud_mul;
+    volatile int16_t bsel;
+    volatile float real_baud, baud_rate_error;
+
+    baud_mul = ( check_reg_bit( hal_ll_hw_reg->ctrlb, HAL_LL_UART_CTRLB_CLK2X_BIT )) ? HAL_LL_UART_BAUD_RATE_MUL_CLK2X : HAL_LL_UART_BAUD_RATE_MUL;
+
+    for( i = -7; i < 8; i++) {
+        if( i < 0 ) {
+            bsel =  ( pow( 2, i * (-1) ) * (( (float)peripheral_clock / ( map->baud_rate.baud * baud_mul )) - 1 ));
+            real_baud = (float)peripheral_clock / ( baud_mul*( pow( 2, i ) * bsel + 1 ));
+        } else {
+            bsel = pow( 2, i * (-1) ) * ( (float)peripheral_clock / ( map->baud_rate.baud * baud_mul )) - 1;
+            real_baud = peripheral_clock / (float)( pow( 2, i ) * baud_mul * ( bsel + 1 ));
+        }
+        if (( 4095 < bsel ) || ( 0 > bsel ) || ( 0 == bsel ) && ( 0 != i )) continue;
+        baud_rate_error = hal_ll_uart_get_baud_error( real_baud, map->baud_rate.baud );
+        if( (float)1.0 > baud_rate_error ) break;
+    }
+    bscale = i;
+    write_reg( hal_ll_hw_reg->baudctrla, bsel );
+    write_reg( hal_ll_hw_reg->baudctrlb, ( bsel >> 8 ) | ( bscale << 4 ));
+}
+
+static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) {
+    const hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base );
+
+    switch( map->data_bit ) {
+        // NOTE: HAL_LL_UART_DATA_BITS_5 and HAL_LL_UART_DATA_BITS_6 are not defined
+        /*
+        case HAL_LL_UART_DATA_BITS_5:
+            set_reg_bits( hal_ll_hw_reg->ctrlc, HAL_LL_UART_CHSIZE_5BIT );
+            break;
+        case HAL_LL_UART_DATA_BITS_6:
+            set_reg_bits( hal_ll_hw_reg->ctrlc, HAL_LL_UART_CHSIZE_6BIT );
+            break;
+        */
+        case HAL_LL_UART_DATA_BITS_7:
+            set_reg_bits( hal_ll_hw_reg->ctrlc, HAL_LL_UART_CHSIZE_7BIT );
+            break;
+        case HAL_LL_UART_DATA_BITS_8:
+            set_reg_bits( hal_ll_hw_reg->ctrlc, HAL_LL_UART_CHSIZE_8BIT );
+            break;
+        case HAL_LL_UART_DATA_BITS_9:
+            set_reg_bits( hal_ll_hw_reg->ctrlc, HAL_LL_UART_CHSIZE_9BIT );
+            break;
+
+        default:
+            break;
+    }
+}
+
+static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) {
+    const hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base );
+
+    switch( map->stop_bit ) {
+        case HAL_LL_UART_STOP_BITS_ONE:
+            set_reg_bits( hal_ll_hw_reg->ctrlc, HAL_LL_UART_SBMODE_ONE << HAL_LL_UART_SBMODE_SHIFT );
+            break;
+        case HAL_LL_UART_STOP_BITS_TWO:
+            set_reg_bits( hal_ll_hw_reg->ctrlc, HAL_LL_UART_SBMODE_TWO << HAL_LL_UART_SBMODE_SHIFT );
+            break;
+
+        default:
+            break;
+    }
+}
+
+static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) {
+    const hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base );
+
+    switch( map->parity ) {
+        case HAL_LL_UART_PARITY_NONE:
+            clear_reg_bits( hal_ll_hw_reg->ctrlc, HAL_LL_UART_PARITY_NONE << HAL_LL_UART_PMODE_SHIFT );
+            break;
+        case HAL_LL_UART_PARITY_EVEN:
+            set_reg_bits( hal_ll_hw_reg->ctrlc, HAL_LL_UART_PARITY_EVEN << HAL_LL_UART_PMODE_SHIFT );
+            break;
+        case HAL_LL_UART_PARITY_ODD:
+            set_reg_bits( hal_ll_hw_reg->ctrlc, HAL_LL_UART_PARITY_ODD << HAL_LL_UART_PMODE_SHIFT );
+            break;
+
+        default:
+            break;
+    }
+}
+
+static void hal_ll_uart_set_transmitter( const hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) {
+    switch ( pin_state )
+    {
+        case HAL_LL_UART_DISABLE:
+            clear_reg_bit( hal_ll_hw_reg->ctrlb, HAL_LL_UART_CTRLB_TXEN_BIT );
+            break;
+
+        case HAL_LL_UART_ENABLE:
+            set_reg_bit( hal_ll_hw_reg->ctrlb, HAL_LL_UART_CTRLB_TXEN_BIT );
+            break;
+
+        default:
+            break;
+    }
+}
+
+static void hal_ll_uart_set_receiver( const hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) {
+    switch ( pin_state )
+    {
+        case HAL_LL_UART_DISABLE:
+            clear_reg_bit( hal_ll_hw_reg->ctrlb, HAL_LL_UART_CTRLB_RXEN_BIT );
+            break;
+
+        case HAL_LL_UART_ENABLE:
+            set_reg_bit( hal_ll_hw_reg->ctrlb, HAL_LL_UART_CTRLB_RXEN_BIT );
+            break;
+
+        default:
+            break;
+    }
+}
+
+static void hal_ll_uart_power_reduction_enable( uint8_t module_num, bool hal_ll_state ) {
+
+    switch ( module_num ) {
+        #ifdef UART_MODULE_C0
+        case hal_ll_uart_module_num(UART_MODULE_C0):
+            if( true == hal_ll_state ) {
+                set_reg_bit( HAL_LL_PRPC_REG_ADDRESS, HAL_LL_PRPn_USART0_MODULE_ENABLE );
+            } else {
+                clear_reg_bit( HAL_LL_PRPC_REG_ADDRESS, HAL_LL_PRPn_USART0_MODULE_ENABLE );
+            }
+            break;
+        #endif
+        #ifdef UART_MODULE_C1
+        case hal_ll_uart_module_num(UART_MODULE_C1):
+            if( true == hal_ll_state ) {
+                set_reg_bit( HAL_LL_PRPC_REG_ADDRESS, HAL_LL_PRPn_USART1_MODULE_ENABLE );
+            } else {
+                clear_reg_bit( HAL_LL_PRPC_REG_ADDRESS, HAL_LL_PRPn_USART1_MODULE_ENABLE );
+            }
+            break;
+        #endif
+        #ifdef UART_MODULE_D0
+        case hal_ll_uart_module_num(UART_MODULE_D0):
+            if( true == hal_ll_state ) {
+                set_reg_bit( HAL_LL_PRPD_REG_ADDRESS, HAL_LL_PRPn_USART0_MODULE_ENABLE );
+            } else {
+                clear_reg_bit( HAL_LL_PRPD_REG_ADDRESS, HAL_LL_PRPn_USART0_MODULE_ENABLE );
+            }
+            break;
+        #endif
+        #ifdef UART_MODULE_D1
+        case hal_ll_uart_module_num(UART_MODULE_D1):
+            if( true == hal_ll_state ) {
+                set_reg_bit( HAL_LL_PRPD_REG_ADDRESS, HAL_LL_PRPn_USART1_MODULE_ENABLE );
+            } else {
+                clear_reg_bit( HAL_LL_PRPD_REG_ADDRESS, HAL_LL_PRPn_USART1_MODULE_ENABLE );
+            }
+            break;
+        #endif
+        #ifdef UART_MODULE_E0
+        case hal_ll_uart_module_num(UART_MODULE_E0):
+            if( true == hal_ll_state ) {
+                set_reg_bit( HAL_LL_PRPE_REG_ADDRESS, HAL_LL_PRPn_USART0_MODULE_ENABLE );
+            } else {
+                clear_reg_bit( HAL_LL_PRPE_REG_ADDRESS, HAL_LL_PRPn_USART0_MODULE_ENABLE );
+            }
+            break;
+        #endif
+        #ifdef UART_MODULE_E1
+        case hal_ll_uart_module_num(UART_MODULE_E1):
+            if( true == hal_ll_state ) {
+                set_reg_bit( HAL_LL_PRPE_REG_ADDRESS, HAL_LL_PRPn_USART1_MODULE_ENABLE );
+            } else {
+                clear_reg_bit( HAL_LL_PRPE_REG_ADDRESS, HAL_LL_PRPn_USART1_MODULE_ENABLE );
+            }
+            break;
+        #endif
+        #ifdef UART_MODULE_F0
+        case hal_ll_uart_module_num(UART_MODULE_F0):
+            if( true == hal_ll_state ) {
+                set_reg_bit( HAL_LL_PRPF_REG_ADDRESS, HAL_LL_PRPn_USART0_MODULE_ENABLE );
+            } else {
+                clear_reg_bit( HAL_LL_PRPF_REG_ADDRESS, HAL_LL_PRPn_USART0_MODULE_ENABLE );
+            }
+            break;
+        #endif
+        #ifdef UART_MODULE_F1
+        case hal_ll_uart_module_num(UART_MODULE_F1):
+            if( true == hal_ll_state ) {
+                set_reg_bit( HAL_LL_PRPF_REG_ADDRESS, HAL_LL_PRPn_USART1_MODULE_ENABLE );
+            } else {
+                clear_reg_bit( HAL_LL_PRPF_REG_ADDRESS, HAL_LL_PRPn_USART1_MODULE_ENABLE );
+            }
+            break;
+        #endif
+    }
+}
+
+static void hal_ll_uart_clear_regs( const hal_ll_uart_base_handle_t *hal_ll_hw_reg ) {
+    clear_reg( hal_ll_hw_reg->ctrla );
+    clear_reg( hal_ll_hw_reg->ctrlc );
+}
+
+static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) {
+    const hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base );
+
+    hal_ll_uart_clear_regs( map->base );
+
+    // Power-down appropriate UART module via Power Reduction Register (if available).
+    #if HAL_LL_POWER_REDUCTION
+    hal_ll_uart_power_reduction_enable( map->module_index, false );
+    #endif
+
+    hal_ll_uart_set_baud_bare_metal( map );
+
+    hal_ll_uart_set_parity_bare_metal( map );
+
+    hal_ll_uart_set_data_bits_bare_metal( map );
+
+    hal_ll_uart_set_stop_bits_bare_metal( map );
+
+    write_reg( HAL_LL_PMIC_CTRL_REG_ADDRESS, HAL_LL_PMIC_CTRL_HILVLEN | HAL_LL_PMIC_CTRL_MEDLVLEN | HAL_LL_PMIC_CTRL_LOLVLEN );
+
+    hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE );
+
+    hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE );
+
+    /*
+     * In order for UART Transmit interrupt to be triggered, initial dummy data write is required.
+     * According to documentation:
+     * "Data transfer is initiated by writing to the DATA register.
+     *  This is the case for both sending and receiving data, since the transmitter controls the transfer clock."
+     */
+    write_reg( hal_ll_hw_reg->dat, HAL_LL_UART_TRIGGER_INTERRUPT );
+}
+
+static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) {
+    hal_ll_uart_hw_init( map );
+}
+
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/CMakeLists.txt b/targets/avr_8bit/mikroe/common/CMakeLists.txt
new file mode 100644
index 000000000..74d9cbd21
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/CMakeLists.txt
@@ -0,0 +1,39 @@
+
+mikrosdk_add_interface_library(lib_hal_ll_common MikroSDK.HalLowLevelCommon
+    include/hal_ll_bit_control.h
+    include/mcu_definitions/${MCU_NAME}/mcu_definitions.h
+    include/common_macros.h
+    include/assembly.h
+)
+
+target_link_libraries(lib_hal_ll_common
+INTERFACE
+    MikroC.Core
+)
+target_include_directories(lib_hal_ll_common
+INTERFACE
+$<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/include>
+$<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/include/mcu_definitions/${MCU_NAME}>
+$<INSTALL_INTERFACE:include>
+)
+
+mikrosdk_install(MikroSDK.HalLowLevelCommon)
+
+install(
+FILES
+    include/hal_ll_bit_control.h
+    include/common_macros.h
+    include/assembly.h
+DESTINATION
+    ${CMAKE_INSTALL_PREFIX}/include/hal_ll_port
+)
+
+string(TOLOWER ${MCU_NAME} MEMAKE_MCU_NAME_LOWER)
+
+install(
+FILES
+    include/mcu_definitions/${MCU_NAME}/mcu_definitions.h
+    include/common_macros.h
+DESTINATION
+    ${CMAKE_INSTALL_PREFIX}/include/${MEMAKE_MCU_NAME_LOWER}
+)
diff --git a/targets/avr_8bit/mikroe/common/include/assembly.h b/targets/avr_8bit/mikroe/common/include/assembly.h
new file mode 100644
index 000000000..3b00416c7
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/assembly.h
@@ -0,0 +1,62 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_assembly.h
+ * @brief Macros used for bitwise register manipulation.
+ */
+
+#ifndef _HAL_LL_ASSEMBLY_H_
+#define _HAL_LL_ASSEMBLY_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#ifdef __GNUC__
+#define assembly(_instruction) asm(#_instruction)
+#elif defined(__MIKROC__)
+#define assembly(_instruction) asm _instruction
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_ASSEMBLY_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/common_macros.h b/targets/avr_8bit/mikroe/common/include/common_macros.h
new file mode 100644
index 000000000..865d1aa18
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/common_macros.h
@@ -0,0 +1,72 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  common_macros.h
+ * @brief Macros (common per architecture type).
+ */
+
+#ifndef _COMMON_MACROS_H_
+#define _COMMON_MACROS_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#ifdef __MIKROC_AI__
+    #define __weak __attribute__((weak))
+#else
+    #define __weak
+#endif
+
+// One Wire
+#ifdef MACRO_USAGE_ONE_WIRE
+#define ONE_WIRE_CMD_ROM_READ (0x33)
+#define ONE_WIRE_CMD_ROM_SKIP (0xCC)
+#define ONE_WIRE_CMD_ROM_MATCH (0x55)
+#define ONE_WIRE_CMD_ROM_SEARCH (0xF0)
+#define ONE_WIRE_CMD_ROM_READ_LEGACY (0x0F)
+#endif
+// EOF One Wire
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _COMMON_MACROS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/hal_ll_bit_control.h b/targets/avr_8bit/mikroe/common/include/hal_ll_bit_control.h
new file mode 100644
index 000000000..afcffa41d
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/hal_ll_bit_control.h
@@ -0,0 +1,155 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_bit_control.h
+ * @brief Macros used for bitwise register manipulation.
+ */
+
+#ifndef _HAL_LL_BIT_CONTROL_H_
+#define _HAL_LL_BIT_CONTROL_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include <stdint.h>
+
+/*!< @brief Mask used for register clearing */
+#define HAL_LL_CLEAR 0x00U
+
+/*!< @brief Macro */
+#define selected_reg(__reg) (*(uint8_t *)__reg)
+
+/*!< @brief Low nibble macros */
+#define HAL_LL_NIBBLE_LOW_8BIT (0xF)
+#define HAL_LL_NIBBLE_LOW_16BIT (0xFFU)
+#define HAL_LL_NIBBLE_LOW_32BIT (0xFFFFUL)
+
+/*!< @brief High nibble macros */
+#define HAL_LL_NIBBLE_HIGH_8BIT (0xF0)
+#define HAL_LL_NIBBLE_HIGH_16BIT (0xFF00U)
+#define HAL_LL_NIBBLE_HIGH_32BIT (0xFFFF0000UL)
+
+/**
+ * @brief Sets one bit in a register.
+ *
+ * @param[in] reg  - register address.
+ * @param[in] _bit - bit number (0-7).
+ */
+#define set_reg_bit(reg,_bit) (selected_reg(reg) |= ((1U)<<(_bit)))
+
+/**
+ * @brief Sets bits specified by bit_mask
+ *        in the specified register.
+ *
+ * @param[in] reg  - register address
+ * @param[in] bit_mask - bit mask.
+ */
+#define set_reg_bits(reg,bit_mask) (selected_reg(reg) |= (bit_mask))
+
+/**
+ * @brief Clears one bit in a register.
+ *
+ * @param[in] reg  - register address.
+ * @param[in] _bit - bit number (0-7).
+ */
+#define clear_reg_bit(reg,_bit) (selected_reg(reg) &= ~((1U)<<(_bit)))
+
+/**
+ * @brief Clears bits specified by bit_mask
+ *        in the specified register.
+ *
+ * @param[in] reg  - register address
+ * @param[in] bit_mask - bit mask.
+ */
+#define clear_reg_bits(reg,bit_mask) (selected_reg(reg) &= ~(bit_mask))
+
+/**
+ * @brief Returns value of one bit
+ *        in a register.
+ *
+ * @param[in] reg  - register address.
+ * @param[in] _bit - bit number (0-7).
+ * @return Register(reg) bit value.
+ */
+#define check_reg_bit(reg,_bit) (selected_reg(reg) & ((1U)<<(_bit)))
+
+/**
+ * @brief Writes specified value to
+ *        specified register.
+ *
+ * @param[in] reg  - register address.
+ * @param[in] _val - Value to be written.
+ */
+#define write_reg(reg,_val) (selected_reg(reg) = (_val))
+
+/**
+ * @brief Returns value stored
+ *        in a register.
+ *
+ * @param[in] reg  - register address.
+ *
+ * @return Register(reg) value.
+ */
+#define read_reg(reg) (selected_reg(reg))
+
+/**
+ * @brief Returns value of specified bit
+ *        mask from a register.
+ *
+ * @param[in] reg  - register address
+ * @param[in] bit_mask - bit mask.
+ *
+ * @return Register(reg) bits value.
+ */
+#define read_reg_bits(reg,bit_mask) (selected_reg(reg) & (bit_mask))
+
+/**
+ * @brief Clears all bits in a register.
+ *
+ * @param[in] reg  - register address
+ */
+#define clear_reg(reg) write_reg(reg, HAL_LL_CLEAR)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_BIT_CONTROL_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/AT90USB1286/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/AT90USB1286/mcu_definitions.h
new file mode 100644
index 000000000..7fe81235b
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/AT90USB1286/mcu_definitions.h
@@ -0,0 +1,267 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PD0
+#define TWI0_SDA_PD1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART1_RX_PD2
+#define USART1_TX_PD3
+
+#define UART_MODULE_1 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_PRR1_REG_ADDRESS (0x65)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART1_RX_IVT (25)
+#define HAL_LL_USART1_UDRE_IVT (26)
+#define HAL_LL_USART1_TX_IVT (27)
+// IVT ADDRESSES
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x32)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x36)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/AT90USB1287/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/AT90USB1287/mcu_definitions.h
new file mode 100644
index 000000000..7fe81235b
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/AT90USB1287/mcu_definitions.h
@@ -0,0 +1,267 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PD0
+#define TWI0_SDA_PD1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART1_RX_PD2
+#define USART1_TX_PD3
+
+#define UART_MODULE_1 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_PRR1_REG_ADDRESS (0x65)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART1_RX_IVT (25)
+#define HAL_LL_USART1_UDRE_IVT (26)
+#define HAL_LL_USART1_TX_IVT (27)
+// IVT ADDRESSES
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x32)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x36)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/AT90USB646/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/AT90USB646/mcu_definitions.h
new file mode 100644
index 000000000..7fe81235b
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/AT90USB646/mcu_definitions.h
@@ -0,0 +1,267 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PD0
+#define TWI0_SDA_PD1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART1_RX_PD2
+#define USART1_TX_PD3
+
+#define UART_MODULE_1 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_PRR1_REG_ADDRESS (0x65)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART1_RX_IVT (25)
+#define HAL_LL_USART1_UDRE_IVT (26)
+#define HAL_LL_USART1_TX_IVT (27)
+// IVT ADDRESSES
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x32)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x36)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/AT90USB647/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/AT90USB647/mcu_definitions.h
new file mode 100644
index 000000000..7fe81235b
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/AT90USB647/mcu_definitions.h
@@ -0,0 +1,267 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PD0
+#define TWI0_SDA_PD1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART1_RX_PD2
+#define USART1_TX_PD3
+
+#define UART_MODULE_1 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_PRR1_REG_ADDRESS (0x65)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART1_RX_IVT (25)
+#define HAL_LL_USART1_UDRE_IVT (26)
+#define HAL_LL_USART1_TX_IVT (27)
+// IVT ADDRESSES
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x32)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x36)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA128/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA128/mcu_definitions.h
new file mode 100644
index 000000000..3aeea19b4
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA128/mcu_definitions.h
@@ -0,0 +1,298 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x24)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x25)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x24)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x26)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x27)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PD0
+#define TWI0_SDA_PD1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0x70)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0x71)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0x72)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0x73)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0x74)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0x29)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0x2A)
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0x2B)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0x2C)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0x90)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0x95)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0x98)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0x99)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0x9A)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0x9B)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0x9C)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0x9D)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x2D)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x2E)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x2F)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB4_CH_NONE
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM1_PB7_CH_C
+#define TIM2_PB7_CH_NONE
+#define TIM3_PE3_CH_A
+#define TIM3_PE4_CH_B
+#define TIM3_PE5_CH_C
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0x43)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0x44)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0x45)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x46)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x49)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x48)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x4b)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x4A)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x4d)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x4C)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x4E)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x4F)
+#define HAL_LL_TIM0_ASSR_REG_ADDRESS (0x50)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x51)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x52)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x53)
+#define HAL_LL_TIM1_OCR1CH_REG_ADDRESS (0x79)
+#define HAL_LL_TIM1_OCR1CL_REG_ADDRESS (0x78)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x7A)
+#define HAL_LL_TIM3_ICR3_REG_ADDRESS (0x80)
+#define HAL_LL_TIM3_OCR3CH_REG_ADDRESS (0x83)
+#define HAL_LL_TIM3_OCR3CL_REG_ADDRESS (0x82)
+#define HAL_LL_TIM3_OCR3BH_REG_ADDRESS (0x85)
+#define HAL_LL_TIM3_OCR3BL_REG_ADDRESS (0x84)
+#define HAL_LL_TIM3_OCR3AH_REG_ADDRESS (0x87)
+#define HAL_LL_TIM3_OCR3AL_REG_ADDRESS (0x86)
+#define HAL_LL_TIM3_TCNT3H_REG_ADDRESS (0x89)
+#define HAL_LL_TIM3_TCNT3L_REG_ADDRESS (0x88)
+#define HAL_LL_TIM3_TCCR3B_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM3_TCCR3A_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM3_TCCR3C_REG_ADDRESS (0x8C)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINF_REG_ADDRESS (0x20)
+#define PINE_REG_ADDRESS (0x21)
+#define DDRE_REG_ADDRESS (0x22)
+#define PORTE_REG_ADDRESS (0x23)
+#define PIND_REG_ADDRESS (0x30)
+#define DDRD_REG_ADDRESS (0x31)
+#define PORTD_REG_ADDRESS (0x32)
+#define PINC_REG_ADDRESS (0x33)
+#define DDRC_REG_ADDRESS (0x34)
+#define PORTC_REG_ADDRESS (0x35)
+#define PINB_REG_ADDRESS (0x36)
+#define DDRB_REG_ADDRESS (0x37)
+#define PORTB_REG_ADDRESS (0x38)
+#define PINA_REG_ADDRESS (0x39)
+#define DDRA_REG_ADDRESS (0x3A)
+#define PORTA_REG_ADDRESS (0x3B)
+#define DDRF_REG_ADDRESS (0x61)
+#define PORTF_REG_ADDRESS (0x62)
+#define PING_REG_ADDRESS (0x63)
+#define DDRG_REG_ADDRESS (0x64)
+#define PORTG_REG_ADDRESS (0x65)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_POWER_REDUCTION (false)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (18)
+#define HAL_LL_USART0_UDRE_IVT (19)
+#define HAL_LL_USART0_TX_IVT (20)
+#define HAL_LL_USART1_RX_IVT (30)
+#define HAL_LL_USART1_UDRE_IVT (31)
+#define HAL_LL_USART1_TX_IVT (32)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x24)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x26)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x3C)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x3E)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x40)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA1280/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA1280/mcu_definitions.h
new file mode 100644
index 000000000..e064c75ac
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA1280/mcu_definitions.h
@@ -0,0 +1,442 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+#define ADC0_PK0_CH8
+#define ADC0_PK1_CH9
+#define ADC0_PK2_CH10
+#define ADC0_PK3_CH11
+#define ADC0_PK4_CH12
+#define ADC0_PK5_CH13
+#define ADC0_PK6_CH14
+#define ADC0_PK7_CH15
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (16)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PD0
+#define TWI0_SDA_PD1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+#define USART2_RXD_PH0
+#define USART2_TXD_PH1
+#define USART3_RXD_PJ0
+#define USART3_TXD_PJ1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_2 (3)
+#define UART_MODULE_3 (4)
+#define UART_MODULE_COUNT (4)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+#define HAL_LL_USART2_UCSR2A_REG_ADDRESS (0xD0)
+#define HAL_LL_USART2_UCSR2B_REG_ADDRESS (0xD1)
+#define HAL_LL_USART2_UCSR2C_REG_ADDRESS (0xD2)
+#define HAL_LL_USART2_UBRR2L_REG_ADDRESS (0xD4)
+#define HAL_LL_USART2_UBRR2H_REG_ADDRESS (0xD5)
+#define HAL_LL_USART2_UBRR2_REG_ADDRESS (0xD4)
+#define HAL_LL_USART2_UDR2_REG_ADDRESS (0xD6)
+#define HAL_LL_USART3_UCSR3A_REG_ADDRESS (0x130)
+#define HAL_LL_USART3_UCSR3B_REG_ADDRESS (0x131)
+#define HAL_LL_USART3_UCSR3C_REG_ADDRESS (0x132)
+#define HAL_LL_USART3_UBRR3L_REG_ADDRESS (0x134)
+#define HAL_LL_USART3_UBRR3H_REG_ADDRESS (0x135)
+#define HAL_LL_USART3_UBRR3_REG_ADDRESS (0x134)
+#define HAL_LL_USART3_UDR3_REG_ADDRESS (0x136)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB7_CH_A
+#define TIM0_PG5_CH_B
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM1_PB7_CH_C
+#define TIM2_PB4_CH_A
+#define TIM2_PH6_CH_B
+#define TIM3_PE3_CH_A
+#define TIM3_PE4_CH_B
+#define TIM3_PE5_CH_C
+#define TIM4_PH3_CH_A
+#define TIM4_PH4_CH_B
+#define TIM4_PH5_CH_C
+#define TIM5_PL3_CH_A
+#define TIM5_PL4_CH_B
+#define TIM5_PL5_CH_C
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_4 (5)
+#define TIM_MODULE_5 (6)
+#define TIM_MODULE_COUNT (6)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM3_TIFR3_REG_ADDRESS (0x38)
+#define HAL_LL_TIM4_TIFR4_REG_ADDRESS (0x39)
+#define HAL_LL_TIM5_TIFR5_REG_ADDRESS (0x3A)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM3_TIMSK3_REG_ADDRESS (0x71)
+#define HAL_LL_TIM4_TIMSK4_REG_ADDRESS (0x72)
+#define HAL_LL_TIM5_TIMSK5_REG_ADDRESS (0x73)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM1_OCR1CH_REG_ADDRESS (0x8d)
+#define HAL_LL_TIM1_OCR1CL_REG_ADDRESS (0x8C)
+#define HAL_LL_TIM3_TCCR3A_REG_ADDRESS (0x90)
+#define HAL_LL_TIM3_TCCR3B_REG_ADDRESS (0x91)
+#define HAL_LL_TIM3_TCCR3C_REG_ADDRESS (0x92)
+#define HAL_LL_TIM3_TCNT3H_REG_ADDRESS (0x95)
+#define HAL_LL_TIM3_TCNT3L_REG_ADDRESS (0x94)
+#define HAL_LL_TIM3_ICR3_REG_ADDRESS (0x96)
+#define HAL_LL_TIM3_OCR3AH_REG_ADDRESS (0x99)
+#define HAL_LL_TIM3_OCR3AL_REG_ADDRESS (0x98)
+#define HAL_LL_TIM3_OCR3BH_REG_ADDRESS (0x9b)
+#define HAL_LL_TIM3_OCR3BL_REG_ADDRESS (0x9A)
+#define HAL_LL_TIM3_OCR3CH_REG_ADDRESS (0x9d)
+#define HAL_LL_TIM3_OCR3CL_REG_ADDRESS (0x9C)
+#define HAL_LL_TIM4_TCCR4A_REG_ADDRESS (0xA0)
+#define HAL_LL_TIM4_TCCR4B_REG_ADDRESS (0xA1)
+#define HAL_LL_TIM4_TCCR4C_REG_ADDRESS (0xA2)
+#define HAL_LL_TIM4_TCNT4H_REG_ADDRESS (0xa5)
+#define HAL_LL_TIM4_TCNT4L_REG_ADDRESS (0xA4)
+#define HAL_LL_TIM4_ICR4_REG_ADDRESS (0xA6)
+#define HAL_LL_TIM4_OCR4AH_REG_ADDRESS (0xa9)
+#define HAL_LL_TIM4_OCR4AL_REG_ADDRESS (0xA8)
+#define HAL_LL_TIM4_OCR4BH_REG_ADDRESS (0xab)
+#define HAL_LL_TIM4_OCR4BL_REG_ADDRESS (0xAA)
+#define HAL_LL_TIM4_OCR4CH_REG_ADDRESS (0xad)
+#define HAL_LL_TIM4_OCR4CL_REG_ADDRESS (0xAC)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+#define HAL_LL_TIM5_TCCR5A_REG_ADDRESS (0x120)
+#define HAL_LL_TIM5_TCCR5B_REG_ADDRESS (0x121)
+#define HAL_LL_TIM5_TCCR5C_REG_ADDRESS (0x122)
+#define HAL_LL_TIM5_TCNT5H_REG_ADDRESS (0x125)
+#define HAL_LL_TIM5_TCNT5L_REG_ADDRESS (0x124)
+#define HAL_LL_TIM5_ICR5_REG_ADDRESS (0x126)
+#define HAL_LL_TIM5_OCR5AH_REG_ADDRESS (0x129)
+#define HAL_LL_TIM5_OCR5AL_REG_ADDRESS (0x128)
+#define HAL_LL_TIM5_OCR5BH_REG_ADDRESS (0x12b)
+#define HAL_LL_TIM5_OCR5BL_REG_ADDRESS (0x12A)
+#define HAL_LL_TIM5_OCR5CH_REG_ADDRESS (0x12d)
+#define HAL_LL_TIM5_OCR5CL_REG_ADDRESS (0x12C)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+#define __PK0_CN
+#define __PK1_CN
+#define __PK2_CN
+#define __PK3_CN
+#define __PK4_CN
+#define __PK5_CN
+#define __PK6_CN
+#define __PK7_CN
+#define __PL0_CN
+#define __PL1_CN
+#define __PL2_CN
+#define __PL3_CN
+#define __PL4_CN
+#define __PL5_CN
+#define __PL6_CN
+#define __PL7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+#define __PORT_K_CN
+#define __PORT_L_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (11)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+#define PINH_REG_ADDRESS (0x100)
+#define DDRH_REG_ADDRESS (0x101)
+#define PORTH_REG_ADDRESS (0x102)
+#define PINJ_REG_ADDRESS (0x103)
+#define DDRJ_REG_ADDRESS (0x104)
+#define PORTJ_REG_ADDRESS (0x105)
+#define PINK_REG_ADDRESS (0x106)
+#define DDRK_REG_ADDRESS (0x107)
+#define PORTK_REG_ADDRESS (0x108)
+#define PINL_REG_ADDRESS (0x109)
+#define DDRL_REG_ADDRESS (0x10A)
+#define PORTL_REG_ADDRESS (0x10B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_PRR1_REG_ADDRESS (0x65)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (25)
+#define HAL_LL_USART0_UDRE_IVT (26)
+#define HAL_LL_USART0_TX_IVT (27)
+#define HAL_LL_USART1_RX_IVT (36)
+#define HAL_LL_USART1_UDRE_IVT (37)
+#define HAL_LL_USART1_TX_IVT (38)
+#define HAL_LL_USART2_RX_IVT (51)
+#define HAL_LL_USART2_UDRE_IVT (52)
+#define HAL_LL_USART2_TX_IVT (53)
+#define HAL_LL_USART3_RX_IVT (54)
+#define HAL_LL_USART3_UDRE_IVT (55)
+#define HAL_LL_USART3_TX_IVT (56)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x32)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x36)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x48)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x4A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x4C)
+#define HAL_LL_USART2_RX_IVT_ADDRESS (0x66)
+#define HAL_LL_USART2_UDRE_IVT_ADDRESS (0x68)
+#define HAL_LL_USART2_TX_IVT_ADDRESS (0x6A)
+#define HAL_LL_USART3_RX_IVT_ADDRESS (0x6C)
+#define HAL_LL_USART3_UDRE_IVT_ADDRESS (0x6E)
+#define HAL_LL_USART3_TX_IVT_ADDRESS (0x70)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA1281/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA1281/mcu_definitions.h
new file mode 100644
index 000000000..81f03d759
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA1281/mcu_definitions.h
@@ -0,0 +1,357 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PD0
+#define TWI0_SDA_PD1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB7_CH_A
+#define TIM0_PG5_CH_B
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM1_PB7_CH_C
+#define TIM2_PB4_CH_A
+#define TIM3_PE3_CH_A
+#define TIM3_PE4_CH_B
+#define TIM3_PE5_CH_C
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM3_TIFR3_REG_ADDRESS (0x38)
+#define HAL_LL_TIM4_TIFR4_REG_ADDRESS (0x39)
+#define HAL_LL_TIM5_TIFR5_REG_ADDRESS (0x3A)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM3_TIMSK3_REG_ADDRESS (0x71)
+#define HAL_LL_TIM4_TIMSK4_REG_ADDRESS (0x72)
+#define HAL_LL_TIM5_TIMSK5_REG_ADDRESS (0x73)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM1_OCR1CH_REG_ADDRESS (0x8d)
+#define HAL_LL_TIM1_OCR1CL_REG_ADDRESS (0x8C)
+#define HAL_LL_TIM3_TCCR3A_REG_ADDRESS (0x90)
+#define HAL_LL_TIM3_TCCR3B_REG_ADDRESS (0x91)
+#define HAL_LL_TIM3_TCCR3C_REG_ADDRESS (0x92)
+#define HAL_LL_TIM3_TCNT3H_REG_ADDRESS (0x95)
+#define HAL_LL_TIM3_TCNT3L_REG_ADDRESS (0x94)
+#define HAL_LL_TIM3_ICR3_REG_ADDRESS (0x96)
+#define HAL_LL_TIM3_OCR3AH_REG_ADDRESS (0x99)
+#define HAL_LL_TIM3_OCR3AL_REG_ADDRESS (0x98)
+#define HAL_LL_TIM3_OCR3BH_REG_ADDRESS (0x9b)
+#define HAL_LL_TIM3_OCR3BL_REG_ADDRESS (0x9A)
+#define HAL_LL_TIM3_OCR3CH_REG_ADDRESS (0x9d)
+#define HAL_LL_TIM3_OCR3CL_REG_ADDRESS (0x9C)
+#define HAL_LL_TIM4_TCCR4A_REG_ADDRESS (0xA0)
+#define HAL_LL_TIM4_TCCR4B_REG_ADDRESS (0xA1)
+#define HAL_LL_TIM4_TCCR4C_REG_ADDRESS (0xA2)
+#define HAL_LL_TIM4_TCNT4H_REG_ADDRESS (0xa5)
+#define HAL_LL_TIM4_TCNT4L_REG_ADDRESS (0xA4)
+#define HAL_LL_TIM4_ICR4_REG_ADDRESS (0xA6)
+#define HAL_LL_TIM4_OCR4AH_REG_ADDRESS (0xa9)
+#define HAL_LL_TIM4_OCR4AL_REG_ADDRESS (0xA8)
+#define HAL_LL_TIM4_OCR4BH_REG_ADDRESS (0xab)
+#define HAL_LL_TIM4_OCR4BL_REG_ADDRESS (0xAA)
+#define HAL_LL_TIM4_OCR4CH_REG_ADDRESS (0xad)
+#define HAL_LL_TIM4_OCR4CL_REG_ADDRESS (0xAC)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+#define HAL_LL_TIM5_TCCR5A_REG_ADDRESS (0x120)
+#define HAL_LL_TIM5_TCCR5B_REG_ADDRESS (0x121)
+#define HAL_LL_TIM5_TCCR5C_REG_ADDRESS (0x122)
+#define HAL_LL_TIM5_TCNT5H_REG_ADDRESS (0x125)
+#define HAL_LL_TIM5_TCNT5L_REG_ADDRESS (0x124)
+#define HAL_LL_TIM5_ICR5_REG_ADDRESS (0x126)
+#define HAL_LL_TIM5_OCR5AH_REG_ADDRESS (0x129)
+#define HAL_LL_TIM5_OCR5AL_REG_ADDRESS (0x128)
+#define HAL_LL_TIM5_OCR5BH_REG_ADDRESS (0x12b)
+#define HAL_LL_TIM5_OCR5BL_REG_ADDRESS (0x12A)
+#define HAL_LL_TIM5_OCR5CH_REG_ADDRESS (0x12d)
+#define HAL_LL_TIM5_OCR5CL_REG_ADDRESS (0x12C)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_PRR1_REG_ADDRESS (0x65)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (25)
+#define HAL_LL_USART0_UDRE_IVT (26)
+#define HAL_LL_USART0_TX_IVT (27)
+#define HAL_LL_USART1_RX_IVT (36)
+#define HAL_LL_USART1_UDRE_IVT (37)
+#define HAL_LL_USART1_TX_IVT (38)
+#define HAL_LL_USART2_RX_IVT (51)
+#define HAL_LL_USART2_UDRE_IVT (52)
+#define HAL_LL_USART2_TX_IVT (53)
+#define HAL_LL_USART3_RX_IVT (54)
+#define HAL_LL_USART3_UDRE_IVT (55)
+#define HAL_LL_USART3_TX_IVT (56)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x32)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x36)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x48)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x4A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x4C)
+#define HAL_LL_USART2_RX_IVT_ADDRESS (0x66)
+#define HAL_LL_USART2_UDRE_IVT_ADDRESS (0x68)
+#define HAL_LL_USART2_TX_IVT_ADDRESS (0x6A)
+#define HAL_LL_USART3_RX_IVT_ADDRESS (0x6C)
+#define HAL_LL_USART3_UDRE_IVT_ADDRESS (0x6E)
+#define HAL_LL_USART3_TX_IVT_ADDRESS (0x70)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA1284/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA1284/mcu_definitions.h
new file mode 100644
index 000000000..0d6c9932a
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA1284/mcu_definitions.h
@@ -0,0 +1,278 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC0
+#define TWI0_SDA_PC1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB6
+#define SPI0_MOSI_PB5
+#define SPI0_SCK_PB7
+#define SPI0_SS_PB4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB3_CH_A
+#define TIM0_PB4_CH_B
+#define TIM1_PD4_CH_B
+#define TIM1_PD5_CH_A
+#define TIM2_PD6_CH_B
+#define TIM2_PD7_CH_A
+#define TIM3_PB6_CH_A
+#define TIM3_PB7_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM3_TIFR3_REG_ADDRESS (0x38)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM3_TIMSK3_REG_ADDRESS (0x71)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM3_TCCR3A_REG_ADDRESS (0x90)
+#define HAL_LL_TIM3_TCCR3B_REG_ADDRESS (0x91)
+#define HAL_LL_TIM3_TCCR3C_REG_ADDRESS (0x92)
+#define HAL_LL_TIM3_TCNT3H_REG_ADDRESS (0x95)
+#define HAL_LL_TIM3_TCNT3L_REG_ADDRESS (0x94)
+#define HAL_LL_TIM3_ICR3_REG_ADDRESS (0x96)
+#define HAL_LL_TIM3_OCR3AH_REG_ADDRESS (0x99)
+#define HAL_LL_TIM3_OCR3AL_REG_ADDRESS (0x98)
+#define HAL_LL_TIM3_OCR3BH_REG_ADDRESS (0x9b)
+#define HAL_LL_TIM3_OCR3BL_REG_ADDRESS (0x9A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_PRR1_REG_ADDRESS (0x65)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (20)
+#define HAL_LL_USART0_UDRE_IVT (21)
+#define HAL_LL_USART0_TX_IVT (22)
+#define HAL_LL_USART1_RX_IVT (28)
+#define HAL_LL_USART1_UDRE_IVT (29)
+#define HAL_LL_USART1_TX_IVT (30)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x2A)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x2C)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x38)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x3C)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA1284P/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA1284P/mcu_definitions.h
new file mode 100644
index 000000000..0d6c9932a
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA1284P/mcu_definitions.h
@@ -0,0 +1,278 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC0
+#define TWI0_SDA_PC1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB6
+#define SPI0_MOSI_PB5
+#define SPI0_SCK_PB7
+#define SPI0_SS_PB4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB3_CH_A
+#define TIM0_PB4_CH_B
+#define TIM1_PD4_CH_B
+#define TIM1_PD5_CH_A
+#define TIM2_PD6_CH_B
+#define TIM2_PD7_CH_A
+#define TIM3_PB6_CH_A
+#define TIM3_PB7_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM3_TIFR3_REG_ADDRESS (0x38)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM3_TIMSK3_REG_ADDRESS (0x71)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM3_TCCR3A_REG_ADDRESS (0x90)
+#define HAL_LL_TIM3_TCCR3B_REG_ADDRESS (0x91)
+#define HAL_LL_TIM3_TCCR3C_REG_ADDRESS (0x92)
+#define HAL_LL_TIM3_TCNT3H_REG_ADDRESS (0x95)
+#define HAL_LL_TIM3_TCNT3L_REG_ADDRESS (0x94)
+#define HAL_LL_TIM3_ICR3_REG_ADDRESS (0x96)
+#define HAL_LL_TIM3_OCR3AH_REG_ADDRESS (0x99)
+#define HAL_LL_TIM3_OCR3AL_REG_ADDRESS (0x98)
+#define HAL_LL_TIM3_OCR3BH_REG_ADDRESS (0x9b)
+#define HAL_LL_TIM3_OCR3BL_REG_ADDRESS (0x9A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_PRR1_REG_ADDRESS (0x65)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (20)
+#define HAL_LL_USART0_UDRE_IVT (21)
+#define HAL_LL_USART0_TX_IVT (22)
+#define HAL_LL_USART1_RX_IVT (28)
+#define HAL_LL_USART1_UDRE_IVT (29)
+#define HAL_LL_USART1_TX_IVT (30)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x2A)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x2C)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x38)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x3C)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA128A/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA128A/mcu_definitions.h
new file mode 100644
index 000000000..3aeea19b4
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA128A/mcu_definitions.h
@@ -0,0 +1,298 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x24)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x25)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x24)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x26)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x27)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PD0
+#define TWI0_SDA_PD1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0x70)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0x71)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0x72)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0x73)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0x74)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0x29)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0x2A)
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0x2B)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0x2C)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0x90)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0x95)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0x98)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0x99)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0x9A)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0x9B)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0x9C)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0x9D)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x2D)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x2E)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x2F)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB4_CH_NONE
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM1_PB7_CH_C
+#define TIM2_PB7_CH_NONE
+#define TIM3_PE3_CH_A
+#define TIM3_PE4_CH_B
+#define TIM3_PE5_CH_C
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0x43)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0x44)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0x45)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x46)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x49)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x48)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x4b)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x4A)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x4d)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x4C)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x4E)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x4F)
+#define HAL_LL_TIM0_ASSR_REG_ADDRESS (0x50)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x51)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x52)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x53)
+#define HAL_LL_TIM1_OCR1CH_REG_ADDRESS (0x79)
+#define HAL_LL_TIM1_OCR1CL_REG_ADDRESS (0x78)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x7A)
+#define HAL_LL_TIM3_ICR3_REG_ADDRESS (0x80)
+#define HAL_LL_TIM3_OCR3CH_REG_ADDRESS (0x83)
+#define HAL_LL_TIM3_OCR3CL_REG_ADDRESS (0x82)
+#define HAL_LL_TIM3_OCR3BH_REG_ADDRESS (0x85)
+#define HAL_LL_TIM3_OCR3BL_REG_ADDRESS (0x84)
+#define HAL_LL_TIM3_OCR3AH_REG_ADDRESS (0x87)
+#define HAL_LL_TIM3_OCR3AL_REG_ADDRESS (0x86)
+#define HAL_LL_TIM3_TCNT3H_REG_ADDRESS (0x89)
+#define HAL_LL_TIM3_TCNT3L_REG_ADDRESS (0x88)
+#define HAL_LL_TIM3_TCCR3B_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM3_TCCR3A_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM3_TCCR3C_REG_ADDRESS (0x8C)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINF_REG_ADDRESS (0x20)
+#define PINE_REG_ADDRESS (0x21)
+#define DDRE_REG_ADDRESS (0x22)
+#define PORTE_REG_ADDRESS (0x23)
+#define PIND_REG_ADDRESS (0x30)
+#define DDRD_REG_ADDRESS (0x31)
+#define PORTD_REG_ADDRESS (0x32)
+#define PINC_REG_ADDRESS (0x33)
+#define DDRC_REG_ADDRESS (0x34)
+#define PORTC_REG_ADDRESS (0x35)
+#define PINB_REG_ADDRESS (0x36)
+#define DDRB_REG_ADDRESS (0x37)
+#define PORTB_REG_ADDRESS (0x38)
+#define PINA_REG_ADDRESS (0x39)
+#define DDRA_REG_ADDRESS (0x3A)
+#define PORTA_REG_ADDRESS (0x3B)
+#define DDRF_REG_ADDRESS (0x61)
+#define PORTF_REG_ADDRESS (0x62)
+#define PING_REG_ADDRESS (0x63)
+#define DDRG_REG_ADDRESS (0x64)
+#define PORTG_REG_ADDRESS (0x65)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_POWER_REDUCTION (false)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (18)
+#define HAL_LL_USART0_UDRE_IVT (19)
+#define HAL_LL_USART0_TX_IVT (20)
+#define HAL_LL_USART1_RX_IVT (30)
+#define HAL_LL_USART1_UDRE_IVT (31)
+#define HAL_LL_USART1_TX_IVT (32)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x24)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x26)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x3C)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x3E)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x40)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA16/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA16/mcu_definitions.h
new file mode 100644
index 000000000..f4cac7acc
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA16/mcu_definitions.h
@@ -0,0 +1,232 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x24)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x25)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x24)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x26)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x27)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC0
+#define TWI0_SDA_PC1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0x20)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0x21)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0x22)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0x23)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0x56)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART_RXD_PD0
+#define USART_TXD_PD1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0x29)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0x2A)
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0x2B)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0x2C)
+// Shared register addresses
+#define REGISTERS_WITH_SHARED_IO_LOCATION
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0x40)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0x40)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB6
+#define SPI0_MOSI_PB5
+#define SPI0_SCK_PB7
+#define SPI0_SS_PB4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x2D)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x2E)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x2F)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB3_CH_NONE
+#define TIM1_PD4_CH_B
+#define TIM1_PD5_CH_A
+#define TIM2_PD7_CH_NONE
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0x42)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0x43)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0x44)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0x45)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x46)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x49)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x48)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x4b)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x4A)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x4d)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x4C)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x4E)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x4F)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x52)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x53)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x5C)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PIND_REG_ADDRESS (0x30)
+#define DDRD_REG_ADDRESS (0x31)
+#define PORTD_REG_ADDRESS (0x32)
+#define PINC_REG_ADDRESS (0x33)
+#define DDRC_REG_ADDRESS (0x34)
+#define PORTC_REG_ADDRESS (0x35)
+#define PINB_REG_ADDRESS (0x36)
+#define DDRB_REG_ADDRESS (0x37)
+#define PORTB_REG_ADDRESS (0x38)
+#define PINA_REG_ADDRESS (0x39)
+#define DDRA_REG_ADDRESS (0x3A)
+#define PORTA_REG_ADDRESS (0x3B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_POWER_REDUCTION (false)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (11)
+#define HAL_LL_USART0_UDRE_IVT (12)
+#define HAL_LL_USART0_TX_IVT (13)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x16)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x18)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1A)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA164A/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA164A/mcu_definitions.h
new file mode 100644
index 000000000..5fa7ba891
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA164A/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC0
+#define TWI0_SDA_PC1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB6
+#define SPI0_MOSI_PB5
+#define SPI0_SCK_PB7
+#define SPI0_SS_PB4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB3_CH_A
+#define TIM0_PB4_CH_B
+#define TIM1_PD4_CH_B
+#define TIM1_PD5_CH_A
+#define TIM2_PD6_CH_B
+#define TIM2_PD7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (20)
+#define HAL_LL_USART0_UDRE_IVT (21)
+#define HAL_LL_USART0_TX_IVT (22)
+#define HAL_LL_USART1_RX_IVT (28)
+#define HAL_LL_USART1_UDRE_IVT (29)
+#define HAL_LL_USART1_TX_IVT (30)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x2A)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x2C)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x38)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x3C)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA164P/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA164P/mcu_definitions.h
new file mode 100644
index 000000000..5fa7ba891
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA164P/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC0
+#define TWI0_SDA_PC1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB6
+#define SPI0_MOSI_PB5
+#define SPI0_SCK_PB7
+#define SPI0_SS_PB4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB3_CH_A
+#define TIM0_PB4_CH_B
+#define TIM1_PD4_CH_B
+#define TIM1_PD5_CH_A
+#define TIM2_PD6_CH_B
+#define TIM2_PD7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (20)
+#define HAL_LL_USART0_UDRE_IVT (21)
+#define HAL_LL_USART0_TX_IVT (22)
+#define HAL_LL_USART1_RX_IVT (28)
+#define HAL_LL_USART1_UDRE_IVT (29)
+#define HAL_LL_USART1_TX_IVT (30)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x2A)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x2C)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x38)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x3C)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA164PA/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA164PA/mcu_definitions.h
new file mode 100644
index 000000000..5fa7ba891
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA164PA/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC0
+#define TWI0_SDA_PC1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB6
+#define SPI0_MOSI_PB5
+#define SPI0_SCK_PB7
+#define SPI0_SS_PB4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB3_CH_A
+#define TIM0_PB4_CH_B
+#define TIM1_PD4_CH_B
+#define TIM1_PD5_CH_A
+#define TIM2_PD6_CH_B
+#define TIM2_PD7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (20)
+#define HAL_LL_USART0_UDRE_IVT (21)
+#define HAL_LL_USART0_TX_IVT (22)
+#define HAL_LL_USART1_RX_IVT (28)
+#define HAL_LL_USART1_UDRE_IVT (29)
+#define HAL_LL_USART1_TX_IVT (30)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x2A)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x2C)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x38)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x3C)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA168/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA168/mcu_definitions.h
new file mode 100644
index 000000000..8e1b51e17
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA168/mcu_definitions.h
@@ -0,0 +1,232 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PC0_CH0
+#define ADC0_PC1_CH1
+#define ADC0_PC2_CH2
+#define ADC0_PC3_CH3
+#define ADC0_PC4_CH4
+#define ADC0_PC5_CH5
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (6)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC5
+#define TWI0_SDA_PC4
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB4
+#define SPI0_MOSI_PB3
+#define SPI0_SCK_PB5
+#define SPI0_SS_PB2
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PD5_CH_B
+#define TIM0_PD6_CH_A
+#define TIM1_PB1_CH_A
+#define TIM1_PB2_CH_B
+#define TIM2_PB3_CH_A
+#define TIM2_PD3_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (3)
+
+// GPIO Register addresses and offsets
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (18)
+#define HAL_LL_USART0_UDRE_IVT (19)
+#define HAL_LL_USART0_TX_IVT (20)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x24)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x26)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x28)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA168A/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA168A/mcu_definitions.h
new file mode 100644
index 000000000..8e1b51e17
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA168A/mcu_definitions.h
@@ -0,0 +1,232 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PC0_CH0
+#define ADC0_PC1_CH1
+#define ADC0_PC2_CH2
+#define ADC0_PC3_CH3
+#define ADC0_PC4_CH4
+#define ADC0_PC5_CH5
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (6)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC5
+#define TWI0_SDA_PC4
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB4
+#define SPI0_MOSI_PB3
+#define SPI0_SCK_PB5
+#define SPI0_SS_PB2
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PD5_CH_B
+#define TIM0_PD6_CH_A
+#define TIM1_PB1_CH_A
+#define TIM1_PB2_CH_B
+#define TIM2_PB3_CH_A
+#define TIM2_PD3_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (3)
+
+// GPIO Register addresses and offsets
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (18)
+#define HAL_LL_USART0_UDRE_IVT (19)
+#define HAL_LL_USART0_TX_IVT (20)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x24)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x26)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x28)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA168P/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA168P/mcu_definitions.h
new file mode 100644
index 000000000..8e1b51e17
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA168P/mcu_definitions.h
@@ -0,0 +1,232 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PC0_CH0
+#define ADC0_PC1_CH1
+#define ADC0_PC2_CH2
+#define ADC0_PC3_CH3
+#define ADC0_PC4_CH4
+#define ADC0_PC5_CH5
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (6)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC5
+#define TWI0_SDA_PC4
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB4
+#define SPI0_MOSI_PB3
+#define SPI0_SCK_PB5
+#define SPI0_SS_PB2
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PD5_CH_B
+#define TIM0_PD6_CH_A
+#define TIM1_PB1_CH_A
+#define TIM1_PB2_CH_B
+#define TIM2_PB3_CH_A
+#define TIM2_PD3_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (3)
+
+// GPIO Register addresses and offsets
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (18)
+#define HAL_LL_USART0_UDRE_IVT (19)
+#define HAL_LL_USART0_TX_IVT (20)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x24)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x26)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x28)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA168PA/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA168PA/mcu_definitions.h
new file mode 100644
index 000000000..8e1b51e17
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA168PA/mcu_definitions.h
@@ -0,0 +1,232 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PC0_CH0
+#define ADC0_PC1_CH1
+#define ADC0_PC2_CH2
+#define ADC0_PC3_CH3
+#define ADC0_PC4_CH4
+#define ADC0_PC5_CH5
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (6)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC5
+#define TWI0_SDA_PC4
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB4
+#define SPI0_MOSI_PB3
+#define SPI0_SCK_PB5
+#define SPI0_SS_PB2
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PD5_CH_B
+#define TIM0_PD6_CH_A
+#define TIM1_PB1_CH_A
+#define TIM1_PB2_CH_B
+#define TIM2_PB3_CH_A
+#define TIM2_PD3_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (3)
+
+// GPIO Register addresses and offsets
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (18)
+#define HAL_LL_USART0_UDRE_IVT (19)
+#define HAL_LL_USART0_TX_IVT (20)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x24)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x26)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x28)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA168PB/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA168PB/mcu_definitions.h
new file mode 100644
index 000000000..09b4b54af
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA168PB/mcu_definitions.h
@@ -0,0 +1,245 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PC0_CH0
+#define ADC0_PC1_CH1
+#define ADC0_PC2_CH2
+#define ADC0_PC3_CH3
+#define ADC0_PC4_CH4
+#define ADC0_PC5_CH5
+#define ADC0_PE2_CH6
+#define ADC0_PE3_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC5
+#define TWI0_SDA_PC4
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UCSR0D_REG_ADDRESS (0xC3)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB4
+#define SPI0_MOSI_PB3
+#define SPI0_SCK_PB5
+#define SPI0_SS_PB2
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PD5_CH_B
+#define TIM0_PD6_CH_A
+#define TIM1_PB1_CH_A
+#define TIM1_PB2_CH_B
+#define TIM2_PB3_CH_A
+#define TIM2_PD3_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (18)
+#define HAL_LL_USART0_UDRE_IVT (19)
+#define HAL_LL_USART0_TX_IVT (20)
+#define HAL_LL_USART0_START_IVT (26)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x24)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x26)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART0_START_IVT_ADDRESS (0x34)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA169A/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA169A/mcu_definitions.h
new file mode 100644
index 000000000..74d864d28
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA169A/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega169A does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (7)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB4_CH_A
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM2_PB7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA169P/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA169P/mcu_definitions.h
new file mode 100644
index 000000000..6fdf74208
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA169P/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega169P does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (7)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB4_CH_A
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM2_PB7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA169PA/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA169PA/mcu_definitions.h
new file mode 100644
index 000000000..06d410917
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA169PA/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega169PA does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (7)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB4_CH_A
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM2_PB7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA16A/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA16A/mcu_definitions.h
new file mode 100644
index 000000000..f4cac7acc
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA16A/mcu_definitions.h
@@ -0,0 +1,232 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x24)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x25)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x24)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x26)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x27)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC0
+#define TWI0_SDA_PC1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0x20)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0x21)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0x22)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0x23)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0x56)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART_RXD_PD0
+#define USART_TXD_PD1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0x29)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0x2A)
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0x2B)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0x2C)
+// Shared register addresses
+#define REGISTERS_WITH_SHARED_IO_LOCATION
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0x40)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0x40)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB6
+#define SPI0_MOSI_PB5
+#define SPI0_SCK_PB7
+#define SPI0_SS_PB4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x2D)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x2E)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x2F)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB3_CH_NONE
+#define TIM1_PD4_CH_B
+#define TIM1_PD5_CH_A
+#define TIM2_PD7_CH_NONE
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0x42)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0x43)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0x44)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0x45)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x46)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x49)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x48)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x4b)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x4A)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x4d)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x4C)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x4E)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x4F)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x52)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x53)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x5C)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PIND_REG_ADDRESS (0x30)
+#define DDRD_REG_ADDRESS (0x31)
+#define PORTD_REG_ADDRESS (0x32)
+#define PINC_REG_ADDRESS (0x33)
+#define DDRC_REG_ADDRESS (0x34)
+#define PORTC_REG_ADDRESS (0x35)
+#define PINB_REG_ADDRESS (0x36)
+#define DDRB_REG_ADDRESS (0x37)
+#define PORTB_REG_ADDRESS (0x38)
+#define PINA_REG_ADDRESS (0x39)
+#define DDRA_REG_ADDRESS (0x3A)
+#define PORTA_REG_ADDRESS (0x3B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_POWER_REDUCTION (false)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (11)
+#define HAL_LL_USART0_UDRE_IVT (12)
+#define HAL_LL_USART0_TX_IVT (13)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x16)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x18)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1A)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA16U4/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA16U4/mcu_definitions.h
new file mode 100644
index 000000000..68f049e95
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA16U4/mcu_definitions.h
@@ -0,0 +1,281 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PB4_CH11
+#define ADC0_PB5_CH12
+#define ADC0_PB6_CH13
+#define ADC0_PD4_CH8
+#define ADC0_PD6_CH9
+#define ADC0_PD7_CH10
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (12)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PD0
+#define TWI0_SDA_PD1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_1 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UCSR1D_REG_ADDRESS (0xCB)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB7_CH_A
+#define TIM0_PD0_CH_B
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM1_PB7_CH_C
+#define TIM3_PC6_CH_A
+#define TIM4_PB6_CH_B
+#define TIM4_PC7_CH_A
+#define TIM4_PD7_CH_D
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_3 (3)
+#define TIM_MODULE_4 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM3_TIFR3_REG_ADDRESS (0x38)
+#define HAL_LL_TIM4_TIFR4_REG_ADDRESS (0x39)
+#define HAL_LL_TIM0_GTCCR_REG_ADDRESS (0x43)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM3_TIMSK3_REG_ADDRESS (0x71)
+#define HAL_LL_TIM4_TIMSK4_REG_ADDRESS (0x72)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM1_OCR1CH_REG_ADDRESS (0x8d)
+#define HAL_LL_TIM1_OCR1CL_REG_ADDRESS (0x8C)
+#define HAL_LL_TIM3_TCCR3A_REG_ADDRESS (0x90)
+#define HAL_LL_TIM3_TCCR3B_REG_ADDRESS (0x91)
+#define HAL_LL_TIM3_TCCR3C_REG_ADDRESS (0x92)
+#define HAL_LL_TIM3_TCNT3H_REG_ADDRESS (0x95)
+#define HAL_LL_TIM3_TCNT3L_REG_ADDRESS (0x94)
+#define HAL_LL_TIM3_ICR3_REG_ADDRESS (0x96)
+#define HAL_LL_TIM3_OCR3AH_REG_ADDRESS (0x99)
+#define HAL_LL_TIM3_OCR3AL_REG_ADDRESS (0x98)
+#define HAL_LL_TIM3_OCR3BH_REG_ADDRESS (0x9b)
+#define HAL_LL_TIM3_OCR3BL_REG_ADDRESS (0x9A)
+#define HAL_LL_TIM3_OCR3CH_REG_ADDRESS (0x9d)
+#define HAL_LL_TIM3_OCR3CL_REG_ADDRESS (0x9C)
+#define HAL_LL_TIM4_TCNT4H_REG_ADDRESS (0xbf)
+#define HAL_LL_TIM4_TCNT4L_REG_ADDRESS (0xBE)
+#define HAL_LL_TIM4_TC4H_REG_ADDRESS (0xBF)
+#define HAL_LL_TIM4_TCCR4A_REG_ADDRESS (0xC0)
+#define HAL_LL_TIM4_TCCR4B_REG_ADDRESS (0xC1)
+#define HAL_LL_TIM4_TCCR4C_REG_ADDRESS (0xC2)
+#define HAL_LL_TIM4_TCCR4D_REG_ADDRESS (0xC3)
+#define HAL_LL_TIM4_TCCR4E_REG_ADDRESS (0xC4)
+#define HAL_LL_TIM4_OCR4AH_REG_ADDRESS (0xd0)
+#define HAL_LL_TIM4_OCR4AL_REG_ADDRESS (0xCF)
+#define HAL_LL_TIM4_OCR4BH_REG_ADDRESS (0xd1)
+#define HAL_LL_TIM4_OCR4BL_REG_ADDRESS (0xD0)
+#define HAL_LL_TIM4_OCR4CH_REG_ADDRESS (0xd2)
+#define HAL_LL_TIM4_OCR4CL_REG_ADDRESS (0xD1)
+#define HAL_LL_TIM4_OCR4D_REG_ADDRESS (0xD2)
+#define HAL_LL_TIM4_DT4_REG_ADDRESS (0xD4)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE2_CN
+#define __PE6_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (5)
+
+// GPIO Register addresses and offsets
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_PRR1_REG_ADDRESS (0x65)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART1_RX_IVT (25)
+#define HAL_LL_USART1_UDRE_IVT (26)
+#define HAL_LL_USART1_TX_IVT (27)
+// IVT ADDRESSES
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x32)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x36)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA2560/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA2560/mcu_definitions.h
new file mode 100644
index 000000000..e064c75ac
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA2560/mcu_definitions.h
@@ -0,0 +1,442 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+#define ADC0_PK0_CH8
+#define ADC0_PK1_CH9
+#define ADC0_PK2_CH10
+#define ADC0_PK3_CH11
+#define ADC0_PK4_CH12
+#define ADC0_PK5_CH13
+#define ADC0_PK6_CH14
+#define ADC0_PK7_CH15
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (16)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PD0
+#define TWI0_SDA_PD1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+#define USART2_RXD_PH0
+#define USART2_TXD_PH1
+#define USART3_RXD_PJ0
+#define USART3_TXD_PJ1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_2 (3)
+#define UART_MODULE_3 (4)
+#define UART_MODULE_COUNT (4)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+#define HAL_LL_USART2_UCSR2A_REG_ADDRESS (0xD0)
+#define HAL_LL_USART2_UCSR2B_REG_ADDRESS (0xD1)
+#define HAL_LL_USART2_UCSR2C_REG_ADDRESS (0xD2)
+#define HAL_LL_USART2_UBRR2L_REG_ADDRESS (0xD4)
+#define HAL_LL_USART2_UBRR2H_REG_ADDRESS (0xD5)
+#define HAL_LL_USART2_UBRR2_REG_ADDRESS (0xD4)
+#define HAL_LL_USART2_UDR2_REG_ADDRESS (0xD6)
+#define HAL_LL_USART3_UCSR3A_REG_ADDRESS (0x130)
+#define HAL_LL_USART3_UCSR3B_REG_ADDRESS (0x131)
+#define HAL_LL_USART3_UCSR3C_REG_ADDRESS (0x132)
+#define HAL_LL_USART3_UBRR3L_REG_ADDRESS (0x134)
+#define HAL_LL_USART3_UBRR3H_REG_ADDRESS (0x135)
+#define HAL_LL_USART3_UBRR3_REG_ADDRESS (0x134)
+#define HAL_LL_USART3_UDR3_REG_ADDRESS (0x136)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB7_CH_A
+#define TIM0_PG5_CH_B
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM1_PB7_CH_C
+#define TIM2_PB4_CH_A
+#define TIM2_PH6_CH_B
+#define TIM3_PE3_CH_A
+#define TIM3_PE4_CH_B
+#define TIM3_PE5_CH_C
+#define TIM4_PH3_CH_A
+#define TIM4_PH4_CH_B
+#define TIM4_PH5_CH_C
+#define TIM5_PL3_CH_A
+#define TIM5_PL4_CH_B
+#define TIM5_PL5_CH_C
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_4 (5)
+#define TIM_MODULE_5 (6)
+#define TIM_MODULE_COUNT (6)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM3_TIFR3_REG_ADDRESS (0x38)
+#define HAL_LL_TIM4_TIFR4_REG_ADDRESS (0x39)
+#define HAL_LL_TIM5_TIFR5_REG_ADDRESS (0x3A)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM3_TIMSK3_REG_ADDRESS (0x71)
+#define HAL_LL_TIM4_TIMSK4_REG_ADDRESS (0x72)
+#define HAL_LL_TIM5_TIMSK5_REG_ADDRESS (0x73)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM1_OCR1CH_REG_ADDRESS (0x8d)
+#define HAL_LL_TIM1_OCR1CL_REG_ADDRESS (0x8C)
+#define HAL_LL_TIM3_TCCR3A_REG_ADDRESS (0x90)
+#define HAL_LL_TIM3_TCCR3B_REG_ADDRESS (0x91)
+#define HAL_LL_TIM3_TCCR3C_REG_ADDRESS (0x92)
+#define HAL_LL_TIM3_TCNT3H_REG_ADDRESS (0x95)
+#define HAL_LL_TIM3_TCNT3L_REG_ADDRESS (0x94)
+#define HAL_LL_TIM3_ICR3_REG_ADDRESS (0x96)
+#define HAL_LL_TIM3_OCR3AH_REG_ADDRESS (0x99)
+#define HAL_LL_TIM3_OCR3AL_REG_ADDRESS (0x98)
+#define HAL_LL_TIM3_OCR3BH_REG_ADDRESS (0x9b)
+#define HAL_LL_TIM3_OCR3BL_REG_ADDRESS (0x9A)
+#define HAL_LL_TIM3_OCR3CH_REG_ADDRESS (0x9d)
+#define HAL_LL_TIM3_OCR3CL_REG_ADDRESS (0x9C)
+#define HAL_LL_TIM4_TCCR4A_REG_ADDRESS (0xA0)
+#define HAL_LL_TIM4_TCCR4B_REG_ADDRESS (0xA1)
+#define HAL_LL_TIM4_TCCR4C_REG_ADDRESS (0xA2)
+#define HAL_LL_TIM4_TCNT4H_REG_ADDRESS (0xa5)
+#define HAL_LL_TIM4_TCNT4L_REG_ADDRESS (0xA4)
+#define HAL_LL_TIM4_ICR4_REG_ADDRESS (0xA6)
+#define HAL_LL_TIM4_OCR4AH_REG_ADDRESS (0xa9)
+#define HAL_LL_TIM4_OCR4AL_REG_ADDRESS (0xA8)
+#define HAL_LL_TIM4_OCR4BH_REG_ADDRESS (0xab)
+#define HAL_LL_TIM4_OCR4BL_REG_ADDRESS (0xAA)
+#define HAL_LL_TIM4_OCR4CH_REG_ADDRESS (0xad)
+#define HAL_LL_TIM4_OCR4CL_REG_ADDRESS (0xAC)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+#define HAL_LL_TIM5_TCCR5A_REG_ADDRESS (0x120)
+#define HAL_LL_TIM5_TCCR5B_REG_ADDRESS (0x121)
+#define HAL_LL_TIM5_TCCR5C_REG_ADDRESS (0x122)
+#define HAL_LL_TIM5_TCNT5H_REG_ADDRESS (0x125)
+#define HAL_LL_TIM5_TCNT5L_REG_ADDRESS (0x124)
+#define HAL_LL_TIM5_ICR5_REG_ADDRESS (0x126)
+#define HAL_LL_TIM5_OCR5AH_REG_ADDRESS (0x129)
+#define HAL_LL_TIM5_OCR5AL_REG_ADDRESS (0x128)
+#define HAL_LL_TIM5_OCR5BH_REG_ADDRESS (0x12b)
+#define HAL_LL_TIM5_OCR5BL_REG_ADDRESS (0x12A)
+#define HAL_LL_TIM5_OCR5CH_REG_ADDRESS (0x12d)
+#define HAL_LL_TIM5_OCR5CL_REG_ADDRESS (0x12C)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+#define __PK0_CN
+#define __PK1_CN
+#define __PK2_CN
+#define __PK3_CN
+#define __PK4_CN
+#define __PK5_CN
+#define __PK6_CN
+#define __PK7_CN
+#define __PL0_CN
+#define __PL1_CN
+#define __PL2_CN
+#define __PL3_CN
+#define __PL4_CN
+#define __PL5_CN
+#define __PL6_CN
+#define __PL7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+#define __PORT_K_CN
+#define __PORT_L_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (11)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+#define PINH_REG_ADDRESS (0x100)
+#define DDRH_REG_ADDRESS (0x101)
+#define PORTH_REG_ADDRESS (0x102)
+#define PINJ_REG_ADDRESS (0x103)
+#define DDRJ_REG_ADDRESS (0x104)
+#define PORTJ_REG_ADDRESS (0x105)
+#define PINK_REG_ADDRESS (0x106)
+#define DDRK_REG_ADDRESS (0x107)
+#define PORTK_REG_ADDRESS (0x108)
+#define PINL_REG_ADDRESS (0x109)
+#define DDRL_REG_ADDRESS (0x10A)
+#define PORTL_REG_ADDRESS (0x10B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_PRR1_REG_ADDRESS (0x65)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (25)
+#define HAL_LL_USART0_UDRE_IVT (26)
+#define HAL_LL_USART0_TX_IVT (27)
+#define HAL_LL_USART1_RX_IVT (36)
+#define HAL_LL_USART1_UDRE_IVT (37)
+#define HAL_LL_USART1_TX_IVT (38)
+#define HAL_LL_USART2_RX_IVT (51)
+#define HAL_LL_USART2_UDRE_IVT (52)
+#define HAL_LL_USART2_TX_IVT (53)
+#define HAL_LL_USART3_RX_IVT (54)
+#define HAL_LL_USART3_UDRE_IVT (55)
+#define HAL_LL_USART3_TX_IVT (56)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x32)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x36)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x48)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x4A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x4C)
+#define HAL_LL_USART2_RX_IVT_ADDRESS (0x66)
+#define HAL_LL_USART2_UDRE_IVT_ADDRESS (0x68)
+#define HAL_LL_USART2_TX_IVT_ADDRESS (0x6A)
+#define HAL_LL_USART3_RX_IVT_ADDRESS (0x6C)
+#define HAL_LL_USART3_UDRE_IVT_ADDRESS (0x6E)
+#define HAL_LL_USART3_TX_IVT_ADDRESS (0x70)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA2561/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA2561/mcu_definitions.h
new file mode 100644
index 000000000..81f03d759
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA2561/mcu_definitions.h
@@ -0,0 +1,357 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PD0
+#define TWI0_SDA_PD1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB7_CH_A
+#define TIM0_PG5_CH_B
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM1_PB7_CH_C
+#define TIM2_PB4_CH_A
+#define TIM3_PE3_CH_A
+#define TIM3_PE4_CH_B
+#define TIM3_PE5_CH_C
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM3_TIFR3_REG_ADDRESS (0x38)
+#define HAL_LL_TIM4_TIFR4_REG_ADDRESS (0x39)
+#define HAL_LL_TIM5_TIFR5_REG_ADDRESS (0x3A)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM3_TIMSK3_REG_ADDRESS (0x71)
+#define HAL_LL_TIM4_TIMSK4_REG_ADDRESS (0x72)
+#define HAL_LL_TIM5_TIMSK5_REG_ADDRESS (0x73)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM1_OCR1CH_REG_ADDRESS (0x8d)
+#define HAL_LL_TIM1_OCR1CL_REG_ADDRESS (0x8C)
+#define HAL_LL_TIM3_TCCR3A_REG_ADDRESS (0x90)
+#define HAL_LL_TIM3_TCCR3B_REG_ADDRESS (0x91)
+#define HAL_LL_TIM3_TCCR3C_REG_ADDRESS (0x92)
+#define HAL_LL_TIM3_TCNT3H_REG_ADDRESS (0x95)
+#define HAL_LL_TIM3_TCNT3L_REG_ADDRESS (0x94)
+#define HAL_LL_TIM3_ICR3_REG_ADDRESS (0x96)
+#define HAL_LL_TIM3_OCR3AH_REG_ADDRESS (0x99)
+#define HAL_LL_TIM3_OCR3AL_REG_ADDRESS (0x98)
+#define HAL_LL_TIM3_OCR3BH_REG_ADDRESS (0x9b)
+#define HAL_LL_TIM3_OCR3BL_REG_ADDRESS (0x9A)
+#define HAL_LL_TIM3_OCR3CH_REG_ADDRESS (0x9d)
+#define HAL_LL_TIM3_OCR3CL_REG_ADDRESS (0x9C)
+#define HAL_LL_TIM4_TCCR4A_REG_ADDRESS (0xA0)
+#define HAL_LL_TIM4_TCCR4B_REG_ADDRESS (0xA1)
+#define HAL_LL_TIM4_TCCR4C_REG_ADDRESS (0xA2)
+#define HAL_LL_TIM4_TCNT4H_REG_ADDRESS (0xa5)
+#define HAL_LL_TIM4_TCNT4L_REG_ADDRESS (0xA4)
+#define HAL_LL_TIM4_ICR4_REG_ADDRESS (0xA6)
+#define HAL_LL_TIM4_OCR4AH_REG_ADDRESS (0xa9)
+#define HAL_LL_TIM4_OCR4AL_REG_ADDRESS (0xA8)
+#define HAL_LL_TIM4_OCR4BH_REG_ADDRESS (0xab)
+#define HAL_LL_TIM4_OCR4BL_REG_ADDRESS (0xAA)
+#define HAL_LL_TIM4_OCR4CH_REG_ADDRESS (0xad)
+#define HAL_LL_TIM4_OCR4CL_REG_ADDRESS (0xAC)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+#define HAL_LL_TIM5_TCCR5A_REG_ADDRESS (0x120)
+#define HAL_LL_TIM5_TCCR5B_REG_ADDRESS (0x121)
+#define HAL_LL_TIM5_TCCR5C_REG_ADDRESS (0x122)
+#define HAL_LL_TIM5_TCNT5H_REG_ADDRESS (0x125)
+#define HAL_LL_TIM5_TCNT5L_REG_ADDRESS (0x124)
+#define HAL_LL_TIM5_ICR5_REG_ADDRESS (0x126)
+#define HAL_LL_TIM5_OCR5AH_REG_ADDRESS (0x129)
+#define HAL_LL_TIM5_OCR5AL_REG_ADDRESS (0x128)
+#define HAL_LL_TIM5_OCR5BH_REG_ADDRESS (0x12b)
+#define HAL_LL_TIM5_OCR5BL_REG_ADDRESS (0x12A)
+#define HAL_LL_TIM5_OCR5CH_REG_ADDRESS (0x12d)
+#define HAL_LL_TIM5_OCR5CL_REG_ADDRESS (0x12C)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_PRR1_REG_ADDRESS (0x65)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (25)
+#define HAL_LL_USART0_UDRE_IVT (26)
+#define HAL_LL_USART0_TX_IVT (27)
+#define HAL_LL_USART1_RX_IVT (36)
+#define HAL_LL_USART1_UDRE_IVT (37)
+#define HAL_LL_USART1_TX_IVT (38)
+#define HAL_LL_USART2_RX_IVT (51)
+#define HAL_LL_USART2_UDRE_IVT (52)
+#define HAL_LL_USART2_TX_IVT (53)
+#define HAL_LL_USART3_RX_IVT (54)
+#define HAL_LL_USART3_UDRE_IVT (55)
+#define HAL_LL_USART3_TX_IVT (56)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x32)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x36)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x48)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x4A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x4C)
+#define HAL_LL_USART2_RX_IVT_ADDRESS (0x66)
+#define HAL_LL_USART2_UDRE_IVT_ADDRESS (0x68)
+#define HAL_LL_USART2_TX_IVT_ADDRESS (0x6A)
+#define HAL_LL_USART3_RX_IVT_ADDRESS (0x6C)
+#define HAL_LL_USART3_UDRE_IVT_ADDRESS (0x6E)
+#define HAL_LL_USART3_TX_IVT_ADDRESS (0x70)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA32/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA32/mcu_definitions.h
new file mode 100644
index 000000000..2bda5280a
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA32/mcu_definitions.h
@@ -0,0 +1,232 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x24)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x25)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x24)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x26)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x27)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC0
+#define TWI0_SDA_PC1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0x20)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0x21)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0x22)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0x23)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0x56)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART_RXD_PD0
+#define USART_TXD_PD1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0x29)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0x2A)
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0x2B)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0x2C)
+// Shared register addresses
+#define REGISTERS_WITH_SHARED_IO_LOCATION
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0x40)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0x40)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB6
+#define SPI0_MOSI_PB5
+#define SPI0_SCK_PB7
+#define SPI0_SS_PB4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x2D)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x2E)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x2F)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB3_CH_NONE
+#define TIM1_PD4_CH_B
+#define TIM1_PD5_CH_A
+#define TIM2_PD7_CH_NONE
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0x42)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0x43)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0x44)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0x45)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x46)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x49)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x48)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x4b)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x4A)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x4d)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x4C)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x4E)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x4F)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x52)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x53)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x5C)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PIND_REG_ADDRESS (0x30)
+#define DDRD_REG_ADDRESS (0x31)
+#define PORTD_REG_ADDRESS (0x32)
+#define PINC_REG_ADDRESS (0x33)
+#define DDRC_REG_ADDRESS (0x34)
+#define PORTC_REG_ADDRESS (0x35)
+#define PINB_REG_ADDRESS (0x36)
+#define DDRB_REG_ADDRESS (0x37)
+#define PORTB_REG_ADDRESS (0x38)
+#define PINA_REG_ADDRESS (0x39)
+#define DDRA_REG_ADDRESS (0x3A)
+#define PORTA_REG_ADDRESS (0x3B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_POWER_REDUCTION (false)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA324A/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA324A/mcu_definitions.h
new file mode 100644
index 000000000..5fa7ba891
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA324A/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC0
+#define TWI0_SDA_PC1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB6
+#define SPI0_MOSI_PB5
+#define SPI0_SCK_PB7
+#define SPI0_SS_PB4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB3_CH_A
+#define TIM0_PB4_CH_B
+#define TIM1_PD4_CH_B
+#define TIM1_PD5_CH_A
+#define TIM2_PD6_CH_B
+#define TIM2_PD7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (20)
+#define HAL_LL_USART0_UDRE_IVT (21)
+#define HAL_LL_USART0_TX_IVT (22)
+#define HAL_LL_USART1_RX_IVT (28)
+#define HAL_LL_USART1_UDRE_IVT (29)
+#define HAL_LL_USART1_TX_IVT (30)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x2A)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x2C)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x38)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x3C)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA324P/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA324P/mcu_definitions.h
new file mode 100644
index 000000000..5fa7ba891
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA324P/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC0
+#define TWI0_SDA_PC1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB6
+#define SPI0_MOSI_PB5
+#define SPI0_SCK_PB7
+#define SPI0_SS_PB4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB3_CH_A
+#define TIM0_PB4_CH_B
+#define TIM1_PD4_CH_B
+#define TIM1_PD5_CH_A
+#define TIM2_PD6_CH_B
+#define TIM2_PD7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (20)
+#define HAL_LL_USART0_UDRE_IVT (21)
+#define HAL_LL_USART0_TX_IVT (22)
+#define HAL_LL_USART1_RX_IVT (28)
+#define HAL_LL_USART1_UDRE_IVT (29)
+#define HAL_LL_USART1_TX_IVT (30)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x2A)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x2C)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x38)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x3C)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA324PA/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA324PA/mcu_definitions.h
new file mode 100644
index 000000000..5fa7ba891
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA324PA/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC0
+#define TWI0_SDA_PC1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB6
+#define SPI0_MOSI_PB5
+#define SPI0_SCK_PB7
+#define SPI0_SS_PB4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB3_CH_A
+#define TIM0_PB4_CH_B
+#define TIM1_PD4_CH_B
+#define TIM1_PD5_CH_A
+#define TIM2_PD6_CH_B
+#define TIM2_PD7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (20)
+#define HAL_LL_USART0_UDRE_IVT (21)
+#define HAL_LL_USART0_TX_IVT (22)
+#define HAL_LL_USART1_RX_IVT (28)
+#define HAL_LL_USART1_UDRE_IVT (29)
+#define HAL_LL_USART1_TX_IVT (30)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x2A)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x2C)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x38)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x3C)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA324PB/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA324PB/mcu_definitions.h
new file mode 100644
index 000000000..f8c321a11
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA324PB/mcu_definitions.h
@@ -0,0 +1,357 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL0_PC0
+#define TWI0_SDA0_PC1
+#define TWI1_SCL1_PE6
+#define TWI1_SDA1_PE5
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_1 (2)
+#define I2C_MODULE_1 (TWI_MODULE_1)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI0_TWBR0_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI0_TWBR0_REG_ADDRESS)
+#define HAL_LL_TWI0_TWSR0_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI0_TWAR0_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI0_TWDR0_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI0_TWCR0_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI0_TWAMR0_REG_ADDRESS (0xBD)
+#define HAL_LL_TWI1_TWBR1_REG_ADDRESS (0xD8)
+#define HAL_LL_I2C1_BASE_ADDRESS (HAL_LL_TWI1_TWBR1_REG_ADDRESS)
+#define HAL_LL_TWI1_TWSR1_REG_ADDRESS (0xD9)
+#define HAL_LL_TWI1_TWAR1_REG_ADDRESS (0xDA)
+#define HAL_LL_TWI1_TWDR1_REG_ADDRESS (0xDB)
+#define HAL_LL_TWI1_TWCR1_REG_ADDRESS (0xDC)
+#define HAL_LL_TWI1_TWAMR1_REG_ADDRESS (0xDD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+#define USART2_RXD_PE2
+#define USART2_TXD_PE3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_2 (3)
+#define UART_MODULE_COUNT (3)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UCSR0D_REG_ADDRESS (0xC3)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UCSR1D_REG_ADDRESS (0xCB)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+#define HAL_LL_USART2_UCSR2A_REG_ADDRESS (0xD0)
+#define HAL_LL_USART2_UCSR2B_REG_ADDRESS (0xD1)
+#define HAL_LL_USART2_UCSR2C_REG_ADDRESS (0xD2)
+#define HAL_LL_USART2_UCSR2D_REG_ADDRESS (0xD3)
+#define HAL_LL_USART2_UBRR2L_REG_ADDRESS (0xD4)
+#define HAL_LL_USART2_UBRR2H_REG_ADDRESS (0xD5)
+#define HAL_LL_USART2_UBRR2_REG_ADDRESS (0xD4)
+#define HAL_LL_USART2_UDR2_REG_ADDRESS (0xD6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB6
+#define SPI0_MOSI_PB5
+#define SPI0_SCK_PB7
+#define SPI0_SS_PB4
+#define SPI1_MISO_PE2
+#define SPI1_MOSI_PE3
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD6
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+#define HAL_LL_SPI1_SPCR_REG_ADDRESS (0xAC)
+#define HAL_LL_SPI1_SPSR_REG_ADDRESS (0xAD)
+#define HAL_LL_SPI1_SPDR_REG_ADDRESS (0xAE)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB3_CH_A
+#define TIM0_PB4_CH_B
+#define TIM1_PD4_CH_B
+#define TIM1_PD5_CH_A
+#define TIM2_PD6_CH_B
+#define TIM2_PD7_CH_A
+#define TIM3_PB6_CH_A
+#define TIM3_PB7_CH_B
+#define TIM4_PB7_CH_B
+#define TIM4_PC4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_4 (5)
+#define TIM_MODULE_COUNT (5)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM3_TIFR3_REG_ADDRESS (0x38)
+#define HAL_LL_TIM4_TIFR4_REG_ADDRESS (0x39)
+#define HAL_LL_TIM0_GTCCR_REG_ADDRESS (0x43)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM3_TIMSK3_REG_ADDRESS (0x71)
+#define HAL_LL_TIM4_TIMSK4_REG_ADDRESS (0x72)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM3_TCCR3A_REG_ADDRESS (0x90)
+#define HAL_LL_TIM3_TCCR3B_REG_ADDRESS (0x91)
+#define HAL_LL_TIM3_TCCR3C_REG_ADDRESS (0x92)
+#define HAL_LL_TIM3_TCNT3H_REG_ADDRESS (0x95)
+#define HAL_LL_TIM3_TCNT3L_REG_ADDRESS (0x94)
+#define HAL_LL_TIM3_ICR3_REG_ADDRESS (0x96)
+#define HAL_LL_TIM3_OCR3AH_REG_ADDRESS (0x99)
+#define HAL_LL_TIM3_OCR3AL_REG_ADDRESS (0x98)
+#define HAL_LL_TIM3_OCR3BH_REG_ADDRESS (0x9b)
+#define HAL_LL_TIM3_OCR3BL_REG_ADDRESS (0x9A)
+#define HAL_LL_TIM4_TCCR4A_REG_ADDRESS (0xA0)
+#define HAL_LL_TIM4_TCCR4B_REG_ADDRESS (0xA1)
+#define HAL_LL_TIM4_TCCR4C_REG_ADDRESS (0xA2)
+#define HAL_LL_TIM4_TCNT4H_REG_ADDRESS (0xa5)
+#define HAL_LL_TIM4_TCNT4L_REG_ADDRESS (0xA4)
+#define HAL_LL_TIM4_ICR4_REG_ADDRESS (0xA6)
+#define HAL_LL_TIM4_OCR4AH_REG_ADDRESS (0xa9)
+#define HAL_LL_TIM4_OCR4AL_REG_ADDRESS (0xA8)
+#define HAL_LL_TIM4_OCR4BH_REG_ADDRESS (0xab)
+#define HAL_LL_TIM4_OCR4BL_REG_ADDRESS (0xAA)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (5)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR2_REG_ADDRESS (0x63)
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_PRR1_REG_ADDRESS (0x65)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (20)
+#define HAL_LL_USART0_UDRE_IVT (21)
+#define HAL_LL_USART0_TX_IVT (22)
+#define HAL_LL_USART1_RX_IVT (28)
+#define HAL_LL_USART1_UDRE_IVT (29)
+#define HAL_LL_USART1_TX_IVT (30)
+#define HAL_LL_USART0_RXS_IVT (35)
+#define HAL_LL_USART0_START_IVT (35)
+#define HAL_LL_USART1_RXS_IVT (36)
+#define HAL_LL_USART1_START_IVT (36)
+#define HAL_LL_USART2_RX_IVT (47)
+#define HAL_LL_USART2_UDRE_IVT (48)
+#define HAL_LL_USART2_TX_IVT (49)
+#define HAL_LL_USART2_RXS_IVT (50)
+#define HAL_LL_USART2_START_IVT (50)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x2A)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x2C)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x38)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x3C)
+#define HAL_LL_USART0_RXS_IVT_ADDRESS (0x46)
+#define HAL_LL_USART0_START_IVT_ADDRESS (0x46)
+#define HAL_LL_USART1_RXS_IVT_ADDRESS (0x48)
+#define HAL_LL_USART1_START_IVT_ADDRESS (0x48)
+#define HAL_LL_USART2_RX_IVT_ADDRESS (0x5E)
+#define HAL_LL_USART2_UDRE_IVT_ADDRESS (0x60)
+#define HAL_LL_USART2_TX_IVT_ADDRESS (0x62)
+#define HAL_LL_USART2_RXS_IVT_ADDRESS (0x64)
+#define HAL_LL_USART2_START_IVT_ADDRESS (0x64)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA325/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA325/mcu_definitions.h
new file mode 100644
index 000000000..61cbaa948
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA325/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega325 does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (7)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3250/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3250/mcu_definitions.h
new file mode 100644
index 000000000..721e154df
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3250/mcu_definitions.h
@@ -0,0 +1,286 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega3250 does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (9)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (9)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+#define PINH_REG_ADDRESS (0xD8)
+#define DDRH_REG_ADDRESS (0xD9)
+#define PORTH_REG_ADDRESS (0xDA)
+#define PINJ_REG_ADDRESS (0xDB)
+#define DDRJ_REG_ADDRESS (0xDC)
+#define PORTJ_REG_ADDRESS (0xDD)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3250A/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3250A/mcu_definitions.h
new file mode 100644
index 000000000..6dc24c5ea
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3250A/mcu_definitions.h
@@ -0,0 +1,286 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega3250A does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (9)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (9)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+#define PINH_REG_ADDRESS (0xD8)
+#define DDRH_REG_ADDRESS (0xD9)
+#define PORTH_REG_ADDRESS (0xDA)
+#define PINJ_REG_ADDRESS (0xDB)
+#define DDRJ_REG_ADDRESS (0xDC)
+#define PORTJ_REG_ADDRESS (0xDD)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3250P/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3250P/mcu_definitions.h
new file mode 100644
index 000000000..dce667947
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3250P/mcu_definitions.h
@@ -0,0 +1,286 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega3250P does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (9)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (9)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+#define PINH_REG_ADDRESS (0xD8)
+#define DDRH_REG_ADDRESS (0xD9)
+#define PORTH_REG_ADDRESS (0xDA)
+#define PINJ_REG_ADDRESS (0xDB)
+#define DDRJ_REG_ADDRESS (0xDC)
+#define PORTJ_REG_ADDRESS (0xDD)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3250PA/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3250PA/mcu_definitions.h
new file mode 100644
index 000000000..d71be10eb
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3250PA/mcu_definitions.h
@@ -0,0 +1,286 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega3250PA does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (9)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (9)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+#define PINH_REG_ADDRESS (0xD8)
+#define DDRH_REG_ADDRESS (0xD9)
+#define PORTH_REG_ADDRESS (0xDA)
+#define PINJ_REG_ADDRESS (0xDB)
+#define DDRJ_REG_ADDRESS (0xDC)
+#define PORTJ_REG_ADDRESS (0xDD)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA325A/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA325A/mcu_definitions.h
new file mode 100644
index 000000000..87c85a7b2
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA325A/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega325A does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (7)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA325P/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA325P/mcu_definitions.h
new file mode 100644
index 000000000..4a0c88d2e
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA325P/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega325P does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (7)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA325PA/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA325PA/mcu_definitions.h
new file mode 100644
index 000000000..e22ddd4ee
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA325PA/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega325PA does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (7)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA328/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA328/mcu_definitions.h
new file mode 100644
index 000000000..8e1b51e17
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA328/mcu_definitions.h
@@ -0,0 +1,232 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PC0_CH0
+#define ADC0_PC1_CH1
+#define ADC0_PC2_CH2
+#define ADC0_PC3_CH3
+#define ADC0_PC4_CH4
+#define ADC0_PC5_CH5
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (6)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC5
+#define TWI0_SDA_PC4
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB4
+#define SPI0_MOSI_PB3
+#define SPI0_SCK_PB5
+#define SPI0_SS_PB2
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PD5_CH_B
+#define TIM0_PD6_CH_A
+#define TIM1_PB1_CH_A
+#define TIM1_PB2_CH_B
+#define TIM2_PB3_CH_A
+#define TIM2_PD3_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (3)
+
+// GPIO Register addresses and offsets
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (18)
+#define HAL_LL_USART0_UDRE_IVT (19)
+#define HAL_LL_USART0_TX_IVT (20)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x24)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x26)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x28)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA328PB/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA328PB/mcu_definitions.h
new file mode 100644
index 000000000..79730a37e
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA328PB/mcu_definitions.h
@@ -0,0 +1,314 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PC0_CH0
+#define ADC0_PC1_CH1
+#define ADC0_PC2_CH2
+#define ADC0_PC3_CH3
+#define ADC0_PC4_CH4
+#define ADC0_PC5_CH5
+#define ADC0_PE2_CH6
+#define ADC0_PE3_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC5
+#define TWI0_SDA_PC4
+#define TWI1_SCL_PE1
+#define TWI1_SDA_PE0
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_1 (2)
+#define I2C_MODULE_1 (TWI_MODULE_1)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI0_TWBR0_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI0_TWBR0_REG_ADDRESS)
+#define HAL_LL_TWI0_TWSR0_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI0_TWAR0_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI0_TWDR0_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI0_TWCR0_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI0_TWAMR0_REG_ADDRESS (0xBD)
+#define HAL_LL_TWI1_TWBR1_REG_ADDRESS (0xD8)
+#define HAL_LL_I2C1_BASE_ADDRESS (HAL_LL_TWI1_TWBR1_REG_ADDRESS)
+#define HAL_LL_TWI1_TWSR1_REG_ADDRESS (0xD9)
+#define HAL_LL_TWI1_TWAR1_REG_ADDRESS (0xDA)
+#define HAL_LL_TWI1_TWDR1_REG_ADDRESS (0xDB)
+#define HAL_LL_TWI1_TWCR1_REG_ADDRESS (0xDC)
+#define HAL_LL_TWI1_TWAMR1_REG_ADDRESS (0xDD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+#define USART1_RXD_PB4
+#define USART1_TXD_PB3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UCSR0D_REG_ADDRESS (0xC3)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UCSR1D_REG_ADDRESS (0xCB)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB4
+#define SPI0_MOSI_PB3
+#define SPI0_SCK_PB5
+#define SPI0_SS_PB2
+#define SPI1_MISO_PC0
+#define SPI1_MOSI_PE3
+#define SPI1_SCK_PC1
+#define SPI1_SS_PE2
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+#define HAL_LL_SPI1_SPCR_REG_ADDRESS (0xAC)
+#define HAL_LL_SPI1_SPSR_REG_ADDRESS (0xAD)
+#define HAL_LL_SPI1_SPDR_REG_ADDRESS (0xAE)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PD5_CH_B
+#define TIM0_PD6_CH_A
+#define TIM1_PB1_CH_A
+#define TIM1_PB2_CH_B
+#define TIM2_PB3_CH_A
+#define TIM2_PD3_CH_B
+#define TIM3_PD0_CH_A
+#define TIM3_PD2_CH_B
+#define TIM4_PD1_CH_A
+#define TIM4_PD2_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_4 (5)
+#define TIM_MODULE_COUNT (5)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM3_TIFR3_REG_ADDRESS (0x38)
+#define HAL_LL_TIM4_TIFR4_REG_ADDRESS (0x39)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM3_TIMSK3_REG_ADDRESS (0x71)
+#define HAL_LL_TIM4_TIMSK4_REG_ADDRESS (0x72)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM3_TCCR3A_REG_ADDRESS (0x90)
+#define HAL_LL_TIM3_TCCR3B_REG_ADDRESS (0x91)
+#define HAL_LL_TIM3_TCCR3C_REG_ADDRESS (0x92)
+#define HAL_LL_TIM3_TCNT3H_REG_ADDRESS (0x95)
+#define HAL_LL_TIM3_TCNT3L_REG_ADDRESS (0x94)
+#define HAL_LL_TIM3_ICR3_REG_ADDRESS (0x96)
+#define HAL_LL_TIM3_OCR3AH_REG_ADDRESS (0x99)
+#define HAL_LL_TIM3_OCR3AL_REG_ADDRESS (0x98)
+#define HAL_LL_TIM3_OCR3BH_REG_ADDRESS (0x9b)
+#define HAL_LL_TIM3_OCR3BL_REG_ADDRESS (0x9A)
+#define HAL_LL_TIM4_TCCR4A_REG_ADDRESS (0xA0)
+#define HAL_LL_TIM4_TCCR4B_REG_ADDRESS (0xA1)
+#define HAL_LL_TIM4_TCCR4C_REG_ADDRESS (0xA2)
+#define HAL_LL_TIM4_TCNT4H_REG_ADDRESS (0xa5)
+#define HAL_LL_TIM4_TCNT4L_REG_ADDRESS (0xA4)
+#define HAL_LL_TIM4_ICR4_REG_ADDRESS (0xA6)
+#define HAL_LL_TIM4_OCR4AH_REG_ADDRESS (0xa9)
+#define HAL_LL_TIM4_OCR4AL_REG_ADDRESS (0xA8)
+#define HAL_LL_TIM4_OCR4BH_REG_ADDRESS (0xab)
+#define HAL_LL_TIM4_OCR4BL_REG_ADDRESS (0xAA)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_PRR1_REG_ADDRESS (0x65)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (18)
+#define HAL_LL_USART0_UDRE_IVT (19)
+#define HAL_LL_USART0_TX_IVT (20)
+#define HAL_LL_USART0_START_IVT (26)
+#define HAL_LL_USART1_RX_IVT (28)
+#define HAL_LL_USART1_UDRE_IVT (29)
+#define HAL_LL_USART1_TX_IVT (30)
+#define HAL_LL_USART1_START_IVT (31)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x24)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x26)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART0_START_IVT_ADDRESS (0x34)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x38)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x3C)
+#define HAL_LL_USART1_START_IVT_ADDRESS (0x3E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA329/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA329/mcu_definitions.h
new file mode 100644
index 000000000..2792ad2f3
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA329/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega329 does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (7)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB4_CH_A
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM2_PB7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3290/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3290/mcu_definitions.h
new file mode 100644
index 000000000..0bc7e7af6
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3290/mcu_definitions.h
@@ -0,0 +1,286 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega3290 does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (9)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (9)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+#define PINH_REG_ADDRESS (0xD8)
+#define DDRH_REG_ADDRESS (0xD9)
+#define PORTH_REG_ADDRESS (0xDA)
+#define PINJ_REG_ADDRESS (0xDB)
+#define DDRJ_REG_ADDRESS (0xDC)
+#define PORTJ_REG_ADDRESS (0xDD)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3290A/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3290A/mcu_definitions.h
new file mode 100644
index 000000000..aadff2823
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3290A/mcu_definitions.h
@@ -0,0 +1,286 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega3290A does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (9)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (9)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+#define PINH_REG_ADDRESS (0xD8)
+#define DDRH_REG_ADDRESS (0xD9)
+#define PORTH_REG_ADDRESS (0xDA)
+#define PINJ_REG_ADDRESS (0xDB)
+#define DDRJ_REG_ADDRESS (0xDC)
+#define PORTJ_REG_ADDRESS (0xDD)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3290P/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3290P/mcu_definitions.h
new file mode 100644
index 000000000..03e40218f
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA3290P/mcu_definitions.h
@@ -0,0 +1,286 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega3290P does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (9)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (9)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+#define PINH_REG_ADDRESS (0xD8)
+#define DDRH_REG_ADDRESS (0xD9)
+#define PORTH_REG_ADDRESS (0xDA)
+#define PINJ_REG_ADDRESS (0xDB)
+#define DDRJ_REG_ADDRESS (0xDC)
+#define PORTJ_REG_ADDRESS (0xDD)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA329A/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA329A/mcu_definitions.h
new file mode 100644
index 000000000..e66fa8fca
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA329A/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega329A does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (7)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB4_CH_A
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM2_PB7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA329P/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA329P/mcu_definitions.h
new file mode 100644
index 000000000..a58f78313
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA329P/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega329P does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (7)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB4_CH_A
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM2_PB7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA329PA/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA329PA/mcu_definitions.h
new file mode 100644
index 000000000..6195df624
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA329PA/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega329PA does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (7)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB4_CH_A
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM2_PB7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA32A/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA32A/mcu_definitions.h
new file mode 100644
index 000000000..2bda5280a
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA32A/mcu_definitions.h
@@ -0,0 +1,232 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x24)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x25)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x24)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x26)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x27)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC0
+#define TWI0_SDA_PC1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0x20)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0x21)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0x22)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0x23)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0x56)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART_RXD_PD0
+#define USART_TXD_PD1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0x29)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0x2A)
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0x2B)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0x2C)
+// Shared register addresses
+#define REGISTERS_WITH_SHARED_IO_LOCATION
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0x40)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0x40)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB6
+#define SPI0_MOSI_PB5
+#define SPI0_SCK_PB7
+#define SPI0_SS_PB4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x2D)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x2E)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x2F)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB3_CH_NONE
+#define TIM1_PD4_CH_B
+#define TIM1_PD5_CH_A
+#define TIM2_PD7_CH_NONE
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0x42)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0x43)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0x44)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0x45)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x46)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x49)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x48)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x4b)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x4A)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x4d)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x4C)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x4E)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x4F)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x52)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x53)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x5C)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PIND_REG_ADDRESS (0x30)
+#define DDRD_REG_ADDRESS (0x31)
+#define PORTD_REG_ADDRESS (0x32)
+#define PINC_REG_ADDRESS (0x33)
+#define DDRC_REG_ADDRESS (0x34)
+#define PORTC_REG_ADDRESS (0x35)
+#define PINB_REG_ADDRESS (0x36)
+#define DDRB_REG_ADDRESS (0x37)
+#define PORTB_REG_ADDRESS (0x38)
+#define PINA_REG_ADDRESS (0x39)
+#define DDRA_REG_ADDRESS (0x3A)
+#define PORTA_REG_ADDRESS (0x3B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_POWER_REDUCTION (false)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA32U4/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA32U4/mcu_definitions.h
new file mode 100644
index 000000000..68f049e95
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA32U4/mcu_definitions.h
@@ -0,0 +1,281 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PB4_CH11
+#define ADC0_PB5_CH12
+#define ADC0_PB6_CH13
+#define ADC0_PD4_CH8
+#define ADC0_PD6_CH9
+#define ADC0_PD7_CH10
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (12)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PD0
+#define TWI0_SDA_PD1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_1 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UCSR1D_REG_ADDRESS (0xCB)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB7_CH_A
+#define TIM0_PD0_CH_B
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM1_PB7_CH_C
+#define TIM3_PC6_CH_A
+#define TIM4_PB6_CH_B
+#define TIM4_PC7_CH_A
+#define TIM4_PD7_CH_D
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_3 (3)
+#define TIM_MODULE_4 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM3_TIFR3_REG_ADDRESS (0x38)
+#define HAL_LL_TIM4_TIFR4_REG_ADDRESS (0x39)
+#define HAL_LL_TIM0_GTCCR_REG_ADDRESS (0x43)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM3_TIMSK3_REG_ADDRESS (0x71)
+#define HAL_LL_TIM4_TIMSK4_REG_ADDRESS (0x72)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM1_OCR1CH_REG_ADDRESS (0x8d)
+#define HAL_LL_TIM1_OCR1CL_REG_ADDRESS (0x8C)
+#define HAL_LL_TIM3_TCCR3A_REG_ADDRESS (0x90)
+#define HAL_LL_TIM3_TCCR3B_REG_ADDRESS (0x91)
+#define HAL_LL_TIM3_TCCR3C_REG_ADDRESS (0x92)
+#define HAL_LL_TIM3_TCNT3H_REG_ADDRESS (0x95)
+#define HAL_LL_TIM3_TCNT3L_REG_ADDRESS (0x94)
+#define HAL_LL_TIM3_ICR3_REG_ADDRESS (0x96)
+#define HAL_LL_TIM3_OCR3AH_REG_ADDRESS (0x99)
+#define HAL_LL_TIM3_OCR3AL_REG_ADDRESS (0x98)
+#define HAL_LL_TIM3_OCR3BH_REG_ADDRESS (0x9b)
+#define HAL_LL_TIM3_OCR3BL_REG_ADDRESS (0x9A)
+#define HAL_LL_TIM3_OCR3CH_REG_ADDRESS (0x9d)
+#define HAL_LL_TIM3_OCR3CL_REG_ADDRESS (0x9C)
+#define HAL_LL_TIM4_TCNT4H_REG_ADDRESS (0xbf)
+#define HAL_LL_TIM4_TCNT4L_REG_ADDRESS (0xBE)
+#define HAL_LL_TIM4_TC4H_REG_ADDRESS (0xBF)
+#define HAL_LL_TIM4_TCCR4A_REG_ADDRESS (0xC0)
+#define HAL_LL_TIM4_TCCR4B_REG_ADDRESS (0xC1)
+#define HAL_LL_TIM4_TCCR4C_REG_ADDRESS (0xC2)
+#define HAL_LL_TIM4_TCCR4D_REG_ADDRESS (0xC3)
+#define HAL_LL_TIM4_TCCR4E_REG_ADDRESS (0xC4)
+#define HAL_LL_TIM4_OCR4AH_REG_ADDRESS (0xd0)
+#define HAL_LL_TIM4_OCR4AL_REG_ADDRESS (0xCF)
+#define HAL_LL_TIM4_OCR4BH_REG_ADDRESS (0xd1)
+#define HAL_LL_TIM4_OCR4BL_REG_ADDRESS (0xD0)
+#define HAL_LL_TIM4_OCR4CH_REG_ADDRESS (0xd2)
+#define HAL_LL_TIM4_OCR4CL_REG_ADDRESS (0xD1)
+#define HAL_LL_TIM4_OCR4D_REG_ADDRESS (0xD2)
+#define HAL_LL_TIM4_DT4_REG_ADDRESS (0xD4)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE2_CN
+#define __PE6_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (5)
+
+// GPIO Register addresses and offsets
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_PRR1_REG_ADDRESS (0x65)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART1_RX_IVT (25)
+#define HAL_LL_USART1_UDRE_IVT (26)
+#define HAL_LL_USART1_TX_IVT (27)
+// IVT ADDRESSES
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x32)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x36)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA64/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA64/mcu_definitions.h
new file mode 100644
index 000000000..00f0dd979
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA64/mcu_definitions.h
@@ -0,0 +1,299 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x24)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x25)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x24)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x26)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x27)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x8E)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PD0
+#define TWI0_SDA_PD1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0x70)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0x71)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0x72)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0x73)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0x74)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0x29)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0x2A)
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0x2B)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0x2C)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0x90)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0x95)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0x98)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0x99)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0x9A)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0x9B)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0x9C)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0x9D)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x2D)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x2E)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x2F)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB4_CH_NONE
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM1_PB7_CH_C
+#define TIM2_PB7_CH_NONE
+#define TIM3_PE3_CH_A
+#define TIM3_PE4_CH_B
+#define TIM3_PE5_CH_C
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0x43)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0x44)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0x45)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x46)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x49)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x48)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x4b)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x4A)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x4d)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x4C)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x4E)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x4F)
+#define HAL_LL_TIM0_ASSR_REG_ADDRESS (0x50)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x51)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x52)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x53)
+#define HAL_LL_TIM1_OCR1CH_REG_ADDRESS (0x79)
+#define HAL_LL_TIM1_OCR1CL_REG_ADDRESS (0x78)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x7A)
+#define HAL_LL_TIM3_ICR3_REG_ADDRESS (0x80)
+#define HAL_LL_TIM3_OCR3CH_REG_ADDRESS (0x83)
+#define HAL_LL_TIM3_OCR3CL_REG_ADDRESS (0x82)
+#define HAL_LL_TIM3_OCR3BH_REG_ADDRESS (0x85)
+#define HAL_LL_TIM3_OCR3BL_REG_ADDRESS (0x84)
+#define HAL_LL_TIM3_OCR3AH_REG_ADDRESS (0x87)
+#define HAL_LL_TIM3_OCR3AL_REG_ADDRESS (0x86)
+#define HAL_LL_TIM3_TCNT3H_REG_ADDRESS (0x89)
+#define HAL_LL_TIM3_TCNT3L_REG_ADDRESS (0x88)
+#define HAL_LL_TIM3_TCCR3B_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM3_TCCR3A_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM3_TCCR3C_REG_ADDRESS (0x8C)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINF_REG_ADDRESS (0x20)
+#define PINE_REG_ADDRESS (0x21)
+#define DDRE_REG_ADDRESS (0x22)
+#define PORTE_REG_ADDRESS (0x23)
+#define PIND_REG_ADDRESS (0x30)
+#define DDRD_REG_ADDRESS (0x31)
+#define PORTD_REG_ADDRESS (0x32)
+#define PINC_REG_ADDRESS (0x33)
+#define DDRC_REG_ADDRESS (0x34)
+#define PORTC_REG_ADDRESS (0x35)
+#define PINB_REG_ADDRESS (0x36)
+#define DDRB_REG_ADDRESS (0x37)
+#define PORTB_REG_ADDRESS (0x38)
+#define PINA_REG_ADDRESS (0x39)
+#define DDRA_REG_ADDRESS (0x3A)
+#define PORTA_REG_ADDRESS (0x3B)
+#define DDRF_REG_ADDRESS (0x61)
+#define PORTF_REG_ADDRESS (0x62)
+#define PING_REG_ADDRESS (0x63)
+#define DDRG_REG_ADDRESS (0x64)
+#define PORTG_REG_ADDRESS (0x65)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_POWER_REDUCTION (false)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (18)
+#define HAL_LL_USART0_UDRE_IVT (19)
+#define HAL_LL_USART0_TX_IVT (20)
+#define HAL_LL_USART1_RX_IVT (30)
+#define HAL_LL_USART1_UDRE_IVT (31)
+#define HAL_LL_USART1_TX_IVT (32)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x24)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x26)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x3C)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x3E)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x40)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA640/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA640/mcu_definitions.h
new file mode 100644
index 000000000..e064c75ac
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA640/mcu_definitions.h
@@ -0,0 +1,442 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+#define ADC0_PK0_CH8
+#define ADC0_PK1_CH9
+#define ADC0_PK2_CH10
+#define ADC0_PK3_CH11
+#define ADC0_PK4_CH12
+#define ADC0_PK5_CH13
+#define ADC0_PK6_CH14
+#define ADC0_PK7_CH15
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (16)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PD0
+#define TWI0_SDA_PD1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+#define USART2_RXD_PH0
+#define USART2_TXD_PH1
+#define USART3_RXD_PJ0
+#define USART3_TXD_PJ1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_2 (3)
+#define UART_MODULE_3 (4)
+#define UART_MODULE_COUNT (4)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+#define HAL_LL_USART2_UCSR2A_REG_ADDRESS (0xD0)
+#define HAL_LL_USART2_UCSR2B_REG_ADDRESS (0xD1)
+#define HAL_LL_USART2_UCSR2C_REG_ADDRESS (0xD2)
+#define HAL_LL_USART2_UBRR2L_REG_ADDRESS (0xD4)
+#define HAL_LL_USART2_UBRR2H_REG_ADDRESS (0xD5)
+#define HAL_LL_USART2_UBRR2_REG_ADDRESS (0xD4)
+#define HAL_LL_USART2_UDR2_REG_ADDRESS (0xD6)
+#define HAL_LL_USART3_UCSR3A_REG_ADDRESS (0x130)
+#define HAL_LL_USART3_UCSR3B_REG_ADDRESS (0x131)
+#define HAL_LL_USART3_UCSR3C_REG_ADDRESS (0x132)
+#define HAL_LL_USART3_UBRR3L_REG_ADDRESS (0x134)
+#define HAL_LL_USART3_UBRR3H_REG_ADDRESS (0x135)
+#define HAL_LL_USART3_UBRR3_REG_ADDRESS (0x134)
+#define HAL_LL_USART3_UDR3_REG_ADDRESS (0x136)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB7_CH_A
+#define TIM0_PG5_CH_B
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM1_PB7_CH_C
+#define TIM2_PB4_CH_A
+#define TIM2_PH6_CH_B
+#define TIM3_PE3_CH_A
+#define TIM3_PE4_CH_B
+#define TIM3_PE5_CH_C
+#define TIM4_PH3_CH_A
+#define TIM4_PH4_CH_B
+#define TIM4_PH5_CH_C
+#define TIM5_PL3_CH_A
+#define TIM5_PL4_CH_B
+#define TIM5_PL5_CH_C
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_4 (5)
+#define TIM_MODULE_5 (6)
+#define TIM_MODULE_COUNT (6)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM3_TIFR3_REG_ADDRESS (0x38)
+#define HAL_LL_TIM4_TIFR4_REG_ADDRESS (0x39)
+#define HAL_LL_TIM5_TIFR5_REG_ADDRESS (0x3A)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM3_TIMSK3_REG_ADDRESS (0x71)
+#define HAL_LL_TIM4_TIMSK4_REG_ADDRESS (0x72)
+#define HAL_LL_TIM5_TIMSK5_REG_ADDRESS (0x73)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM1_OCR1CH_REG_ADDRESS (0x8d)
+#define HAL_LL_TIM1_OCR1CL_REG_ADDRESS (0x8C)
+#define HAL_LL_TIM3_TCCR3A_REG_ADDRESS (0x90)
+#define HAL_LL_TIM3_TCCR3B_REG_ADDRESS (0x91)
+#define HAL_LL_TIM3_TCCR3C_REG_ADDRESS (0x92)
+#define HAL_LL_TIM3_TCNT3H_REG_ADDRESS (0x95)
+#define HAL_LL_TIM3_TCNT3L_REG_ADDRESS (0x94)
+#define HAL_LL_TIM3_ICR3_REG_ADDRESS (0x96)
+#define HAL_LL_TIM3_OCR3AH_REG_ADDRESS (0x99)
+#define HAL_LL_TIM3_OCR3AL_REG_ADDRESS (0x98)
+#define HAL_LL_TIM3_OCR3BH_REG_ADDRESS (0x9b)
+#define HAL_LL_TIM3_OCR3BL_REG_ADDRESS (0x9A)
+#define HAL_LL_TIM3_OCR3CH_REG_ADDRESS (0x9d)
+#define HAL_LL_TIM3_OCR3CL_REG_ADDRESS (0x9C)
+#define HAL_LL_TIM4_TCCR4A_REG_ADDRESS (0xA0)
+#define HAL_LL_TIM4_TCCR4B_REG_ADDRESS (0xA1)
+#define HAL_LL_TIM4_TCCR4C_REG_ADDRESS (0xA2)
+#define HAL_LL_TIM4_TCNT4H_REG_ADDRESS (0xa5)
+#define HAL_LL_TIM4_TCNT4L_REG_ADDRESS (0xA4)
+#define HAL_LL_TIM4_ICR4_REG_ADDRESS (0xA6)
+#define HAL_LL_TIM4_OCR4AH_REG_ADDRESS (0xa9)
+#define HAL_LL_TIM4_OCR4AL_REG_ADDRESS (0xA8)
+#define HAL_LL_TIM4_OCR4BH_REG_ADDRESS (0xab)
+#define HAL_LL_TIM4_OCR4BL_REG_ADDRESS (0xAA)
+#define HAL_LL_TIM4_OCR4CH_REG_ADDRESS (0xad)
+#define HAL_LL_TIM4_OCR4CL_REG_ADDRESS (0xAC)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+#define HAL_LL_TIM5_TCCR5A_REG_ADDRESS (0x120)
+#define HAL_LL_TIM5_TCCR5B_REG_ADDRESS (0x121)
+#define HAL_LL_TIM5_TCCR5C_REG_ADDRESS (0x122)
+#define HAL_LL_TIM5_TCNT5H_REG_ADDRESS (0x125)
+#define HAL_LL_TIM5_TCNT5L_REG_ADDRESS (0x124)
+#define HAL_LL_TIM5_ICR5_REG_ADDRESS (0x126)
+#define HAL_LL_TIM5_OCR5AH_REG_ADDRESS (0x129)
+#define HAL_LL_TIM5_OCR5AL_REG_ADDRESS (0x128)
+#define HAL_LL_TIM5_OCR5BH_REG_ADDRESS (0x12b)
+#define HAL_LL_TIM5_OCR5BL_REG_ADDRESS (0x12A)
+#define HAL_LL_TIM5_OCR5CH_REG_ADDRESS (0x12d)
+#define HAL_LL_TIM5_OCR5CL_REG_ADDRESS (0x12C)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+#define __PK0_CN
+#define __PK1_CN
+#define __PK2_CN
+#define __PK3_CN
+#define __PK4_CN
+#define __PK5_CN
+#define __PK6_CN
+#define __PK7_CN
+#define __PL0_CN
+#define __PL1_CN
+#define __PL2_CN
+#define __PL3_CN
+#define __PL4_CN
+#define __PL5_CN
+#define __PL6_CN
+#define __PL7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+#define __PORT_K_CN
+#define __PORT_L_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (11)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+#define PINH_REG_ADDRESS (0x100)
+#define DDRH_REG_ADDRESS (0x101)
+#define PORTH_REG_ADDRESS (0x102)
+#define PINJ_REG_ADDRESS (0x103)
+#define DDRJ_REG_ADDRESS (0x104)
+#define PORTJ_REG_ADDRESS (0x105)
+#define PINK_REG_ADDRESS (0x106)
+#define DDRK_REG_ADDRESS (0x107)
+#define PORTK_REG_ADDRESS (0x108)
+#define PINL_REG_ADDRESS (0x109)
+#define DDRL_REG_ADDRESS (0x10A)
+#define PORTL_REG_ADDRESS (0x10B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_PRR1_REG_ADDRESS (0x65)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (25)
+#define HAL_LL_USART0_UDRE_IVT (26)
+#define HAL_LL_USART0_TX_IVT (27)
+#define HAL_LL_USART1_RX_IVT (36)
+#define HAL_LL_USART1_UDRE_IVT (37)
+#define HAL_LL_USART1_TX_IVT (38)
+#define HAL_LL_USART2_RX_IVT (51)
+#define HAL_LL_USART2_UDRE_IVT (52)
+#define HAL_LL_USART2_TX_IVT (53)
+#define HAL_LL_USART3_RX_IVT (54)
+#define HAL_LL_USART3_UDRE_IVT (55)
+#define HAL_LL_USART3_TX_IVT (56)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x32)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x36)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x48)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x4A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x4C)
+#define HAL_LL_USART2_RX_IVT_ADDRESS (0x66)
+#define HAL_LL_USART2_UDRE_IVT_ADDRESS (0x68)
+#define HAL_LL_USART2_TX_IVT_ADDRESS (0x6A)
+#define HAL_LL_USART3_RX_IVT_ADDRESS (0x6C)
+#define HAL_LL_USART3_UDRE_IVT_ADDRESS (0x6E)
+#define HAL_LL_USART3_TX_IVT_ADDRESS (0x70)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA644/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA644/mcu_definitions.h
new file mode 100644
index 000000000..e09a3555a
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA644/mcu_definitions.h
@@ -0,0 +1,246 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC0
+#define TWI0_SDA_PC1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RX_PD0
+#define USART0_TX_PD1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB6
+#define SPI0_MOSI_PB5
+#define SPI0_SCK_PB7
+#define SPI0_SS_PB4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB3_CH_A
+#define TIM0_PB4_CH_B
+#define TIM1_PD4_CH_B
+#define TIM1_PD5_CH_A
+#define TIM2_PD6_CH_B
+#define TIM2_PD7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (20)
+#define HAL_LL_USART0_UDRE_IVT (21)
+#define HAL_LL_USART0_TX_IVT (22)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x2A)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x2C)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA644A/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA644A/mcu_definitions.h
new file mode 100644
index 000000000..5fa7ba891
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA644A/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC0
+#define TWI0_SDA_PC1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB6
+#define SPI0_MOSI_PB5
+#define SPI0_SCK_PB7
+#define SPI0_SS_PB4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB3_CH_A
+#define TIM0_PB4_CH_B
+#define TIM1_PD4_CH_B
+#define TIM1_PD5_CH_A
+#define TIM2_PD6_CH_B
+#define TIM2_PD7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (20)
+#define HAL_LL_USART0_UDRE_IVT (21)
+#define HAL_LL_USART0_TX_IVT (22)
+#define HAL_LL_USART1_RX_IVT (28)
+#define HAL_LL_USART1_UDRE_IVT (29)
+#define HAL_LL_USART1_TX_IVT (30)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x2A)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x2C)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x38)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x3C)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA644P/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA644P/mcu_definitions.h
new file mode 100644
index 000000000..5fa7ba891
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA644P/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC0
+#define TWI0_SDA_PC1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB6
+#define SPI0_MOSI_PB5
+#define SPI0_SCK_PB7
+#define SPI0_SS_PB4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB3_CH_A
+#define TIM0_PB4_CH_B
+#define TIM1_PD4_CH_B
+#define TIM1_PD5_CH_A
+#define TIM2_PD6_CH_B
+#define TIM2_PD7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (20)
+#define HAL_LL_USART0_UDRE_IVT (21)
+#define HAL_LL_USART0_TX_IVT (22)
+#define HAL_LL_USART1_RX_IVT (28)
+#define HAL_LL_USART1_UDRE_IVT (29)
+#define HAL_LL_USART1_TX_IVT (30)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x2A)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x2C)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x38)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x3C)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA644PA/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA644PA/mcu_definitions.h
new file mode 100644
index 000000000..5fa7ba891
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA644PA/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PC0
+#define TWI0_SDA_PC1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0xB8)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0xB9)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0xBA)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0xBB)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0xBC)
+#define HAL_LL_TWI_TWAMR_REG_ADDRESS (0xBD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PD0
+#define USART0_TXD_PD1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0xC8)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0xC9)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0xCA)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0xCD)
+#define HAL_LL_USART1_UBRR1_REG_ADDRESS (0xCC)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0xCE)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB6
+#define SPI0_MOSI_PB5
+#define SPI0_SCK_PB7
+#define SPI0_SS_PB4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB3_CH_A
+#define TIM0_PB4_CH_B
+#define TIM1_PD4_CH_B
+#define TIM1_PD5_CH_A
+#define TIM2_PD6_CH_B
+#define TIM2_PD7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCCR0B_REG_ADDRESS (0x45)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_OCR0B_REG_ADDRESS (0x48)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCCR2B_REG_ADDRESS (0xB1)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_OCR2B_REG_ADDRESS (0xB4)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (20)
+#define HAL_LL_USART0_UDRE_IVT (21)
+#define HAL_LL_USART0_TX_IVT (22)
+#define HAL_LL_USART1_RX_IVT (28)
+#define HAL_LL_USART1_UDRE_IVT (29)
+#define HAL_LL_USART1_TX_IVT (30)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x2A)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x2C)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x38)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x3C)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA645/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA645/mcu_definitions.h
new file mode 100644
index 000000000..69100c708
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA645/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega645 does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (7)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6450/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6450/mcu_definitions.h
new file mode 100644
index 000000000..a709eaf90
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6450/mcu_definitions.h
@@ -0,0 +1,286 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega6450 does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (9)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (9)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+#define PINH_REG_ADDRESS (0xD8)
+#define DDRH_REG_ADDRESS (0xD9)
+#define PORTH_REG_ADDRESS (0xDA)
+#define PINJ_REG_ADDRESS (0xDB)
+#define DDRJ_REG_ADDRESS (0xDC)
+#define PORTJ_REG_ADDRESS (0xDD)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6450A/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6450A/mcu_definitions.h
new file mode 100644
index 000000000..4c6c6f049
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6450A/mcu_definitions.h
@@ -0,0 +1,286 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega6450A does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (9)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (9)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+#define PINH_REG_ADDRESS (0xD8)
+#define DDRH_REG_ADDRESS (0xD9)
+#define PORTH_REG_ADDRESS (0xDA)
+#define PINJ_REG_ADDRESS (0xDB)
+#define DDRJ_REG_ADDRESS (0xDC)
+#define PORTJ_REG_ADDRESS (0xDD)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6450P/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6450P/mcu_definitions.h
new file mode 100644
index 000000000..4b283bb95
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6450P/mcu_definitions.h
@@ -0,0 +1,286 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega6450P does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (9)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (9)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+#define PINH_REG_ADDRESS (0xD8)
+#define DDRH_REG_ADDRESS (0xD9)
+#define PORTH_REG_ADDRESS (0xDA)
+#define PINJ_REG_ADDRESS (0xDB)
+#define DDRJ_REG_ADDRESS (0xDC)
+#define PORTJ_REG_ADDRESS (0xDD)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA645A/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA645A/mcu_definitions.h
new file mode 100644
index 000000000..7c5ecaa51
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA645A/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega645A does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (7)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA645P/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA645P/mcu_definitions.h
new file mode 100644
index 000000000..7cad4a935
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA645P/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega645P does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (7)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA649/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA649/mcu_definitions.h
new file mode 100644
index 000000000..113498cdd
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA649/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega649 does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (7)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB4_CH_A
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM2_PB7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6490/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6490/mcu_definitions.h
new file mode 100644
index 000000000..23dd4e4a3
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6490/mcu_definitions.h
@@ -0,0 +1,286 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega6490 does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (9)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (9)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+#define PINH_REG_ADDRESS (0xD8)
+#define DDRH_REG_ADDRESS (0xD9)
+#define PORTH_REG_ADDRESS (0xDA)
+#define PINJ_REG_ADDRESS (0xDB)
+#define DDRJ_REG_ADDRESS (0xDC)
+#define PORTJ_REG_ADDRESS (0xDD)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6490A/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6490A/mcu_definitions.h
new file mode 100644
index 000000000..4f73f5f06
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6490A/mcu_definitions.h
@@ -0,0 +1,286 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega6490A does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (9)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (9)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+#define PINH_REG_ADDRESS (0xD8)
+#define DDRH_REG_ADDRESS (0xD9)
+#define PORTH_REG_ADDRESS (0xDA)
+#define PINJ_REG_ADDRESS (0xDB)
+#define DDRJ_REG_ADDRESS (0xDC)
+#define PORTJ_REG_ADDRESS (0xDD)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6490P/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6490P/mcu_definitions.h
new file mode 100644
index 000000000..beb184052
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA6490P/mcu_definitions.h
@@ -0,0 +1,286 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x7B)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADCL_REG_ADDRESS)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega6490P does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (9)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PB0
+#define SPI0_SCK_PB1
+#define SPI0_MOSI_PB2
+#define SPI0_MISO_PB3
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// 8-bit Timer/Counter2
+#define TIM2_PB7_CH_A
+// 16-bit Timer/Counter1
+#define TIM1_PB6_CH_B
+// 16-bit Timer/Counter1
+#define TIM1_PB5_CH_A
+// 8-bit Timer/Counter0
+#define TIM0_PB4_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (9)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+#define PINH_REG_ADDRESS (0xD8)
+#define DDRH_REG_ADDRESS (0xD9)
+#define PORTH_REG_ADDRESS (0xDA)
+#define PINJ_REG_ADDRESS (0xDB)
+#define DDRJ_REG_ADDRESS (0xDC)
+#define PORTJ_REG_ADDRESS (0xDD)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA649A/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA649A/mcu_definitions.h
new file mode 100644
index 000000000..58876d3a7
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA649A/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega649A does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (7)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB4_CH_A
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM2_PB7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA649P/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA649P/mcu_definitions.h
new file mode 100644
index 000000000..1c0a6266c
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA649P/mcu_definitions.h
@@ -0,0 +1,262 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x79)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x78)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x7A)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x7C)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+// ATmega649P does not have hardware I2C/TWI module
+// Number of modules equals number of available ports
+#define TWI_MODULE_HW (false)
+#define TWI_MODULE_COUNT (7)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0xC0)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0xC1)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0xC2)
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0xC5)
+#define HAL_LL_USART0_UBRR0_REG_ADDRESS (0xC4)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0xC6)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x4C)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x4D)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x4E)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB4_CH_A
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM2_PB7_CH_A
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_TIFR0_REG_ADDRESS (0x35)
+#define HAL_LL_TIM1_TIFR1_REG_ADDRESS (0x36)
+#define HAL_LL_TIM2_TIFR2_REG_ADDRESS (0x37)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x44)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x46)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x47)
+#define HAL_LL_TIM0_TIMSK0_REG_ADDRESS (0x6E)
+#define HAL_LL_TIM1_TIMSK1_REG_ADDRESS (0x6F)
+#define HAL_LL_TIM2_TIMSK2_REG_ADDRESS (0x70)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x80)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x81)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x82)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x85)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x84)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x86)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x89)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x88)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x8b)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0xB0)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0xB2)
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0xB3)
+#define HAL_LL_TIM2_ASSR_REG_ADDRESS (0xB6)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINA_REG_ADDRESS (0x20)
+#define DDRA_REG_ADDRESS (0x21)
+#define PORTA_REG_ADDRESS (0x22)
+#define PINB_REG_ADDRESS (0x23)
+#define DDRB_REG_ADDRESS (0x24)
+#define PORTB_REG_ADDRESS (0x25)
+#define PINC_REG_ADDRESS (0x26)
+#define DDRC_REG_ADDRESS (0x27)
+#define PORTC_REG_ADDRESS (0x28)
+#define PIND_REG_ADDRESS (0x29)
+#define DDRD_REG_ADDRESS (0x2A)
+#define PORTD_REG_ADDRESS (0x2B)
+#define PINE_REG_ADDRESS (0x2C)
+#define DDRE_REG_ADDRESS (0x2D)
+#define PORTE_REG_ADDRESS (0x2E)
+#define PINF_REG_ADDRESS (0x2F)
+#define DDRF_REG_ADDRESS (0x30)
+#define PORTF_REG_ADDRESS (0x31)
+#define PING_REG_ADDRESS (0x32)
+#define DDRG_REG_ADDRESS (0x33)
+#define PORTG_REG_ADDRESS (0x34)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRR0_REG_ADDRESS (0x64)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (13)
+#define HAL_LL_USART0_UDRE_IVT (14)
+#define HAL_LL_USART0_TX_IVT (15)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x1A)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x1C)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x1E)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA64A/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA64A/mcu_definitions.h
new file mode 100644
index 000000000..00f0dd979
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATMEGA64A/mcu_definitions.h
@@ -0,0 +1,299 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PF0_CH0
+#define ADC0_PF1_CH1
+#define ADC0_PF2_CH2
+#define ADC0_PF3_CH3
+#define ADC0_PF4_CH4
+#define ADC0_PF5_CH5
+#define ADC0_PF6_CH6
+#define ADC0_PF7_CH7
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_ADCL_REG_ADDRESS (0x24)
+#define HAL_LL_ADC0_ADCH_REG_ADDRESS (0x25)
+#define HAL_LL_ADC0_ADC_REG_ADDRESS (0x24)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_ADC_REG_ADDRESS)
+#define HAL_LL_ADC0_ADCSRA_REG_ADDRESS (0x26)
+#define HAL_LL_ADC0_ADMUX_REG_ADDRESS (0x27)
+#define HAL_LL_ADC0_ADCSRB_REG_ADDRESS (0x8E)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWI0_SCL_PD0
+#define TWI0_SDA_PD1
+
+#define TWI_MODULE_0 (1)
+#define I2C_MODULE_0 (TWI_MODULE_0)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWI_TWBR_REG_ADDRESS (0x70)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWI_TWBR_REG_ADDRESS)
+#define HAL_LL_TWI_TWSR_REG_ADDRESS (0x71)
+#define HAL_LL_TWI_TWAR_REG_ADDRESS (0x72)
+#define HAL_LL_TWI_TWDR_REG_ADDRESS (0x73)
+#define HAL_LL_TWI_TWCR_REG_ADDRESS (0x74)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USART0_RXD_PE0
+#define USART0_TXD_PE1
+#define USART1_RXD_PD2
+#define USART1_TXD_PD3
+
+#define UART_MODULE_0 (1)
+#define UART_MODULE_1 (2)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USART0_UBRR0L_REG_ADDRESS (0x29)
+#define HAL_LL_USART0_UCSR0B_REG_ADDRESS (0x2A)
+#define HAL_LL_USART0_UCSR0A_REG_ADDRESS (0x2B)
+#define HAL_LL_USART0_UDR0_REG_ADDRESS (0x2C)
+#define HAL_LL_USART0_UBRR0H_REG_ADDRESS (0x90)
+#define HAL_LL_USART0_UCSR0C_REG_ADDRESS (0x95)
+#define HAL_LL_USART1_UBRR1H_REG_ADDRESS (0x98)
+#define HAL_LL_USART1_UBRR1L_REG_ADDRESS (0x99)
+#define HAL_LL_USART1_UCSR1B_REG_ADDRESS (0x9A)
+#define HAL_LL_USART1_UCSR1A_REG_ADDRESS (0x9B)
+#define HAL_LL_USART1_UDR1_REG_ADDRESS (0x9C)
+#define HAL_LL_USART1_UCSR1C_REG_ADDRESS (0x9D)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PB3
+#define SPI0_MOSI_PB2
+#define SPI0_SCK_PB1
+#define SPI0_SS_PB0
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_SPCR_REG_ADDRESS (0x2D)
+#define HAL_LL_SPI0_SPSR_REG_ADDRESS (0x2E)
+#define HAL_LL_SPI0_SPDR_REG_ADDRESS (0x2F)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PB4_CH_NONE
+#define TIM1_PB5_CH_A
+#define TIM1_PB6_CH_B
+#define TIM1_PB7_CH_C
+#define TIM2_PB7_CH_NONE
+#define TIM3_PE3_CH_A
+#define TIM3_PE4_CH_B
+#define TIM3_PE5_CH_C
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM2_OCR2A_REG_ADDRESS (0x43)
+#define HAL_LL_TIM2_TCNT2_REG_ADDRESS (0x44)
+#define HAL_LL_TIM2_TCCR2A_REG_ADDRESS (0x45)
+#define HAL_LL_TIM1_ICR1_REG_ADDRESS (0x46)
+#define HAL_LL_TIM1_OCR1BH_REG_ADDRESS (0x49)
+#define HAL_LL_TIM1_OCR1BL_REG_ADDRESS (0x48)
+#define HAL_LL_TIM1_OCR1AH_REG_ADDRESS (0x4b)
+#define HAL_LL_TIM1_OCR1AL_REG_ADDRESS (0x4A)
+#define HAL_LL_TIM1_TCNT1H_REG_ADDRESS (0x4d)
+#define HAL_LL_TIM1_TCNT1L_REG_ADDRESS (0x4C)
+#define HAL_LL_TIM1_TCCR1B_REG_ADDRESS (0x4E)
+#define HAL_LL_TIM1_TCCR1A_REG_ADDRESS (0x4F)
+#define HAL_LL_TIM0_ASSR_REG_ADDRESS (0x50)
+#define HAL_LL_TIM0_OCR0A_REG_ADDRESS (0x51)
+#define HAL_LL_TIM0_TCNT0_REG_ADDRESS (0x52)
+#define HAL_LL_TIM0_TCCR0A_REG_ADDRESS (0x53)
+#define HAL_LL_TIM1_OCR1CH_REG_ADDRESS (0x79)
+#define HAL_LL_TIM1_OCR1CL_REG_ADDRESS (0x78)
+#define HAL_LL_TIM1_TCCR1C_REG_ADDRESS (0x7A)
+#define HAL_LL_TIM3_ICR3_REG_ADDRESS (0x80)
+#define HAL_LL_TIM3_OCR3CH_REG_ADDRESS (0x83)
+#define HAL_LL_TIM3_OCR3CL_REG_ADDRESS (0x82)
+#define HAL_LL_TIM3_OCR3BH_REG_ADDRESS (0x85)
+#define HAL_LL_TIM3_OCR3BL_REG_ADDRESS (0x84)
+#define HAL_LL_TIM3_OCR3AH_REG_ADDRESS (0x87)
+#define HAL_LL_TIM3_OCR3AL_REG_ADDRESS (0x86)
+#define HAL_LL_TIM3_TCNT3H_REG_ADDRESS (0x89)
+#define HAL_LL_TIM3_TCNT3L_REG_ADDRESS (0x88)
+#define HAL_LL_TIM3_TCCR3B_REG_ADDRESS (0x8A)
+#define HAL_LL_TIM3_TCCR3A_REG_ADDRESS (0x8B)
+#define HAL_LL_TIM3_TCCR3C_REG_ADDRESS (0x8C)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_G_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define PINF_REG_ADDRESS (0x20)
+#define PINE_REG_ADDRESS (0x21)
+#define DDRE_REG_ADDRESS (0x22)
+#define PORTE_REG_ADDRESS (0x23)
+#define PIND_REG_ADDRESS (0x30)
+#define DDRD_REG_ADDRESS (0x31)
+#define PORTD_REG_ADDRESS (0x32)
+#define PINC_REG_ADDRESS (0x33)
+#define DDRC_REG_ADDRESS (0x34)
+#define PORTC_REG_ADDRESS (0x35)
+#define PINB_REG_ADDRESS (0x36)
+#define DDRB_REG_ADDRESS (0x37)
+#define PORTB_REG_ADDRESS (0x38)
+#define PINA_REG_ADDRESS (0x39)
+#define DDRA_REG_ADDRESS (0x3A)
+#define PORTA_REG_ADDRESS (0x3B)
+#define DDRF_REG_ADDRESS (0x61)
+#define PORTF_REG_ADDRESS (0x62)
+#define PING_REG_ADDRESS (0x63)
+#define DDRG_REG_ADDRESS (0x64)
+#define PORTG_REG_ADDRESS (0x65)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_POWER_REDUCTION (false)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USART0_RX_IVT (18)
+#define HAL_LL_USART0_UDRE_IVT (19)
+#define HAL_LL_USART0_TX_IVT (20)
+#define HAL_LL_USART1_RX_IVT (30)
+#define HAL_LL_USART1_UDRE_IVT (31)
+#define HAL_LL_USART1_TX_IVT (32)
+// IVT ADDRESSES
+#define HAL_LL_USART0_RX_IVT_ADDRESS (0x24)
+#define HAL_LL_USART0_UDRE_IVT_ADDRESS (0x26)
+#define HAL_LL_USART0_TX_IVT_ADDRESS (0x28)
+#define HAL_LL_USART1_RX_IVT_ADDRESS (0x3C)
+#define HAL_LL_USART1_UDRE_IVT_ADDRESS (0x3E)
+#define HAL_LL_USART1_TX_IVT_ADDRESS (0x40)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128A1U/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128A1U/mcu_definitions.h
new file mode 100644
index 000000000..6c995df11
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128A1U/mcu_definitions.h
@@ -0,0 +1,837 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH0
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH1
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB2_CH2
+#define ADC0_PB3_CH11
+#define ADC0_PB3_CH3
+#define ADC0_PB4_CH12
+#define ADC0_PB4_CH4
+#define ADC0_PB5_CH13
+#define ADC0_PB5_CH5
+#define ADC0_PB6_CH14
+#define ADC0_PB6_CH6
+#define ADC0_PB7_CH15
+#define ADC0_PB7_CH7
+#define ADC1_PA0_CH0
+#define ADC1_PB0_CH0
+#define ADC1_PB0_CH8
+#define ADC1_PB1_CH1
+#define ADC1_PB1_CH9
+#define ADC1_PB2_CH10
+#define ADC1_PB2_CH2
+#define ADC1_PB3_CH11
+#define ADC1_PB3_CH3
+#define ADC1_PB4_CH12
+#define ADC1_PB4_CH4
+#define ADC1_PB5_CH13
+#define ADC1_PB5_CH5
+#define ADC1_PB6_CH14
+#define ADC1_PB6_CH6
+#define ADC1_PB7_CH15
+#define ADC1_PB7_CH7
+
+#define ADC_MODULE_0 (1)
+#define ADC_MODULE_1 (2)
+
+#define HAL_LL_AN_COUNT (41)
+#define ADC_MODULE_COUNT (2)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+#define HAL_LL_ADC1_CTRLA_REG_ADDRESS (0x240)
+#define HAL_LL_ADC1_BASE_ADDRESS (HAL_LL_ADC1_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC1_CTRLB_REG_ADDRESS (0x241)
+#define HAL_LL_ADC1_REFCTRL_REG_ADDRESS (0x242)
+#define HAL_LL_ADC1_EVCTRL_REG_ADDRESS (0x243)
+#define HAL_LL_ADC1_PRESCALER_REG_ADDRESS (0x244)
+#define HAL_LL_ADC1_INTFLAGS_REG_ADDRESS (0x246)
+#define HAL_LL_ADC1_TEMP_REG_ADDRESS (0x247)
+#define HAL_LL_ADC1_CH0RESL_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0RESH_REG_ADDRESS (0x251)
+#define HAL_LL_ADC1_CH0RES_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH1RESL_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH1RESH_REG_ADDRESS (0x253)
+#define HAL_LL_ADC1_CH1RES_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH2RESL_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH2RESH_REG_ADDRESS (0x255)
+#define HAL_LL_ADC1_CH2RES_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH3RESL_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH3RESH_REG_ADDRESS (0x257)
+#define HAL_LL_ADC1_CH3RES_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH0CTRL_REG_ADDRESS (0x260)
+#define HAL_LL_ADC1_CH0MUXCTRL_REG_ADDRESS (0x261)
+#define HAL_LL_ADC1_CH0INTCTRL_REG_ADDRESS (0x262)
+#define HAL_LL_ADC1_CH0INTFLAGS_REG_ADDRESS (0x263)
+#define HAL_LL_ADC1_CH1CTRL_REG_ADDRESS (0x268)
+#define HAL_LL_ADC1_CH1MUXCTRL_REG_ADDRESS (0x269)
+#define HAL_LL_ADC1_CH1INTCTRL_REG_ADDRESS (0x26A)
+#define HAL_LL_ADC1_CH1INTFLAGS_REG_ADDRESS (0x26B)
+#define HAL_LL_ADC1_CH2CTRL_REG_ADDRESS (0x270)
+#define HAL_LL_ADC1_CH2MUXCTRL_REG_ADDRESS (0x271)
+#define HAL_LL_ADC1_CH2INTCTRL_REG_ADDRESS (0x272)
+#define HAL_LL_ADC1_CH2INTFLAGS_REG_ADDRESS (0x273)
+#define HAL_LL_ADC1_CH3CTRL_REG_ADDRESS (0x278)
+#define HAL_LL_ADC1_CH3MUXCTRL_REG_ADDRESS (0x279)
+#define HAL_LL_ADC1_CH3INTCTRL_REG_ADDRESS (0x27A)
+#define HAL_LL_ADC1_CH3INTFLAGS_REG_ADDRESS (0x27B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWID_SCL_PD1
+#define TWID_SDA_PD0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+#define TWIF_SCL_PF1
+#define TWIF_SDA_PF0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_D (2)
+#define I2C_MODULE_1 (TWI_MODULE_D)
+#define TWI_MODULE_E (3)
+#define I2C_MODULE_2 (TWI_MODULE_E)
+#define TWI_MODULE_F (4)
+#define I2C_MODULE_3 (TWI_MODULE_F)
+#define TWI_MODULE_COUNT (4)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWID_CTRL_REG_ADDRESS (0x490)
+#define HAL_LL_I2C1_BASE_ADDRESS (HAL_LL_TWID_CTRL_REG_ADDRESS)
+#define HAL_LL_TWID_MASTERCTRLA_REG_ADDRESS (0x491)
+#define HAL_LL_TWID_MASTERCTRLB_REG_ADDRESS (0x492)
+#define HAL_LL_TWID_MASTERCTRLC_REG_ADDRESS (0x493)
+#define HAL_LL_TWID_MASTERSTATUS_REG_ADDRESS (0x494)
+#define HAL_LL_TWID_MASTERBAUD_REG_ADDRESS (0x495)
+#define HAL_LL_TWID_MASTERADDR_REG_ADDRESS (0x496)
+#define HAL_LL_TWID_MASTERDATA_REG_ADDRESS (0x497)
+#define HAL_LL_TWID_SLAVECTRLA_REG_ADDRESS (0x498)
+#define HAL_LL_TWID_SLAVECTRLB_REG_ADDRESS (0x499)
+#define HAL_LL_TWID_SLAVESTATUS_REG_ADDRESS (0x49A)
+#define HAL_LL_TWID_SLAVEADDR_REG_ADDRESS (0x49B)
+#define HAL_LL_TWID_SLAVEDATA_REG_ADDRESS (0x49C)
+#define HAL_LL_TWID_SLAVEADDRMASK_REG_ADDRESS (0x49D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+#define HAL_LL_TWIF_CTRL_REG_ADDRESS (0x4B0)
+#define HAL_LL_I2C3_BASE_ADDRESS (HAL_LL_TWIF_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIF_MASTERCTRLA_REG_ADDRESS (0x4B1)
+#define HAL_LL_TWIF_MASTERCTRLB_REG_ADDRESS (0x4B2)
+#define HAL_LL_TWIF_MASTERCTRLC_REG_ADDRESS (0x4B3)
+#define HAL_LL_TWIF_MASTERSTATUS_REG_ADDRESS (0x4B4)
+#define HAL_LL_TWIF_MASTERBAUD_REG_ADDRESS (0x4B5)
+#define HAL_LL_TWIF_MASTERADDR_REG_ADDRESS (0x4B6)
+#define HAL_LL_TWIF_MASTERDATA_REG_ADDRESS (0x4B7)
+#define HAL_LL_TWIF_SLAVECTRLA_REG_ADDRESS (0x4B8)
+#define HAL_LL_TWIF_SLAVECTRLB_REG_ADDRESS (0x4B9)
+#define HAL_LL_TWIF_SLAVESTATUS_REG_ADDRESS (0x4BA)
+#define HAL_LL_TWIF_SLAVEADDR_REG_ADDRESS (0x4BB)
+#define HAL_LL_TWIF_SLAVEDATA_REG_ADDRESS (0x4BC)
+#define HAL_LL_TWIF_SLAVEADDRMASK_REG_ADDRESS (0x4BD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+#define USARTE1_RXD_PE6
+#define USARTE1_TXD_PE7
+#define USARTF0_RXD_PF2
+#define USARTF0_TXD_PF3
+#define USARTF1_RXD_PF6
+#define USARTF1_TXD_PF7
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_E1 (6)
+#define UART_MODULE_5 (UART_MODULE_E1)
+#define UART_MODULE_F0 (7)
+#define UART_MODULE_6 (UART_MODULE_F0)
+#define UART_MODULE_F1 (8)
+#define UART_MODULE_7 (UART_MODULE_F1)
+#define UART_MODULE_COUNT (8)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+#define HAL_LL_USARTE1_DATA_REG_ADDRESS (0xAB0)
+#define HAL_LL_USARTE1_STATUS_REG_ADDRESS (0xAB1)
+#define HAL_LL_USARTE1_CTRLA_REG_ADDRESS (0xAB3)
+#define HAL_LL_USARTE1_CTRLB_REG_ADDRESS (0xAB4)
+#define HAL_LL_USARTE1_CTRLC_REG_ADDRESS (0xAB5)
+#define HAL_LL_USARTE1_BAUDCTRLA_REG_ADDRESS (0xAB6)
+#define HAL_LL_USARTE1_BAUDCTRLB_REG_ADDRESS (0xAB7)
+#define HAL_LL_USARTF0_DATA_REG_ADDRESS (0xBA0)
+#define HAL_LL_USARTF0_STATUS_REG_ADDRESS (0xBA1)
+#define HAL_LL_USARTF0_CTRLA_REG_ADDRESS (0xBA3)
+#define HAL_LL_USARTF0_CTRLB_REG_ADDRESS (0xBA4)
+#define HAL_LL_USARTF0_CTRLC_REG_ADDRESS (0xBA5)
+#define HAL_LL_USARTF0_BAUDCTRLA_REG_ADDRESS (0xBA6)
+#define HAL_LL_USARTF0_BAUDCTRLB_REG_ADDRESS (0xBA7)
+#define HAL_LL_USARTF1_DATA_REG_ADDRESS (0xBB0)
+#define HAL_LL_USARTF1_STATUS_REG_ADDRESS (0xBB1)
+#define HAL_LL_USARTF1_CTRLA_REG_ADDRESS (0xBB3)
+#define HAL_LL_USARTF1_CTRLB_REG_ADDRESS (0xBB4)
+#define HAL_LL_USARTF1_CTRLC_REG_ADDRESS (0xBB5)
+#define HAL_LL_USARTF1_BAUDCTRLA_REG_ADDRESS (0xBB6)
+#define HAL_LL_USARTF1_BAUDCTRLB_REG_ADDRESS (0xBB7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+#define SPI2_MISO_PE6
+#define SPI2_MOSI_PE5
+#define SPI2_SCK_PE7
+#define SPI2_SS_PE4
+#define SPI3_MISO_PF6
+#define SPI3_MOSI_PF5
+#define SPI3_SCK_PF7
+#define SPI3_SS_PF4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_2 (3)
+#define SPI_MODULE_3 (4)
+#define SPI_MODULE_COUNT (4)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+#define HAL_LL_SPI2_CTRL_REG_ADDRESS (0xAC0)
+#define HAL_LL_SPI2_INTCTRL_REG_ADDRESS (0xAC1)
+#define HAL_LL_SPI2_STATUS_REG_ADDRESS (0xAC2)
+#define HAL_LL_SPI2_DATA_REG_ADDRESS (0xAC3)
+#define HAL_LL_SPI3_CTRL_REG_ADDRESS (0xBC0)
+#define HAL_LL_SPI3_INTCTRL_REG_ADDRESS (0xBC1)
+#define HAL_LL_SPI3_STATUS_REG_ADDRESS (0xBC2)
+#define HAL_LL_SPI3_DATA_REG_ADDRESS (0xBC3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+#define TIM0_PC4_CH_A
+#define TIM0_PC5_CH_B
+#define TIM0_PC6_CH_C
+#define TIM0_PC7_CH_D
+#define TIM1_PC4_CH_A
+#define TIM1_PC5_CH_B
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+#define TIM6_PE4_CH_A
+#define TIM6_PE5_CH_B
+#define TIM7_PF4_CH_A
+#define TIM7_PF5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_5 (5)
+#define TIM_MODULE_6 (6)
+#define TIM_MODULE_7 (7)
+#define TIM_MODULE_COUNT (7)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x94A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x94B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x94C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x94F)
+#define HAL_LL_TIM5_CNT_REG_ADDRESS (0x960)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x967)
+#define HAL_LL_TIM5_PER_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_CCA_REG_ADDRESS (0x968)
+#define HAL_LL_TIM5_CCB_REG_ADDRESS (0x96A)
+#define HAL_LL_TIM5_PERBUF_REG_ADDRESS (0x976)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x978)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x97A)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM6_CTRLA_REG_ADDRESS (0xA40)
+#define HAL_LL_TIM6_CTRLB_REG_ADDRESS (0xA41)
+#define HAL_LL_TIM6_CTRLC_REG_ADDRESS (0xA42)
+#define HAL_LL_TIM6_CTRLD_REG_ADDRESS (0xA43)
+#define HAL_LL_TIM6_CTRLE_REG_ADDRESS (0xA44)
+#define HAL_LL_TIM6_INTCTRLA_REG_ADDRESS (0xA46)
+#define HAL_LL_TIM6_INTCTRLB_REG_ADDRESS (0xA47)
+#define HAL_LL_TIM6_CTRLFCLR_REG_ADDRESS (0xA48)
+#define HAL_LL_TIM6_CTRLFSET_REG_ADDRESS (0xA49)
+#define HAL_LL_TIM6_CTRLGCLR_REG_ADDRESS (0xA4A)
+#define HAL_LL_TIM6_CTRLGSET_REG_ADDRESS (0xA4B)
+#define HAL_LL_TIM6_INTFLAGS_REG_ADDRESS (0xA4C)
+#define HAL_LL_TIM6_TEMP_REG_ADDRESS (0xA4F)
+#define HAL_LL_TIM6_CNT_REG_ADDRESS (0xA60)
+#define HAL_LL_TIM6_PERL_REG_ADDRESS (0xA66)
+#define HAL_LL_TIM6_PERH_REG_ADDRESS (0xA67)
+#define HAL_LL_TIM6_PER_REG_ADDRESS (0xA66)
+#define HAL_LL_TIM6_CCA_REG_ADDRESS (0xA68)
+#define HAL_LL_TIM6_CCB_REG_ADDRESS (0xA6A)
+#define HAL_LL_TIM6_PERBUF_REG_ADDRESS (0xA76)
+#define HAL_LL_TIM6_CCABUF_REG_ADDRESS (0xA78)
+#define HAL_LL_TIM6_CCBBUF_REG_ADDRESS (0xA7A)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0xB00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0xB01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0xB02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0xB03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0xB04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0xB06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0xB07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0xB08)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0xB0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0xB0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0xB0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0xB0F)
+#define HAL_LL_TIM3_PERBUF_REG_ADDRESS (0xB36)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0xB38)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0xB3A)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0xB3C)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0xB3E)
+#define HAL_LL_TIM7_CTRLA_REG_ADDRESS (0xB40)
+#define HAL_LL_TIM7_CTRLB_REG_ADDRESS (0xB41)
+#define HAL_LL_TIM7_CTRLC_REG_ADDRESS (0xB42)
+#define HAL_LL_TIM7_CTRLD_REG_ADDRESS (0xB43)
+#define HAL_LL_TIM7_CTRLE_REG_ADDRESS (0xB44)
+#define HAL_LL_TIM7_INTCTRLA_REG_ADDRESS (0xB46)
+#define HAL_LL_TIM7_INTCTRLB_REG_ADDRESS (0xB47)
+#define HAL_LL_TIM7_CTRLFCLR_REG_ADDRESS (0xB48)
+#define HAL_LL_TIM7_CTRLFSET_REG_ADDRESS (0xB49)
+#define HAL_LL_TIM7_CTRLGCLR_REG_ADDRESS (0xB4A)
+#define HAL_LL_TIM7_CTRLGSET_REG_ADDRESS (0xB4B)
+#define HAL_LL_TIM7_INTFLAGS_REG_ADDRESS (0xB4C)
+#define HAL_LL_TIM7_TEMP_REG_ADDRESS (0xB4F)
+#define HAL_LL_TIM7_CNT_REG_ADDRESS (0xB60)
+#define HAL_LL_TIM7_PERL_REG_ADDRESS (0xB66)
+#define HAL_LL_TIM7_PERH_REG_ADDRESS (0xB67)
+#define HAL_LL_TIM7_PER_REG_ADDRESS (0xB66)
+#define HAL_LL_TIM7_CCA_REG_ADDRESS (0xB68)
+#define HAL_LL_TIM7_CCB_REG_ADDRESS (0xB6A)
+#define HAL_LL_TIM7_PERBUF_REG_ADDRESS (0xB76)
+#define HAL_LL_TIM7_CCABUF_REG_ADDRESS (0xB78)
+#define HAL_LL_TIM7_CCBBUF_REG_ADDRESS (0xB7A)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM3_CNT_REG_ADDRESS (0xB20)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0xB26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0xB27)
+#define HAL_LL_TIM3_CCA_REG_ADDRESS (0xB28)
+#define HAL_LL_TIM3_CCB_REG_ADDRESS (0xB2A)
+#define HAL_LL_TIM3_CCC_REG_ADDRESS (0xB2C)
+#define HAL_LL_TIM3_CCD_REG_ADDRESS (0xB2E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+#define __PK0_CN
+#define __PK1_CN
+#define __PK2_CN
+#define __PK3_CN
+#define __PK4_CN
+#define __PK5_CN
+#define __PK6_CN
+#define __PK7_CN
+#define __PQ0_CN
+#define __PQ1_CN
+#define __PQ2_CN
+#define __PQ3_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+#define __PORT_K_CN
+#define __PORT_Q_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (11)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRH_REG_ADDRESS (0x6E0)
+#define PORTH_REG_ADDRESS (0x6E4)
+#define PINH_REG_ADDRESS (0x6E8)
+#define DDRJ_REG_ADDRESS (0x700)
+#define PORTJ_REG_ADDRESS (0x704)
+#define PINJ_REG_ADDRESS (0x708)
+#define DDRK_REG_ADDRESS (0x720)
+#define PORTK_REG_ADDRESS (0x724)
+#define PINK_REG_ADDRESS (0x728)
+#define DDRQ_REG_ADDRESS (0x7C0)
+#define PORTQ_REG_ADDRESS (0x7C4)
+#define PINQ_REG_ADDRESS (0x7C8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTF_REMAP_REG_ADDRESS (0x6AE)
+#define PORTH_REMAP_REG_ADDRESS (0x6EE)
+#define PORTJ_REMAP_REG_ADDRESS (0x70E)
+#define PORTK_REMAP_REG_ADDRESS (0x72E)
+#define PORTQ_REMAP_REG_ADDRESS (0x7CE)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTE1_RXC_IVT (61)
+#define HAL_LL_USARTE1_DRE_IVT (62)
+#define HAL_LL_USARTE1_TXC_IVT (63)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+#define HAL_LL_USARTF0_RXC_IVT (119)
+#define HAL_LL_USARTF0_DRE_IVT (120)
+#define HAL_LL_USARTF0_TXC_IVT (121)
+#define HAL_LL_USARTF1_RXC_IVT (122)
+#define HAL_LL_USARTF1_DRE_IVT (123)
+#define HAL_LL_USARTF1_TXC_IVT (124)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTE1_RXC_IVT_ADDRESS (0x7A)
+#define HAL_LL_USARTE1_DRE_IVT_ADDRESS (0x7C)
+#define HAL_LL_USARTE1_TXC_IVT_ADDRESS (0x7E)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+#define HAL_LL_USARTF0_RXC_IVT_ADDRESS (0xEE)
+#define HAL_LL_USARTF0_DRE_IVT_ADDRESS (0xF0)
+#define HAL_LL_USARTF0_TXC_IVT_ADDRESS (0xF2)
+#define HAL_LL_USARTF1_RXC_IVT_ADDRESS (0xF4)
+#define HAL_LL_USARTF1_DRE_IVT_ADDRESS (0xF6)
+#define HAL_LL_USARTF1_TXC_IVT_ADDRESS (0xF8)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128A3/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128A3/mcu_definitions.h
new file mode 100644
index 000000000..4183b74d5
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128A3/mcu_definitions.h
@@ -0,0 +1,752 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC1_PB0_CH0
+#define ADC1_PB1_CH1
+#define ADC1_PB2_CH2
+#define ADC1_PB3_CH3
+#define ADC1_PB4_CH4
+#define ADC1_PB5_CH5
+#define ADC1_PB6_CH6
+#define ADC1_PB7_CH7
+
+#define ADC_MODULE_0 (1)
+#define ADC_MODULE_1 (2)
+
+#define HAL_LL_AN_COUNT (16)
+#define ADC_MODULE_COUNT (2)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+#define HAL_LL_ADC1_CTRLA_REG_ADDRESS (0x240)
+#define HAL_LL_ADC1_BASE_ADDRESS (HAL_LL_ADC1_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC1_CTRLB_REG_ADDRESS (0x241)
+#define HAL_LL_ADC1_REFCTRL_REG_ADDRESS (0x242)
+#define HAL_LL_ADC1_EVCTRL_REG_ADDRESS (0x243)
+#define HAL_LL_ADC1_PRESCALER_REG_ADDRESS (0x244)
+#define HAL_LL_ADC1_INTFLAGS_REG_ADDRESS (0x246)
+#define HAL_LL_ADC1_TEMP_REG_ADDRESS (0x247)
+#define HAL_LL_ADC1_CH0RESL_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0RESH_REG_ADDRESS (0x251)
+#define HAL_LL_ADC1_CH0RES_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH1RESL_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH1RESH_REG_ADDRESS (0x253)
+#define HAL_LL_ADC1_CH1RES_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH2RESL_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH2RESH_REG_ADDRESS (0x255)
+#define HAL_LL_ADC1_CH2RES_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH3RESL_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH3RESH_REG_ADDRESS (0x257)
+#define HAL_LL_ADC1_CH3RES_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH0CTRL_REG_ADDRESS (0x260)
+#define HAL_LL_ADC1_CH0MUXCTRL_REG_ADDRESS (0x261)
+#define HAL_LL_ADC1_CH0INTCTRL_REG_ADDRESS (0x262)
+#define HAL_LL_ADC1_CH0INTFLAGS_REG_ADDRESS (0x263)
+#define HAL_LL_ADC1_CH1CTRL_REG_ADDRESS (0x268)
+#define HAL_LL_ADC1_CH1MUXCTRL_REG_ADDRESS (0x269)
+#define HAL_LL_ADC1_CH1INTCTRL_REG_ADDRESS (0x26A)
+#define HAL_LL_ADC1_CH1INTFLAGS_REG_ADDRESS (0x26B)
+#define HAL_LL_ADC1_CH2CTRL_REG_ADDRESS (0x270)
+#define HAL_LL_ADC1_CH2MUXCTRL_REG_ADDRESS (0x271)
+#define HAL_LL_ADC1_CH2INTCTRL_REG_ADDRESS (0x272)
+#define HAL_LL_ADC1_CH2INTFLAGS_REG_ADDRESS (0x273)
+#define HAL_LL_ADC1_CH3CTRL_REG_ADDRESS (0x278)
+#define HAL_LL_ADC1_CH3MUXCTRL_REG_ADDRESS (0x279)
+#define HAL_LL_ADC1_CH3INTCTRL_REG_ADDRESS (0x27A)
+#define HAL_LL_ADC1_CH3INTFLAGS_REG_ADDRESS (0x27B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_TXD_PC3
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+#define USARTE1_RXD_PE6
+#define USARTE1_TXD_PE7
+#define USARTF0_RXD_PF2
+#define USARTF0_TXD_PF3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_E1 (6)
+#define UART_MODULE_5 (UART_MODULE_E1)
+#define UART_MODULE_F0 (7)
+#define UART_MODULE_6 (UART_MODULE_F0)
+#define UART_MODULE_COUNT (7)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+#define HAL_LL_USARTE1_DATA_REG_ADDRESS (0xAB0)
+#define HAL_LL_USARTE1_STATUS_REG_ADDRESS (0xAB1)
+#define HAL_LL_USARTE1_CTRLA_REG_ADDRESS (0xAB3)
+#define HAL_LL_USARTE1_CTRLB_REG_ADDRESS (0xAB4)
+#define HAL_LL_USARTE1_CTRLC_REG_ADDRESS (0xAB5)
+#define HAL_LL_USARTE1_BAUDCTRLA_REG_ADDRESS (0xAB6)
+#define HAL_LL_USARTE1_BAUDCTRLB_REG_ADDRESS (0xAB7)
+#define HAL_LL_USARTF0_DATA_REG_ADDRESS (0xBA0)
+#define HAL_LL_USARTF0_STATUS_REG_ADDRESS (0xBA1)
+#define HAL_LL_USARTF0_CTRLA_REG_ADDRESS (0xBA3)
+#define HAL_LL_USARTF0_CTRLB_REG_ADDRESS (0xBA4)
+#define HAL_LL_USARTF0_CTRLC_REG_ADDRESS (0xBA5)
+#define HAL_LL_USARTF0_BAUDCTRLA_REG_ADDRESS (0xBA6)
+#define HAL_LL_USARTF0_BAUDCTRLB_REG_ADDRESS (0xBA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PC4
+#define SPI0_MOSI_PC5
+#define SPI0_MISO_PC6
+#define SPI0_SCK_PC7
+#define SPI1_SS_PD4
+#define SPI1_MOSI_PD5
+#define SPI1_MISO_PD6
+#define SPI1_SCK_PD7
+#define SPI2_SS_PE4
+#define SPI2_MOSI_PE5
+#define SPI2_MISO_PE6
+#define SPI2_SCK_PE7
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_2 (3)
+#define SPI_MODULE_COUNT (3)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x08C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x08C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x08C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x08C3)
+
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x09C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x09C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x09C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x09C3)
+
+#define HAL_LL_SPI2_CTRL_REG_ADDRESS (0x0AC0)
+#define HAL_LL_SPI2_INTCTRL_REG_ADDRESS (0x0AC1)
+#define HAL_LL_SPI2_STATUS_REG_ADDRESS (0x0AC2)
+#define HAL_LL_SPI2_DATA_REG_ADDRESS (0x0AC3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// TCC0 (Timer/Counter0 on PORTC)
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+// TCD0 (Timer/Counter0 on PORTD)
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+// TCE0 (Timer/Counter0 on PORTE)
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+// TCF0 (Timer/Counter0 on PORTF)
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+// TCC1 (Timer/Counter1 on PORTC)
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+// TCD1 (Timer/Counter1 on PORTD)
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+// TCE1 (Timer/Counter1 on PORTE)
+#define TIM6_PE4_CH_A
+#define TIM6_PE5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_4 (5)
+#define TIM_MODULE_5 (6)
+#define TIM_MODULE_6 (7)
+
+#define TIM_MODULE_COUNT (7)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x0800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x0801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x0802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x0803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x0804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x0806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x0807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x0808)
+#define HAL_LL_TIM0_CTRLFSET_REG_ADDRESS (0x0809)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x080A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x080B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x080C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x080F)
+#define HAL_LL_TIM0_CNTL_REG_ADDRESS (0x0820)
+#define HAL_LL_TIM0_CNTH_REG_ADDRESS (0x0821)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x0826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x0827)
+#define HAL_LL_TIM0_CCAL_REG_ADDRESS (0x0828)
+#define HAL_LL_TIM0_CCAH_REG_ADDRESS (0x0829)
+#define HAL_LL_TIM0_CCBL_REG_ADDRESS (0x082A)
+#define HAL_LL_TIM0_CCBH_REG_ADDRESS (0x082B)
+#define HAL_LL_TIM0_CCCL_REG_ADDRESS (0x082C)
+#define HAL_LL_TIM0_CCCH_REG_ADDRESS (0x082D)
+#define HAL_LL_TIM0_CCDL_REG_ADDRESS (0x082E)
+#define HAL_LL_TIM0_CCDH_REG_ADDRESS (0x082F)
+#define HAL_LL_TIM0_PERBUFL_REG_ADDRESS (0x0836)
+#define HAL_LL_TIM0_PERBUFH_REG_ADDRESS (0x0837)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x0838)
+#define HAL_LL_TIM0_CCABUFL_REG_ADDRESS (0x0838)
+#define HAL_LL_TIM0_CCABUFH_REG_ADDRESS (0x0839)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x083A)
+#define HAL_LL_TIM0_CCBBUFL_REG_ADDRESS (0x083A)
+#define HAL_LL_TIM0_CCBBUFH_REG_ADDRESS (0x083B)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x083C)
+#define HAL_LL_TIM0_CCCBUFL_REG_ADDRESS (0x083C)
+#define HAL_LL_TIM0_CCCBUFH_REG_ADDRESS (0x083D)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x083E)
+#define HAL_LL_TIM0_CCDBUFL_REG_ADDRESS (0x083E)
+#define HAL_LL_TIM0_CCDBUFH_REG_ADDRESS (0x083F)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x0900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x0901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x0902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x0903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x0904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x0906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x0907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x0908)
+#define HAL_LL_TIM1_CTRLFSET_REG_ADDRESS (0x0909)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x090A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x090B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x090C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x090F)
+#define HAL_LL_TIM1_CNTL_REG_ADDRESS (0x0920)
+#define HAL_LL_TIM1_CNTH_REG_ADDRESS (0x0921)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x0926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x0927)
+#define HAL_LL_TIM1_CCAL_REG_ADDRESS (0x0928)
+#define HAL_LL_TIM1_CCAH_REG_ADDRESS (0x0929)
+#define HAL_LL_TIM1_CCBL_REG_ADDRESS (0x092A)
+#define HAL_LL_TIM1_CCBH_REG_ADDRESS (0x092B)
+#define HAL_LL_TIM1_CCCL_REG_ADDRESS (0x092C)
+#define HAL_LL_TIM1_CCCH_REG_ADDRESS (0x092D)
+#define HAL_LL_TIM1_CCDL_REG_ADDRESS (0x092E)
+#define HAL_LL_TIM1_CCDH_REG_ADDRESS (0x092F)
+#define HAL_LL_TIM1_PERBUFL_REG_ADDRESS (0x0936)
+#define HAL_LL_TIM1_PERBUFH_REG_ADDRESS (0x0937)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x0938)
+#define HAL_LL_TIM1_CCABUFL_REG_ADDRESS (0x0938)
+#define HAL_LL_TIM1_CCABUFH_REG_ADDRESS (0x0939)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x093A)
+#define HAL_LL_TIM1_CCBBUFL_REG_ADDRESS (0x093A)
+#define HAL_LL_TIM1_CCBBUFH_REG_ADDRESS (0x093B)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x093C)
+#define HAL_LL_TIM1_CCCBUFL_REG_ADDRESS (0x093C)
+#define HAL_LL_TIM1_CCCBUFH_REG_ADDRESS (0x093D)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x093E)
+#define HAL_LL_TIM1_CCDBUFL_REG_ADDRESS (0x093E)
+#define HAL_LL_TIM1_CCDBUFH_REG_ADDRESS (0x093F)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0x0A00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0x0A01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0x0A02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0x0A03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0x0A04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0x0A06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0x0A07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0x0A08)
+#define HAL_LL_TIM2_CTRLFSET_REG_ADDRESS (0x0A09)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0x0A0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0x0A0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0x0A0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0x0A0F)
+#define HAL_LL_TIM2_CNTL_REG_ADDRESS (0x0A20)
+#define HAL_LL_TIM2_CNTH_REG_ADDRESS (0x0A21)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0x0A26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0x0A27)
+#define HAL_LL_TIM2_CCAL_REG_ADDRESS (0x0A28)
+#define HAL_LL_TIM2_CCAH_REG_ADDRESS (0x0A29)
+#define HAL_LL_TIM2_CCBL_REG_ADDRESS (0x0A2A)
+#define HAL_LL_TIM2_CCBH_REG_ADDRESS (0x0A2B)
+#define HAL_LL_TIM2_CCCL_REG_ADDRESS (0x0A2C)
+#define HAL_LL_TIM2_CCCH_REG_ADDRESS (0x0A2D)
+#define HAL_LL_TIM2_CCDL_REG_ADDRESS (0x0A2E)
+#define HAL_LL_TIM2_CCDH_REG_ADDRESS (0x0A2F)
+#define HAL_LL_TIM2_PERBUFL_REG_ADDRESS (0x0A36)
+#define HAL_LL_TIM2_PERBUFH_REG_ADDRESS (0x0A37)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0x0A38)
+#define HAL_LL_TIM2_CCABUFL_REG_ADDRESS (0x0A38)
+#define HAL_LL_TIM2_CCABUFH_REG_ADDRESS (0x0A39)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0x0A3A)
+#define HAL_LL_TIM2_CCBBUFL_REG_ADDRESS (0x0A3A)
+#define HAL_LL_TIM2_CCBBUFH_REG_ADDRESS (0x0A3B)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0x0A3C)
+#define HAL_LL_TIM2_CCCBUFL_REG_ADDRESS (0x0A3C)
+#define HAL_LL_TIM2_CCCBUFH_REG_ADDRESS (0x0A3D)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0x0A3E)
+#define HAL_LL_TIM2_CCDBUFL_REG_ADDRESS (0x0A3E)
+#define HAL_LL_TIM2_CCDBUFH_REG_ADDRESS (0x0A3F)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0x0B00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0x0B01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0x0B02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0x0B03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0x0B04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0x0B06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0x0B07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0x0B08)
+#define HAL_LL_TIM3_CTRLFSET_REG_ADDRESS (0x0B09)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0x0B0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0x0B0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0x0B0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0x0B0F)
+#define HAL_LL_TIM3_CNTL_REG_ADDRESS (0x0B20)
+#define HAL_LL_TIM3_CNTH_REG_ADDRESS (0x0B21)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0x0B26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0x0B27)
+#define HAL_LL_TIM3_CCAL_REG_ADDRESS (0x0B28)
+#define HAL_LL_TIM3_CCAH_REG_ADDRESS (0x0B29)
+#define HAL_LL_TIM3_CCBL_REG_ADDRESS (0x0B2A)
+#define HAL_LL_TIM3_CCBH_REG_ADDRESS (0x0B2B)
+#define HAL_LL_TIM3_CCCL_REG_ADDRESS (0x0B2C)
+#define HAL_LL_TIM3_CCCH_REG_ADDRESS (0x0B2D)
+#define HAL_LL_TIM3_CCDL_REG_ADDRESS (0x0B2E)
+#define HAL_LL_TIM3_CCDH_REG_ADDRESS (0x0B2F)
+#define HAL_LL_TIM3_PERBUFL_REG_ADDRESS (0x0B36)
+#define HAL_LL_TIM3_PERBUFH_REG_ADDRESS (0x0B37)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0x0B38)
+#define HAL_LL_TIM3_CCABUFL_REG_ADDRESS (0x0B38)
+#define HAL_LL_TIM3_CCABUFH_REG_ADDRESS (0x0B39)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0x0B3A)
+#define HAL_LL_TIM3_CCBBUFL_REG_ADDRESS (0x0B3A)
+#define HAL_LL_TIM3_CCBBUFH_REG_ADDRESS (0x0B3B)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0x0B3C)
+#define HAL_LL_TIM3_CCCBUFL_REG_ADDRESS (0x0B3C)
+#define HAL_LL_TIM3_CCCBUFH_REG_ADDRESS (0x0B3D)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0x0B3E)
+#define HAL_LL_TIM3_CCDBUFL_REG_ADDRESS (0x0B3E)
+#define HAL_LL_TIM3_CCDBUFH_REG_ADDRESS (0x0B3F)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x0840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x0841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x0842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x0843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x0844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x0846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x0847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x0848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x0849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x084A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x084B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x084C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x084F)
+#define HAL_LL_TIM4_CNTL_REG_ADDRESS (0x0840)
+#define HAL_LL_TIM4_CNTH_REG_ADDRESS (0x0841)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x0846)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x0847)
+#define HAL_LL_TIM4_CCAL_REG_ADDRESS (0x0848)
+#define HAL_LL_TIM4_CCAH_REG_ADDRESS (0x0849)
+#define HAL_LL_TIM4_CCBL_REG_ADDRESS (0x084A)
+#define HAL_LL_TIM4_CCBH_REG_ADDRESS (0x084B)
+#define HAL_LL_TIM4_PERBUFL_REG_ADDRESS (0x0866)
+#define HAL_LL_TIM4_PERBUFH_REG_ADDRESS (0x0867)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x0868)
+#define HAL_LL_TIM4_CCABUFL_REG_ADDRESS (0x0868)
+#define HAL_LL_TIM4_CCABUFH_REG_ADDRESS (0x0869)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x086A)
+#define HAL_LL_TIM4_CCBBUFL_REG_ADDRESS (0x086A)
+#define HAL_LL_TIM4_CCBBUFH_REG_ADDRESS (0x086B)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x0940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x0941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x0942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x0943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x0944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x0946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x0947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x0948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x0949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x094A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x094B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x094C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x094F)
+#define HAL_LL_TIM5_CNTL_REG_ADDRESS (0x0960)
+#define HAL_LL_TIM5_CNTH_REG_ADDRESS (0x0961)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x0966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x0967)
+#define HAL_LL_TIM5_CCAL_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCAH_REG_ADDRESS (0x0969)
+#define HAL_LL_TIM5_CCBL_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBH_REG_ADDRESS (0x096B)
+#define HAL_LL_TIM5_PERBUFL_REG_ADDRESS (0x0966)
+#define HAL_LL_TIM5_PERBUFH_REG_ADDRESS (0x0967)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCABUFL_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCABUFH_REG_ADDRESS (0x0969)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBBUFL_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBBUFH_REG_ADDRESS (0x096B)
+#define HAL_LL_TIM6_CTRLA_REG_ADDRESS (0x0A40)
+#define HAL_LL_TIM6_CTRLB_REG_ADDRESS (0x0A41)
+#define HAL_LL_TIM6_CTRLC_REG_ADDRESS (0x0A42)
+#define HAL_LL_TIM6_CTRLD_REG_ADDRESS (0x0A43)
+#define HAL_LL_TIM6_CTRLE_REG_ADDRESS (0x0A44)
+#define HAL_LL_TIM6_INTCTRLA_REG_ADDRESS (0x0A46)
+#define HAL_LL_TIM6_INTCTRLB_REG_ADDRESS (0x0A47)
+#define HAL_LL_TIM6_CTRLFCLR_REG_ADDRESS (0x0A48)
+#define HAL_LL_TIM6_CTRLFSET_REG_ADDRESS (0x0A49)
+#define HAL_LL_TIM6_CTRLGCLR_REG_ADDRESS (0x0A4A)
+#define HAL_LL_TIM6_CTRLGSET_REG_ADDRESS (0x0A4B)
+#define HAL_LL_TIM6_INTFLAGS_REG_ADDRESS (0x0A4C)
+#define HAL_LL_TIM6_TEMP_REG_ADDRESS (0x0A4F)
+#define HAL_LL_TIM6_CNTL_REG_ADDRESS (0x0A60)
+#define HAL_LL_TIM6_CNTH_REG_ADDRESS (0x0A61)
+#define HAL_LL_TIM6_PERL_REG_ADDRESS (0x0A66)
+#define HAL_LL_TIM6_PERH_REG_ADDRESS (0x0A67)
+#define HAL_LL_TIM6_CCAL_REG_ADDRESS (0x0A68)
+#define HAL_LL_TIM6_CCAH_REG_ADDRESS (0x0A69)
+#define HAL_LL_TIM6_CCBL_REG_ADDRESS (0x0A6A)
+#define HAL_LL_TIM6_CCBH_REG_ADDRESS (0x0A6B)
+#define HAL_LL_TIM6_PERBUFL_REG_ADDRESS (0x0A66)
+#define HAL_LL_TIM6_PERBUFH_REG_ADDRESS (0x0A67)
+#define HAL_LL_TIM6_CCABUF_REG_ADDRESS (0x0A68)
+#define HAL_LL_TIM6_CCABUFL_REG_ADDRESS (0x0A68)
+#define HAL_LL_TIM6_CCABUFH_REG_ADDRESS (0x0A69)
+#define HAL_LL_TIM6_CCBBUF_REG_ADDRESS (0x0A6A)
+#define HAL_LL_TIM6_CCBBUFL_REG_ADDRESS (0x0A6A)
+#define HAL_LL_TIM6_CCBBUFH_REG_ADDRESS (0x0A6B)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTE1_RXC_IVT (61)
+#define HAL_LL_USARTE1_DRE_IVT (62)
+#define HAL_LL_USARTE1_TXC_IVT (63)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+#define HAL_LL_USARTF0_RXC_IVT (119)
+#define HAL_LL_USARTF0_DRE_IVT (120)
+#define HAL_LL_USARTF0_TXC_IVT (121)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTE1_RXC_IVT_ADDRESS (0x7A)
+#define HAL_LL_USARTE1_DRE_IVT_ADDRESS (0x7C)
+#define HAL_LL_USARTE1_TXC_IVT_ADDRESS (0x7E)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+#define HAL_LL_USARTF0_RXC_IVT_ADDRESS (0xEE)
+#define HAL_LL_USARTF0_DRE_IVT_ADDRESS (0xF0)
+#define HAL_LL_USARTF0_TXC_IVT_ADDRESS (0xF2)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128A3U/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128A3U/mcu_definitions.h
new file mode 100644
index 000000000..57d3aff20
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128A3U/mcu_definitions.h
@@ -0,0 +1,721 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH0
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH1
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB2_CH2
+#define ADC0_PB3_CH11
+#define ADC0_PB3_CH3
+#define ADC0_PB4_CH12
+#define ADC0_PB4_CH4
+#define ADC0_PB5_CH13
+#define ADC0_PB5_CH5
+#define ADC0_PB6_CH14
+#define ADC0_PB6_CH6
+#define ADC0_PB7_CH15
+#define ADC0_PB7_CH7
+#define ADC1_PA0_CH0
+#define ADC1_PB0_CH0
+#define ADC1_PB0_CH8
+#define ADC1_PB1_CH1
+#define ADC1_PB1_CH9
+#define ADC1_PB2_CH10
+#define ADC1_PB2_CH2
+#define ADC1_PB3_CH11
+#define ADC1_PB3_CH3
+#define ADC1_PB4_CH12
+#define ADC1_PB4_CH4
+#define ADC1_PB5_CH13
+#define ADC1_PB5_CH5
+#define ADC1_PB6_CH14
+#define ADC1_PB6_CH6
+#define ADC1_PB7_CH15
+#define ADC1_PB7_CH7
+
+#define ADC_MODULE_0 (1)
+#define ADC_MODULE_1 (2)
+
+#define HAL_LL_AN_COUNT (41)
+#define ADC_MODULE_COUNT (2)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+#define HAL_LL_ADC1_CTRLA_REG_ADDRESS (0x240)
+#define HAL_LL_ADC1_BASE_ADDRESS (HAL_LL_ADC1_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC1_CTRLB_REG_ADDRESS (0x241)
+#define HAL_LL_ADC1_REFCTRL_REG_ADDRESS (0x242)
+#define HAL_LL_ADC1_EVCTRL_REG_ADDRESS (0x243)
+#define HAL_LL_ADC1_PRESCALER_REG_ADDRESS (0x244)
+#define HAL_LL_ADC1_INTFLAGS_REG_ADDRESS (0x246)
+#define HAL_LL_ADC1_TEMP_REG_ADDRESS (0x247)
+#define HAL_LL_ADC1_CH0RESL_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0RESH_REG_ADDRESS (0x251)
+#define HAL_LL_ADC1_CH0RES_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH1RESL_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH1RESH_REG_ADDRESS (0x253)
+#define HAL_LL_ADC1_CH1RES_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH2RESL_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH2RESH_REG_ADDRESS (0x255)
+#define HAL_LL_ADC1_CH2RES_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH3RESL_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH3RESH_REG_ADDRESS (0x257)
+#define HAL_LL_ADC1_CH3RES_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH0CTRL_REG_ADDRESS (0x260)
+#define HAL_LL_ADC1_CH0MUXCTRL_REG_ADDRESS (0x261)
+#define HAL_LL_ADC1_CH0INTCTRL_REG_ADDRESS (0x262)
+#define HAL_LL_ADC1_CH0INTFLAGS_REG_ADDRESS (0x263)
+#define HAL_LL_ADC1_CH1CTRL_REG_ADDRESS (0x268)
+#define HAL_LL_ADC1_CH1MUXCTRL_REG_ADDRESS (0x269)
+#define HAL_LL_ADC1_CH1INTCTRL_REG_ADDRESS (0x26A)
+#define HAL_LL_ADC1_CH1INTFLAGS_REG_ADDRESS (0x26B)
+#define HAL_LL_ADC1_CH2CTRL_REG_ADDRESS (0x270)
+#define HAL_LL_ADC1_CH2MUXCTRL_REG_ADDRESS (0x271)
+#define HAL_LL_ADC1_CH2INTCTRL_REG_ADDRESS (0x272)
+#define HAL_LL_ADC1_CH2INTFLAGS_REG_ADDRESS (0x273)
+#define HAL_LL_ADC1_CH3CTRL_REG_ADDRESS (0x278)
+#define HAL_LL_ADC1_CH3MUXCTRL_REG_ADDRESS (0x279)
+#define HAL_LL_ADC1_CH3INTCTRL_REG_ADDRESS (0x27A)
+#define HAL_LL_ADC1_CH3INTFLAGS_REG_ADDRESS (0x27B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_RXD_PD6_ALT
+#define USARTD0_TXD_PD3
+#define USARTD0_TXD_PD7_ALT
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_RXD_PE6_ALT
+#define USARTE0_TXD_PE3
+#define USARTE0_TXD_PE7_ALT
+#define USARTE1_RXD_PE6
+#define USARTE1_TXD_PE7
+#define USARTF0_RXD_PF2
+#define USARTF0_RXD_PF6_ALT
+#define USARTF0_TXD_PF3
+#define USARTF0_TXD_PF7_ALT
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_E1 (6)
+#define UART_MODULE_5 (UART_MODULE_E1)
+#define UART_MODULE_F0 (7)
+#define UART_MODULE_6 (UART_MODULE_F0)
+#define UART_MODULE_COUNT (7)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+#define HAL_LL_USARTE1_DATA_REG_ADDRESS (0xAB0)
+#define HAL_LL_USARTE1_STATUS_REG_ADDRESS (0xAB1)
+#define HAL_LL_USARTE1_CTRLA_REG_ADDRESS (0xAB3)
+#define HAL_LL_USARTE1_CTRLB_REG_ADDRESS (0xAB4)
+#define HAL_LL_USARTE1_CTRLC_REG_ADDRESS (0xAB5)
+#define HAL_LL_USARTE1_BAUDCTRLA_REG_ADDRESS (0xAB6)
+#define HAL_LL_USARTE1_BAUDCTRLB_REG_ADDRESS (0xAB7)
+#define HAL_LL_USARTF0_DATA_REG_ADDRESS (0xBA0)
+#define HAL_LL_USARTF0_STATUS_REG_ADDRESS (0xBA1)
+#define HAL_LL_USARTF0_CTRLA_REG_ADDRESS (0xBA3)
+#define HAL_LL_USARTF0_CTRLB_REG_ADDRESS (0xBA4)
+#define HAL_LL_USARTF0_CTRLC_REG_ADDRESS (0xBA5)
+#define HAL_LL_USARTF0_BAUDCTRLA_REG_ADDRESS (0xBA6)
+#define HAL_LL_USARTF0_BAUDCTRLB_REG_ADDRESS (0xBA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_MOSI_PD7
+#define SPI1_SCK_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+#define SPI2_MISO_PE6
+#define SPI2_MOSI_PE5
+#define SPI2_MOSI_PE7
+#define SPI2_SCK_PE5
+#define SPI2_SCK_PE7
+#define SPI2_SS_PE4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_2 (3)
+#define SPI_MODULE_COUNT (3)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+#define HAL_LL_SPI2_CTRL_REG_ADDRESS (0xAC0)
+#define HAL_LL_SPI2_INTCTRL_REG_ADDRESS (0xAC1)
+#define HAL_LL_SPI2_STATUS_REG_ADDRESS (0xAC2)
+#define HAL_LL_SPI2_DATA_REG_ADDRESS (0xAC3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+#define TIM0_PC4_CH_A
+#define TIM0_PC5_CH_B
+#define TIM0_PC6_CH_C
+#define TIM0_PC7_CH_D
+#define TIM1_PC4_CH_A
+#define TIM1_PC5_CH_B
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM1_PD4_CH_A
+#define TIM1_PD5_CH_B
+#define TIM1_PD6_CH_C
+#define TIM1_PD7_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM2_PE4_CH_A
+#define TIM2_PE5_CH_B
+#define TIM2_PE6_CH_C
+#define TIM2_PE7_CH_D
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+#define TIM6_PE4_CH_A
+#define TIM6_PE5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_5 (5)
+#define TIM_MODULE_6 (6)
+#define TIM_MODULE_COUNT (6)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x94A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x94B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x94C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x94F)
+#define HAL_LL_TIM5_CNT_REG_ADDRESS (0x960)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x967)
+#define HAL_LL_TIM5_PER_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_CCA_REG_ADDRESS (0x968)
+#define HAL_LL_TIM5_CCB_REG_ADDRESS (0x96A)
+#define HAL_LL_TIM5_PERBUF_REG_ADDRESS (0x976)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x978)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x97A)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM6_CTRLA_REG_ADDRESS (0xA40)
+#define HAL_LL_TIM6_CTRLB_REG_ADDRESS (0xA41)
+#define HAL_LL_TIM6_CTRLC_REG_ADDRESS (0xA42)
+#define HAL_LL_TIM6_CTRLD_REG_ADDRESS (0xA43)
+#define HAL_LL_TIM6_CTRLE_REG_ADDRESS (0xA44)
+#define HAL_LL_TIM6_INTCTRLA_REG_ADDRESS (0xA46)
+#define HAL_LL_TIM6_INTCTRLB_REG_ADDRESS (0xA47)
+#define HAL_LL_TIM6_CTRLFCLR_REG_ADDRESS (0xA48)
+#define HAL_LL_TIM6_CTRLFSET_REG_ADDRESS (0xA49)
+#define HAL_LL_TIM6_CTRLGCLR_REG_ADDRESS (0xA4A)
+#define HAL_LL_TIM6_CTRLGSET_REG_ADDRESS (0xA4B)
+#define HAL_LL_TIM6_INTFLAGS_REG_ADDRESS (0xA4C)
+#define HAL_LL_TIM6_TEMP_REG_ADDRESS (0xA4F)
+#define HAL_LL_TIM6_CNT_REG_ADDRESS (0xA60)
+#define HAL_LL_TIM6_PERL_REG_ADDRESS (0xA66)
+#define HAL_LL_TIM6_PERH_REG_ADDRESS (0xA67)
+#define HAL_LL_TIM6_PER_REG_ADDRESS (0xA66)
+#define HAL_LL_TIM6_CCA_REG_ADDRESS (0xA68)
+#define HAL_LL_TIM6_CCB_REG_ADDRESS (0xA6A)
+#define HAL_LL_TIM6_PERBUF_REG_ADDRESS (0xA76)
+#define HAL_LL_TIM6_CCABUF_REG_ADDRESS (0xA78)
+#define HAL_LL_TIM6_CCBBUF_REG_ADDRESS (0xA7A)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0xB00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0xB01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0xB02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0xB03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0xB04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0xB06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0xB07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0xB08)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0xB0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0xB0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0xB0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0xB0F)
+#define HAL_LL_TIM3_PERBUF_REG_ADDRESS (0xB36)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0xB38)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0xB3A)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0xB3C)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0xB3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM3_CNT_REG_ADDRESS (0xB20)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0xB26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0xB27)
+#define HAL_LL_TIM3_CCA_REG_ADDRESS (0xB28)
+#define HAL_LL_TIM3_CCB_REG_ADDRESS (0xB2A)
+#define HAL_LL_TIM3_CCC_REG_ADDRESS (0xB2C)
+#define HAL_LL_TIM3_CCD_REG_ADDRESS (0xB2E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTF_REMAP_REG_ADDRESS (0x6AE)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTE1_RXC_IVT (61)
+#define HAL_LL_USARTE1_DRE_IVT (62)
+#define HAL_LL_USARTE1_TXC_IVT (63)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+#define HAL_LL_USARTF0_RXC_IVT (119)
+#define HAL_LL_USARTF0_DRE_IVT (120)
+#define HAL_LL_USARTF0_TXC_IVT (121)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTE1_RXC_IVT_ADDRESS (0x7A)
+#define HAL_LL_USARTE1_DRE_IVT_ADDRESS (0x7C)
+#define HAL_LL_USARTE1_TXC_IVT_ADDRESS (0x7E)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+#define HAL_LL_USARTF0_RXC_IVT_ADDRESS (0xEE)
+#define HAL_LL_USARTF0_DRE_IVT_ADDRESS (0xF0)
+#define HAL_LL_USARTF0_TXC_IVT_ADDRESS (0xF2)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128A4U/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128A4U/mcu_definitions.h
new file mode 100644
index 000000000..88558ebc8
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128A4U/mcu_definitions.h
@@ -0,0 +1,529 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB3_CH11
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (12)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_RXD_PD6_ALT
+#define USARTD0_TXD_PD3
+#define USARTD0_TXD_PD7_ALT
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_COUNT (5)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_MOSI_PD7
+#define SPI1_SCK_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+#define TIM0_PC4_CH_A
+#define TIM0_PC5_CH_B
+#define TIM0_PC6_CH_C
+#define TIM0_PC7_CH_D
+#define TIM1_PC4_CH_A
+#define TIM1_PC5_CH_B
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM1_PD4_CH_A
+#define TIM1_PD5_CH_B
+#define TIM1_PD6_CH_C
+#define TIM1_PD7_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_5 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x94A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x94B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x94C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x94F)
+#define HAL_LL_TIM5_CNT_REG_ADDRESS (0x960)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x967)
+#define HAL_LL_TIM5_PER_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_CCA_REG_ADDRESS (0x968)
+#define HAL_LL_TIM5_CCB_REG_ADDRESS (0x96A)
+#define HAL_LL_TIM5_PERBUF_REG_ADDRESS (0x976)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x978)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x97A)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLFSET_REG_ADDRESS (0xA09)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_PER_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128B1/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128B1/mcu_definitions.h
new file mode 100644
index 000000000..5c97e0b41
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128B1/mcu_definitions.h
@@ -0,0 +1,436 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH0
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH1
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB2_CH2
+#define ADC0_PB3_CH11
+#define ADC0_PB3_CH3
+#define ADC0_PB4_CH12
+#define ADC0_PB4_CH4
+#define ADC0_PB5_CH13
+#define ADC0_PB5_CH5
+#define ADC0_PB6_CH14
+#define ADC0_PB6_CH6
+#define ADC0_PB7_CH15
+#define ADC0_PB7_CH7
+#define ADC1_PA0_CH0
+#define ADC1_PB0_CH0
+#define ADC1_PB0_CH8
+#define ADC1_PB1_CH1
+#define ADC1_PB1_CH9
+#define ADC1_PB2_CH10
+#define ADC1_PB2_CH2
+#define ADC1_PB3_CH11
+#define ADC1_PB3_CH3
+#define ADC1_PB4_CH12
+#define ADC1_PB4_CH4
+#define ADC1_PB5_CH13
+#define ADC1_PB5_CH5
+#define ADC1_PB6_CH14
+#define ADC1_PB6_CH6
+#define ADC1_PB7_CH15
+#define ADC1_PB7_CH7
+
+#define ADC_MODULE_0 (1)
+#define ADC_MODULE_1 (2)
+
+#define HAL_LL_AN_COUNT (41)
+#define ADC_MODULE_COUNT (2)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC1_CTRLA_REG_ADDRESS (0x240)
+#define HAL_LL_ADC1_BASE_ADDRESS (HAL_LL_ADC1_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC1_CTRLB_REG_ADDRESS (0x241)
+#define HAL_LL_ADC1_REFCTRL_REG_ADDRESS (0x242)
+#define HAL_LL_ADC1_EVCTRL_REG_ADDRESS (0x243)
+#define HAL_LL_ADC1_PRESCALER_REG_ADDRESS (0x244)
+#define HAL_LL_ADC1_INTFLAGS_REG_ADDRESS (0x246)
+#define HAL_LL_ADC1_TEMP_REG_ADDRESS (0x247)
+#define HAL_LL_ADC1_CH0RESL_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0RESH_REG_ADDRESS (0x251)
+#define HAL_LL_ADC1_CH0RES_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0CTRL_REG_ADDRESS (0x260)
+#define HAL_LL_ADC1_CH0MUXCTRL_REG_ADDRESS (0x261)
+#define HAL_LL_ADC1_CH0INTCTRL_REG_ADDRESS (0x262)
+#define HAL_LL_ADC1_CH0INTFLAGS_REG_ADDRESS (0x263)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTE0_RXD_PE2
+#define USARTE0_RXD_PE6_ALT
+#define USARTE0_TXD_PE3
+#define USARTE0_TXD_PE7_ALT
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_E0 (2)
+#define UART_MODULE_1 (UART_MODULE_E0)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_2 (2)
+#define TIM_MODULE_4 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+#define __PM0_CN
+#define __PM1_CN
+#define __PM2_CN
+#define __PM3_CN
+#define __PM4_CN
+#define __PM5_CN
+#define __PM6_CN
+#define __PM7_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_G_CN
+#define __PORT_M_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (8)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRG_REG_ADDRESS (0x6C0)
+#define PORTG_REG_ADDRESS (0x6C4)
+#define PING_REG_ADDRESS (0x6C8)
+#define DDRM_REG_ADDRESS (0x760)
+#define PORTM_REG_ADDRESS (0x764)
+#define PINM_REG_ADDRESS (0x768)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTG_REMAP_REG_ADDRESS (0x6CE)
+#define PORTM_REMAP_REG_ADDRESS (0x76E)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTE0_RXC_IVT (69)
+#define HAL_LL_USARTE0_DRE_IVT (70)
+#define HAL_LL_USARTE0_TXC_IVT (71)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x8A)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x8C)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x8E)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128B3/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128B3/mcu_definitions.h
new file mode 100644
index 000000000..f99228153
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128B3/mcu_definitions.h
@@ -0,0 +1,312 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC1_PB0_CH0
+#define ADC1_PB1_CH1
+#define ADC1_PB2_CH2
+#define ADC1_PB3_CH3
+#define ADC1_PB4_CH4
+#define ADC1_PB5_CH5
+#define ADC1_PB6_CH6
+#define ADC1_PB7_CH7
+
+#define ADC_MODULE_1 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC1_CTRLA_REG_ADDRESS (0x240)
+#define HAL_LL_ADC1_BASE_ADDRESS (HAL_LL_ADC1_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC1_CTRLB_REG_ADDRESS (0x241)
+#define HAL_LL_ADC1_REFCTRL_REG_ADDRESS (0x242)
+#define HAL_LL_ADC1_EVCTRL_REG_ADDRESS (0x243)
+#define HAL_LL_ADC1_PRESCALER_REG_ADDRESS (0x244)
+#define HAL_LL_ADC1_INTFLAGS_REG_ADDRESS (0x246)
+#define HAL_LL_ADC1_TEMP_REG_ADDRESS (0x247)
+#define HAL_LL_ADC1_CH0RESL_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0RESH_REG_ADDRESS (0x251)
+#define HAL_LL_ADC1_CH0RES_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0CTRL_REG_ADDRESS (0x260)
+#define HAL_LL_ADC1_CH0MUXCTRL_REG_ADDRESS (0x261)
+#define HAL_LL_ADC1_CH0INTCTRL_REG_ADDRESS (0x262)
+#define HAL_LL_ADC1_CH0INTFLAGS_REG_ADDRESS (0x263)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_4 (2)
+#define TIM_MODULE_COUNT (2)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+#define __PM0_CN
+#define __PM1_CN
+#define __PM2_CN
+#define __PM3_CN
+#define __PM4_CN
+#define __PM5_CN
+#define __PM6_CN
+#define __PM7_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_G_CN
+#define __PORT_M_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRG_REG_ADDRESS (0x6C0)
+#define PORTG_REG_ADDRESS (0x6C4)
+#define PING_REG_ADDRESS (0x6C8)
+#define DDRM_REG_ADDRESS (0x760)
+#define PORTM_REG_ADDRESS (0x764)
+#define PINM_REG_ADDRESS (0x768)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTG_REMAP_REG_ADDRESS (0x6CE)
+#define PORTM_REMAP_REG_ADDRESS (0x76E)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128D3/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128D3/mcu_definitions.h
new file mode 100644
index 000000000..459c73d5c
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128D3/mcu_definitions.h
@@ -0,0 +1,498 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB3_CH11
+#define ADC0_PB4_CH12
+#define ADC0_PB5_CH13
+#define ADC0_PB6_CH14
+#define ADC0_PB7_CH15
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (16)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_D0 (2)
+#define UART_MODULE_1 (UART_MODULE_D0)
+#define UART_MODULE_E0 (3)
+#define UART_MODULE_2 (UART_MODULE_E0)
+#define UART_MODULE_COUNT (3)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+#define HAL_LL_SPI2_CTRL_REG_ADDRESS (0xAC0)
+#define HAL_LL_SPI2_INTCTRL_REG_ADDRESS (0xAC1)
+#define HAL_LL_SPI2_STATUS_REG_ADDRESS (0xAC2)
+#define HAL_LL_SPI2_DATA_REG_ADDRESS (0xAC3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+// TODO - Alternate pins to be implemented in a future release
+// #define TIM0_PC4_CH_A_ALT
+// #define TIM0_PC5_CH_B_ALT
+// #define TIM0_PC6_CH_C_ALT
+// #define TIM0_PC7_CH_D_ALT
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_4 (5)
+#define TIM_MODULE_COUNT (5)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0xB00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0xB01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0xB02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0xB03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0xB04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0xB06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0xB07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0xB08)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0xB0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0xB0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0xB0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0xB0F)
+#define HAL_LL_TIM3_PERBUF_REG_ADDRESS (0xB36)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0xB38)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0xB3A)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0xB3C)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0xB3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM3_CNT_REG_ADDRESS (0xB20)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0xB26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0xB27)
+#define HAL_LL_TIM3_CCA_REG_ADDRESS (0xB28)
+#define HAL_LL_TIM3_CCB_REG_ADDRESS (0xB2A)
+#define HAL_LL_TIM3_CCC_REG_ADDRESS (0xB2C)
+#define HAL_LL_TIM3_CCD_REG_ADDRESS (0xB2E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTF_REMAP_REG_ADDRESS (0x6AE)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128D4/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128D4/mcu_definitions.h
new file mode 100644
index 000000000..b5baf1612
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA128D4/mcu_definitions.h
@@ -0,0 +1,425 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB3_CH11
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (12)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_D0 (2)
+#define UART_MODULE_1 (UART_MODULE_D0)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+// TODO - Alternate pins to be implemented in a future release
+// #define TIM0_PC4_CH_A_ALT
+// #define TIM0_PC5_CH_B_ALT
+// #define TIM0_PC6_CH_C_ALT
+// #define TIM0_PC7_CH_D_ALT
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_4 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLFSET_REG_ADDRESS (0xA09)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_PER_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA16A4/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA16A4/mcu_definitions.h
new file mode 100644
index 000000000..73307f259
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA16A4/mcu_definitions.h
@@ -0,0 +1,591 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB3_CH11
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (12)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS_ALTERNATE (0x224)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS_ALTERNATE (0x224)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS_ALTERNATE (0x225)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS_ALTERNATE (0x22C)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS_ALTERNATE (0x22C)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS_ALTERNATE (0x22)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS_ALTERNATE (0x234)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS_ALTERNATE (0x234)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS_ALTERNATE (0x235)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS_ALTERNATE (0x23C)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS_ALTERNATE (0x23C)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS_ALTERNATE (0x23)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_TXD_PC3
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_COUNT (5)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PC4
+#define SPI0_MOSI_PC5
+#define SPI0_MISO_PC6
+#define SPI0_SCK_PC7
+#define SPI1_SS_PD4
+#define SPI1_MOSI_PD5
+#define SPI1_MISO_PD6
+#define SPI1_SCK_PD7
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x08C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x08C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x08C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x08C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x09C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x09C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x09C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x09C3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// NOTE: This family has 5 Timer/Counter modules, and the main diff is
+// three of them utilize 4 Output Compare (OC) channels (A, B, C and D),
+// unlike the other two module which utilize only two channels (A and B).
+
+// TCC0 (Timer/Counter0 on PORTC)
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+// TCD0 (Timer/Counter0 on PORTD)
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+// TCE0 (Timer/Counter0 on PORTE)
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+// TCC1 (Timer/Counter1 on PORTC)
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+// TCD1 (Timer/Counter1 on PORTD)
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_4 (4)
+#define TIM_MODULE_5 (5)
+#define TIM_MODULE_COUNT (5)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x0800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x0801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x0802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x0803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x0804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x0806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x0807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x0808)
+#define HAL_LL_TIM0_CTRLFSET_REG_ADDRESS (0x0809)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x080A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x080B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x080C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x080F)
+#define HAL_LL_TIM0_CNTL_REG_ADDRESS (0x0820)
+#define HAL_LL_TIM0_CNTH_REG_ADDRESS (0x0821)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x0826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x0827)
+#define HAL_LL_TIM0_CCAL_REG_ADDRESS (0x0828)
+#define HAL_LL_TIM0_CCAH_REG_ADDRESS (0x0829)
+#define HAL_LL_TIM0_CCBL_REG_ADDRESS (0x082A)
+#define HAL_LL_TIM0_CCBH_REG_ADDRESS (0x082B)
+#define HAL_LL_TIM0_CCCL_REG_ADDRESS (0x082C)
+#define HAL_LL_TIM0_CCCH_REG_ADDRESS (0x082D)
+#define HAL_LL_TIM0_CCDL_REG_ADDRESS (0x082E)
+#define HAL_LL_TIM0_CCDH_REG_ADDRESS (0x082F)
+#define HAL_LL_TIM0_PERBUFL_REG_ADDRESS (0x0836)
+#define HAL_LL_TIM0_PERBUFH_REG_ADDRESS (0x0837)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x0838)
+#define HAL_LL_TIM0_CCABUFL_REG_ADDRESS (0x0838)
+#define HAL_LL_TIM0_CCABUFH_REG_ADDRESS (0x0839)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x083A)
+#define HAL_LL_TIM0_CCBBUFL_REG_ADDRESS (0x083A)
+#define HAL_LL_TIM0_CCBBUFH_REG_ADDRESS (0x083B)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x083C)
+#define HAL_LL_TIM0_CCCBUFL_REG_ADDRESS (0x083C)
+#define HAL_LL_TIM0_CCCBUFH_REG_ADDRESS (0x083D)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x083E)
+#define HAL_LL_TIM0_CCDBUFL_REG_ADDRESS (0x083E)
+#define HAL_LL_TIM0_CCDBUFH_REG_ADDRESS (0x083F)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x0900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x0901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x0902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x0903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x0904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x0906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x0907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x0908)
+#define HAL_LL_TIM1_CTRLFSET_REG_ADDRESS (0x0909)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x090A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x090B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x090C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x090F)
+#define HAL_LL_TIM1_CNTL_REG_ADDRESS (0x0920)
+#define HAL_LL_TIM1_CNTH_REG_ADDRESS (0x0921)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x0926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x0927)
+#define HAL_LL_TIM1_CCAL_REG_ADDRESS (0x0928)
+#define HAL_LL_TIM1_CCAH_REG_ADDRESS (0x0929)
+#define HAL_LL_TIM1_CCBL_REG_ADDRESS (0x092A)
+#define HAL_LL_TIM1_CCBH_REG_ADDRESS (0x092B)
+#define HAL_LL_TIM1_CCCL_REG_ADDRESS (0x092C)
+#define HAL_LL_TIM1_CCCH_REG_ADDRESS (0x092D)
+#define HAL_LL_TIM1_CCDL_REG_ADDRESS (0x092E)
+#define HAL_LL_TIM1_CCDH_REG_ADDRESS (0x092F)
+#define HAL_LL_TIM1_PERBUFL_REG_ADDRESS (0x0936)
+#define HAL_LL_TIM1_PERBUFH_REG_ADDRESS (0x0937)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x0938)
+#define HAL_LL_TIM1_CCABUFL_REG_ADDRESS (0x0938)
+#define HAL_LL_TIM1_CCABUFH_REG_ADDRESS (0x0939)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x093A)
+#define HAL_LL_TIM1_CCBBUFL_REG_ADDRESS (0x093A)
+#define HAL_LL_TIM1_CCBBUFH_REG_ADDRESS (0x093B)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x093C)
+#define HAL_LL_TIM1_CCCBUFL_REG_ADDRESS (0x093C)
+#define HAL_LL_TIM1_CCCBUFH_REG_ADDRESS (0x093D)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x093E)
+#define HAL_LL_TIM1_CCDBUFL_REG_ADDRESS (0x093E)
+#define HAL_LL_TIM1_CCDBUFH_REG_ADDRESS (0x093F)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0x0A00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0x0A01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0x0A02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0x0A03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0x0A04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0x0A06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0x0A07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0x0A08)
+#define HAL_LL_TIM2_CTRLFSET_REG_ADDRESS (0x0A09)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0x0A0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0x0A0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0x0A0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0x0A0F)
+#define HAL_LL_TIM2_CNTL_REG_ADDRESS (0x0A20)
+#define HAL_LL_TIM2_CNTH_REG_ADDRESS (0x0A21)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0x0A26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0x0A27)
+#define HAL_LL_TIM2_CCAL_REG_ADDRESS (0x0A28)
+#define HAL_LL_TIM2_CCAH_REG_ADDRESS (0x0A29)
+#define HAL_LL_TIM2_CCBL_REG_ADDRESS (0x0A2A)
+#define HAL_LL_TIM2_CCBH_REG_ADDRESS (0x0A2B)
+#define HAL_LL_TIM2_CCCL_REG_ADDRESS (0x0A2C)
+#define HAL_LL_TIM2_CCCH_REG_ADDRESS (0x0A2D)
+#define HAL_LL_TIM2_CCDL_REG_ADDRESS (0x0A2E)
+#define HAL_LL_TIM2_CCDH_REG_ADDRESS (0x0A2F)
+#define HAL_LL_TIM2_PERBUFL_REG_ADDRESS (0x0A36)
+#define HAL_LL_TIM2_PERBUFH_REG_ADDRESS (0x0A37)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0x0A38)
+#define HAL_LL_TIM2_CCABUFL_REG_ADDRESS (0x0A38)
+#define HAL_LL_TIM2_CCABUFH_REG_ADDRESS (0x0A39)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0x0A3A)
+#define HAL_LL_TIM2_CCBBUFL_REG_ADDRESS (0x0A3A)
+#define HAL_LL_TIM2_CCBBUFH_REG_ADDRESS (0x0A3B)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0x0A3C)
+#define HAL_LL_TIM2_CCCBUFL_REG_ADDRESS (0x0A3C)
+#define HAL_LL_TIM2_CCCBUFH_REG_ADDRESS (0x0A3D)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0x0A3E)
+#define HAL_LL_TIM2_CCDBUFL_REG_ADDRESS (0x0A3E)
+#define HAL_LL_TIM2_CCDBUFH_REG_ADDRESS (0x0A3F)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x0840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x0841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x0842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x0843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x0844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x0846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x0847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x0848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x0849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x084A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x084B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x084C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x084F)
+#define HAL_LL_TIM4_CNTL_REG_ADDRESS (0x0840)
+#define HAL_LL_TIM4_CNTH_REG_ADDRESS (0x0841)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x0846)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x0847)
+#define HAL_LL_TIM4_CCAL_REG_ADDRESS (0x0848)
+#define HAL_LL_TIM4_CCAH_REG_ADDRESS (0x0849)
+#define HAL_LL_TIM4_CCBL_REG_ADDRESS (0x084A)
+#define HAL_LL_TIM4_CCBH_REG_ADDRESS (0x084B)
+#define HAL_LL_TIM4_PERBUFL_REG_ADDRESS (0x0866)
+#define HAL_LL_TIM4_PERBUFH_REG_ADDRESS (0x0867)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x0868)
+#define HAL_LL_TIM4_CCABUFL_REG_ADDRESS (0x0868)
+#define HAL_LL_TIM4_CCABUFH_REG_ADDRESS (0x0869)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x086A)
+#define HAL_LL_TIM4_CCBBUFL_REG_ADDRESS (0x086A)
+#define HAL_LL_TIM4_CCBBUFH_REG_ADDRESS (0x086B)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x0940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x0941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x0942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x0943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x0944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x0946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x0947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x0948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x0949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x094A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x094B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x094C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x094F)
+#define HAL_LL_TIM5_CNTL_REG_ADDRESS (0x0960)
+#define HAL_LL_TIM5_CNTH_REG_ADDRESS (0x0961)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x0966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x0967)
+#define HAL_LL_TIM5_CCAL_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCAH_REG_ADDRESS (0x0969)
+#define HAL_LL_TIM5_CCBL_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBH_REG_ADDRESS (0x096B)
+#define HAL_LL_TIM5_PERBUFL_REG_ADDRESS (0x0966)
+#define HAL_LL_TIM5_PERBUFH_REG_ADDRESS (0x0967)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCABUFL_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCABUFH_REG_ADDRESS (0x0969)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBBUFL_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBBUFH_REG_ADDRESS (0x096B)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (5)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA16A4U/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA16A4U/mcu_definitions.h
new file mode 100644
index 000000000..88558ebc8
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA16A4U/mcu_definitions.h
@@ -0,0 +1,529 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB3_CH11
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (12)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_RXD_PD6_ALT
+#define USARTD0_TXD_PD3
+#define USARTD0_TXD_PD7_ALT
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_COUNT (5)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_MOSI_PD7
+#define SPI1_SCK_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+#define TIM0_PC4_CH_A
+#define TIM0_PC5_CH_B
+#define TIM0_PC6_CH_C
+#define TIM0_PC7_CH_D
+#define TIM1_PC4_CH_A
+#define TIM1_PC5_CH_B
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM1_PD4_CH_A
+#define TIM1_PD5_CH_B
+#define TIM1_PD6_CH_C
+#define TIM1_PD7_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_5 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x94A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x94B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x94C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x94F)
+#define HAL_LL_TIM5_CNT_REG_ADDRESS (0x960)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x967)
+#define HAL_LL_TIM5_PER_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_CCA_REG_ADDRESS (0x968)
+#define HAL_LL_TIM5_CCB_REG_ADDRESS (0x96A)
+#define HAL_LL_TIM5_PERBUF_REG_ADDRESS (0x976)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x978)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x97A)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLFSET_REG_ADDRESS (0xA09)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_PER_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA16D4/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA16D4/mcu_definitions.h
new file mode 100644
index 000000000..ed95a36b1
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA16D4/mcu_definitions.h
@@ -0,0 +1,448 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB3_CH11
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (12)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_D0 (2)
+#define UART_MODULE_1 (UART_MODULE_D0)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+// TODO - Alternate pins to be implemented in a future release
+// #define TIM0_PC4_CH_A_ALT
+// #define TIM0_PC5_CH_B_ALT
+// #define TIM0_PC6_CH_C_ALT
+// #define TIM0_PC7_CH_D_ALT
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_4 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLFSET_REG_ADDRESS (0x909)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_PER_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLFSET_REG_ADDRESS (0xA09)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_PER_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA16E5/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA16E5/mcu_definitions.h
new file mode 100644
index 000000000..7bde5b0ec
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA16E5/mcu_definitions.h
@@ -0,0 +1,344 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PD0_CH8
+#define ADC0_PD1_CH9
+#define ADC0_PD2_CH10
+#define ADC0_PD3_CH11
+#define ADC0_PD4_CH12
+#define ADC0_PD5_CH13
+#define ADC0_PD6_CH14
+#define ADC0_PD7_CH15
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (16)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SCL_PD1
+#define TWIC_SDA_PC0
+#define TWIC_SDA_PD0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIC_TIMEOUTTOS_REG_ADDRESS (0x48E)
+#define HAL_LL_TWIC_TIMEOUTTOCONF_REG_ADDRESS (0x48F)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8C0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8C1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8C2)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8C3)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8C4)
+#define HAL_LL_USARTC0_CTRLD_REG_ADDRESS (0x8C5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8C6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8C7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9C0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9C1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9C2)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9C3)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9C4)
+#define HAL_LL_USARTD0_CTRLD_REG_ADDRESS (0x9C5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9C6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9C7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SS_PC4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8E0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8E1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8E2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8E3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+#define TIM0_PC4_CH_A
+#define TIM0_PC5_CH_B
+#define TIM0_PC6_CH_C
+#define TIM0_PC7_CH_D
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_4 (2)
+#define TIM_MODULE_5 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_CTRLF_REG_ADDRESS (0x805)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x809)
+#define HAL_LL_TIM0_CTRLHCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLHSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_PER_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_CTRLF_REG_ADDRESS (0x845)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLHCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLHSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x944)
+#define HAL_LL_TIM5_CTRLF_REG_ADDRESS (0x945)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x947)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x948)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x949)
+#define HAL_LL_TIM5_CTRLHCLR_REG_ADDRESS (0x94A)
+#define HAL_LL_TIM5_CTRLHSET_REG_ADDRESS (0x94B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x94C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x94F)
+#define HAL_LL_TIM5_CNT_REG_ADDRESS (0x960)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x967)
+#define HAL_LL_TIM5_PER_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_CCA_REG_ADDRESS (0x968)
+#define HAL_LL_TIM5_CCB_REG_ADDRESS (0x96A)
+#define HAL_LL_TIM5_PERBUF_REG_ADDRESS (0x976)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x978)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x97A)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (23)
+#define HAL_LL_USARTC0_DRE_IVT (24)
+#define HAL_LL_USARTC0_TXC_IVT (26)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x2E)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x30)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x34)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA192A3/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA192A3/mcu_definitions.h
new file mode 100644
index 000000000..4183b74d5
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA192A3/mcu_definitions.h
@@ -0,0 +1,752 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC1_PB0_CH0
+#define ADC1_PB1_CH1
+#define ADC1_PB2_CH2
+#define ADC1_PB3_CH3
+#define ADC1_PB4_CH4
+#define ADC1_PB5_CH5
+#define ADC1_PB6_CH6
+#define ADC1_PB7_CH7
+
+#define ADC_MODULE_0 (1)
+#define ADC_MODULE_1 (2)
+
+#define HAL_LL_AN_COUNT (16)
+#define ADC_MODULE_COUNT (2)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+#define HAL_LL_ADC1_CTRLA_REG_ADDRESS (0x240)
+#define HAL_LL_ADC1_BASE_ADDRESS (HAL_LL_ADC1_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC1_CTRLB_REG_ADDRESS (0x241)
+#define HAL_LL_ADC1_REFCTRL_REG_ADDRESS (0x242)
+#define HAL_LL_ADC1_EVCTRL_REG_ADDRESS (0x243)
+#define HAL_LL_ADC1_PRESCALER_REG_ADDRESS (0x244)
+#define HAL_LL_ADC1_INTFLAGS_REG_ADDRESS (0x246)
+#define HAL_LL_ADC1_TEMP_REG_ADDRESS (0x247)
+#define HAL_LL_ADC1_CH0RESL_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0RESH_REG_ADDRESS (0x251)
+#define HAL_LL_ADC1_CH0RES_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH1RESL_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH1RESH_REG_ADDRESS (0x253)
+#define HAL_LL_ADC1_CH1RES_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH2RESL_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH2RESH_REG_ADDRESS (0x255)
+#define HAL_LL_ADC1_CH2RES_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH3RESL_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH3RESH_REG_ADDRESS (0x257)
+#define HAL_LL_ADC1_CH3RES_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH0CTRL_REG_ADDRESS (0x260)
+#define HAL_LL_ADC1_CH0MUXCTRL_REG_ADDRESS (0x261)
+#define HAL_LL_ADC1_CH0INTCTRL_REG_ADDRESS (0x262)
+#define HAL_LL_ADC1_CH0INTFLAGS_REG_ADDRESS (0x263)
+#define HAL_LL_ADC1_CH1CTRL_REG_ADDRESS (0x268)
+#define HAL_LL_ADC1_CH1MUXCTRL_REG_ADDRESS (0x269)
+#define HAL_LL_ADC1_CH1INTCTRL_REG_ADDRESS (0x26A)
+#define HAL_LL_ADC1_CH1INTFLAGS_REG_ADDRESS (0x26B)
+#define HAL_LL_ADC1_CH2CTRL_REG_ADDRESS (0x270)
+#define HAL_LL_ADC1_CH2MUXCTRL_REG_ADDRESS (0x271)
+#define HAL_LL_ADC1_CH2INTCTRL_REG_ADDRESS (0x272)
+#define HAL_LL_ADC1_CH2INTFLAGS_REG_ADDRESS (0x273)
+#define HAL_LL_ADC1_CH3CTRL_REG_ADDRESS (0x278)
+#define HAL_LL_ADC1_CH3MUXCTRL_REG_ADDRESS (0x279)
+#define HAL_LL_ADC1_CH3INTCTRL_REG_ADDRESS (0x27A)
+#define HAL_LL_ADC1_CH3INTFLAGS_REG_ADDRESS (0x27B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_TXD_PC3
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+#define USARTE1_RXD_PE6
+#define USARTE1_TXD_PE7
+#define USARTF0_RXD_PF2
+#define USARTF0_TXD_PF3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_E1 (6)
+#define UART_MODULE_5 (UART_MODULE_E1)
+#define UART_MODULE_F0 (7)
+#define UART_MODULE_6 (UART_MODULE_F0)
+#define UART_MODULE_COUNT (7)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+#define HAL_LL_USARTE1_DATA_REG_ADDRESS (0xAB0)
+#define HAL_LL_USARTE1_STATUS_REG_ADDRESS (0xAB1)
+#define HAL_LL_USARTE1_CTRLA_REG_ADDRESS (0xAB3)
+#define HAL_LL_USARTE1_CTRLB_REG_ADDRESS (0xAB4)
+#define HAL_LL_USARTE1_CTRLC_REG_ADDRESS (0xAB5)
+#define HAL_LL_USARTE1_BAUDCTRLA_REG_ADDRESS (0xAB6)
+#define HAL_LL_USARTE1_BAUDCTRLB_REG_ADDRESS (0xAB7)
+#define HAL_LL_USARTF0_DATA_REG_ADDRESS (0xBA0)
+#define HAL_LL_USARTF0_STATUS_REG_ADDRESS (0xBA1)
+#define HAL_LL_USARTF0_CTRLA_REG_ADDRESS (0xBA3)
+#define HAL_LL_USARTF0_CTRLB_REG_ADDRESS (0xBA4)
+#define HAL_LL_USARTF0_CTRLC_REG_ADDRESS (0xBA5)
+#define HAL_LL_USARTF0_BAUDCTRLA_REG_ADDRESS (0xBA6)
+#define HAL_LL_USARTF0_BAUDCTRLB_REG_ADDRESS (0xBA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PC4
+#define SPI0_MOSI_PC5
+#define SPI0_MISO_PC6
+#define SPI0_SCK_PC7
+#define SPI1_SS_PD4
+#define SPI1_MOSI_PD5
+#define SPI1_MISO_PD6
+#define SPI1_SCK_PD7
+#define SPI2_SS_PE4
+#define SPI2_MOSI_PE5
+#define SPI2_MISO_PE6
+#define SPI2_SCK_PE7
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_2 (3)
+#define SPI_MODULE_COUNT (3)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x08C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x08C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x08C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x08C3)
+
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x09C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x09C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x09C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x09C3)
+
+#define HAL_LL_SPI2_CTRL_REG_ADDRESS (0x0AC0)
+#define HAL_LL_SPI2_INTCTRL_REG_ADDRESS (0x0AC1)
+#define HAL_LL_SPI2_STATUS_REG_ADDRESS (0x0AC2)
+#define HAL_LL_SPI2_DATA_REG_ADDRESS (0x0AC3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// TCC0 (Timer/Counter0 on PORTC)
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+// TCD0 (Timer/Counter0 on PORTD)
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+// TCE0 (Timer/Counter0 on PORTE)
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+// TCF0 (Timer/Counter0 on PORTF)
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+// TCC1 (Timer/Counter1 on PORTC)
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+// TCD1 (Timer/Counter1 on PORTD)
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+// TCE1 (Timer/Counter1 on PORTE)
+#define TIM6_PE4_CH_A
+#define TIM6_PE5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_4 (5)
+#define TIM_MODULE_5 (6)
+#define TIM_MODULE_6 (7)
+
+#define TIM_MODULE_COUNT (7)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x0800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x0801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x0802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x0803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x0804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x0806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x0807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x0808)
+#define HAL_LL_TIM0_CTRLFSET_REG_ADDRESS (0x0809)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x080A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x080B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x080C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x080F)
+#define HAL_LL_TIM0_CNTL_REG_ADDRESS (0x0820)
+#define HAL_LL_TIM0_CNTH_REG_ADDRESS (0x0821)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x0826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x0827)
+#define HAL_LL_TIM0_CCAL_REG_ADDRESS (0x0828)
+#define HAL_LL_TIM0_CCAH_REG_ADDRESS (0x0829)
+#define HAL_LL_TIM0_CCBL_REG_ADDRESS (0x082A)
+#define HAL_LL_TIM0_CCBH_REG_ADDRESS (0x082B)
+#define HAL_LL_TIM0_CCCL_REG_ADDRESS (0x082C)
+#define HAL_LL_TIM0_CCCH_REG_ADDRESS (0x082D)
+#define HAL_LL_TIM0_CCDL_REG_ADDRESS (0x082E)
+#define HAL_LL_TIM0_CCDH_REG_ADDRESS (0x082F)
+#define HAL_LL_TIM0_PERBUFL_REG_ADDRESS (0x0836)
+#define HAL_LL_TIM0_PERBUFH_REG_ADDRESS (0x0837)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x0838)
+#define HAL_LL_TIM0_CCABUFL_REG_ADDRESS (0x0838)
+#define HAL_LL_TIM0_CCABUFH_REG_ADDRESS (0x0839)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x083A)
+#define HAL_LL_TIM0_CCBBUFL_REG_ADDRESS (0x083A)
+#define HAL_LL_TIM0_CCBBUFH_REG_ADDRESS (0x083B)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x083C)
+#define HAL_LL_TIM0_CCCBUFL_REG_ADDRESS (0x083C)
+#define HAL_LL_TIM0_CCCBUFH_REG_ADDRESS (0x083D)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x083E)
+#define HAL_LL_TIM0_CCDBUFL_REG_ADDRESS (0x083E)
+#define HAL_LL_TIM0_CCDBUFH_REG_ADDRESS (0x083F)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x0900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x0901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x0902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x0903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x0904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x0906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x0907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x0908)
+#define HAL_LL_TIM1_CTRLFSET_REG_ADDRESS (0x0909)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x090A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x090B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x090C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x090F)
+#define HAL_LL_TIM1_CNTL_REG_ADDRESS (0x0920)
+#define HAL_LL_TIM1_CNTH_REG_ADDRESS (0x0921)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x0926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x0927)
+#define HAL_LL_TIM1_CCAL_REG_ADDRESS (0x0928)
+#define HAL_LL_TIM1_CCAH_REG_ADDRESS (0x0929)
+#define HAL_LL_TIM1_CCBL_REG_ADDRESS (0x092A)
+#define HAL_LL_TIM1_CCBH_REG_ADDRESS (0x092B)
+#define HAL_LL_TIM1_CCCL_REG_ADDRESS (0x092C)
+#define HAL_LL_TIM1_CCCH_REG_ADDRESS (0x092D)
+#define HAL_LL_TIM1_CCDL_REG_ADDRESS (0x092E)
+#define HAL_LL_TIM1_CCDH_REG_ADDRESS (0x092F)
+#define HAL_LL_TIM1_PERBUFL_REG_ADDRESS (0x0936)
+#define HAL_LL_TIM1_PERBUFH_REG_ADDRESS (0x0937)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x0938)
+#define HAL_LL_TIM1_CCABUFL_REG_ADDRESS (0x0938)
+#define HAL_LL_TIM1_CCABUFH_REG_ADDRESS (0x0939)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x093A)
+#define HAL_LL_TIM1_CCBBUFL_REG_ADDRESS (0x093A)
+#define HAL_LL_TIM1_CCBBUFH_REG_ADDRESS (0x093B)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x093C)
+#define HAL_LL_TIM1_CCCBUFL_REG_ADDRESS (0x093C)
+#define HAL_LL_TIM1_CCCBUFH_REG_ADDRESS (0x093D)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x093E)
+#define HAL_LL_TIM1_CCDBUFL_REG_ADDRESS (0x093E)
+#define HAL_LL_TIM1_CCDBUFH_REG_ADDRESS (0x093F)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0x0A00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0x0A01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0x0A02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0x0A03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0x0A04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0x0A06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0x0A07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0x0A08)
+#define HAL_LL_TIM2_CTRLFSET_REG_ADDRESS (0x0A09)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0x0A0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0x0A0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0x0A0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0x0A0F)
+#define HAL_LL_TIM2_CNTL_REG_ADDRESS (0x0A20)
+#define HAL_LL_TIM2_CNTH_REG_ADDRESS (0x0A21)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0x0A26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0x0A27)
+#define HAL_LL_TIM2_CCAL_REG_ADDRESS (0x0A28)
+#define HAL_LL_TIM2_CCAH_REG_ADDRESS (0x0A29)
+#define HAL_LL_TIM2_CCBL_REG_ADDRESS (0x0A2A)
+#define HAL_LL_TIM2_CCBH_REG_ADDRESS (0x0A2B)
+#define HAL_LL_TIM2_CCCL_REG_ADDRESS (0x0A2C)
+#define HAL_LL_TIM2_CCCH_REG_ADDRESS (0x0A2D)
+#define HAL_LL_TIM2_CCDL_REG_ADDRESS (0x0A2E)
+#define HAL_LL_TIM2_CCDH_REG_ADDRESS (0x0A2F)
+#define HAL_LL_TIM2_PERBUFL_REG_ADDRESS (0x0A36)
+#define HAL_LL_TIM2_PERBUFH_REG_ADDRESS (0x0A37)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0x0A38)
+#define HAL_LL_TIM2_CCABUFL_REG_ADDRESS (0x0A38)
+#define HAL_LL_TIM2_CCABUFH_REG_ADDRESS (0x0A39)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0x0A3A)
+#define HAL_LL_TIM2_CCBBUFL_REG_ADDRESS (0x0A3A)
+#define HAL_LL_TIM2_CCBBUFH_REG_ADDRESS (0x0A3B)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0x0A3C)
+#define HAL_LL_TIM2_CCCBUFL_REG_ADDRESS (0x0A3C)
+#define HAL_LL_TIM2_CCCBUFH_REG_ADDRESS (0x0A3D)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0x0A3E)
+#define HAL_LL_TIM2_CCDBUFL_REG_ADDRESS (0x0A3E)
+#define HAL_LL_TIM2_CCDBUFH_REG_ADDRESS (0x0A3F)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0x0B00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0x0B01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0x0B02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0x0B03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0x0B04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0x0B06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0x0B07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0x0B08)
+#define HAL_LL_TIM3_CTRLFSET_REG_ADDRESS (0x0B09)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0x0B0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0x0B0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0x0B0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0x0B0F)
+#define HAL_LL_TIM3_CNTL_REG_ADDRESS (0x0B20)
+#define HAL_LL_TIM3_CNTH_REG_ADDRESS (0x0B21)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0x0B26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0x0B27)
+#define HAL_LL_TIM3_CCAL_REG_ADDRESS (0x0B28)
+#define HAL_LL_TIM3_CCAH_REG_ADDRESS (0x0B29)
+#define HAL_LL_TIM3_CCBL_REG_ADDRESS (0x0B2A)
+#define HAL_LL_TIM3_CCBH_REG_ADDRESS (0x0B2B)
+#define HAL_LL_TIM3_CCCL_REG_ADDRESS (0x0B2C)
+#define HAL_LL_TIM3_CCCH_REG_ADDRESS (0x0B2D)
+#define HAL_LL_TIM3_CCDL_REG_ADDRESS (0x0B2E)
+#define HAL_LL_TIM3_CCDH_REG_ADDRESS (0x0B2F)
+#define HAL_LL_TIM3_PERBUFL_REG_ADDRESS (0x0B36)
+#define HAL_LL_TIM3_PERBUFH_REG_ADDRESS (0x0B37)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0x0B38)
+#define HAL_LL_TIM3_CCABUFL_REG_ADDRESS (0x0B38)
+#define HAL_LL_TIM3_CCABUFH_REG_ADDRESS (0x0B39)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0x0B3A)
+#define HAL_LL_TIM3_CCBBUFL_REG_ADDRESS (0x0B3A)
+#define HAL_LL_TIM3_CCBBUFH_REG_ADDRESS (0x0B3B)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0x0B3C)
+#define HAL_LL_TIM3_CCCBUFL_REG_ADDRESS (0x0B3C)
+#define HAL_LL_TIM3_CCCBUFH_REG_ADDRESS (0x0B3D)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0x0B3E)
+#define HAL_LL_TIM3_CCDBUFL_REG_ADDRESS (0x0B3E)
+#define HAL_LL_TIM3_CCDBUFH_REG_ADDRESS (0x0B3F)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x0840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x0841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x0842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x0843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x0844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x0846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x0847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x0848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x0849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x084A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x084B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x084C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x084F)
+#define HAL_LL_TIM4_CNTL_REG_ADDRESS (0x0840)
+#define HAL_LL_TIM4_CNTH_REG_ADDRESS (0x0841)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x0846)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x0847)
+#define HAL_LL_TIM4_CCAL_REG_ADDRESS (0x0848)
+#define HAL_LL_TIM4_CCAH_REG_ADDRESS (0x0849)
+#define HAL_LL_TIM4_CCBL_REG_ADDRESS (0x084A)
+#define HAL_LL_TIM4_CCBH_REG_ADDRESS (0x084B)
+#define HAL_LL_TIM4_PERBUFL_REG_ADDRESS (0x0866)
+#define HAL_LL_TIM4_PERBUFH_REG_ADDRESS (0x0867)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x0868)
+#define HAL_LL_TIM4_CCABUFL_REG_ADDRESS (0x0868)
+#define HAL_LL_TIM4_CCABUFH_REG_ADDRESS (0x0869)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x086A)
+#define HAL_LL_TIM4_CCBBUFL_REG_ADDRESS (0x086A)
+#define HAL_LL_TIM4_CCBBUFH_REG_ADDRESS (0x086B)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x0940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x0941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x0942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x0943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x0944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x0946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x0947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x0948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x0949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x094A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x094B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x094C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x094F)
+#define HAL_LL_TIM5_CNTL_REG_ADDRESS (0x0960)
+#define HAL_LL_TIM5_CNTH_REG_ADDRESS (0x0961)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x0966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x0967)
+#define HAL_LL_TIM5_CCAL_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCAH_REG_ADDRESS (0x0969)
+#define HAL_LL_TIM5_CCBL_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBH_REG_ADDRESS (0x096B)
+#define HAL_LL_TIM5_PERBUFL_REG_ADDRESS (0x0966)
+#define HAL_LL_TIM5_PERBUFH_REG_ADDRESS (0x0967)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCABUFL_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCABUFH_REG_ADDRESS (0x0969)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBBUFL_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBBUFH_REG_ADDRESS (0x096B)
+#define HAL_LL_TIM6_CTRLA_REG_ADDRESS (0x0A40)
+#define HAL_LL_TIM6_CTRLB_REG_ADDRESS (0x0A41)
+#define HAL_LL_TIM6_CTRLC_REG_ADDRESS (0x0A42)
+#define HAL_LL_TIM6_CTRLD_REG_ADDRESS (0x0A43)
+#define HAL_LL_TIM6_CTRLE_REG_ADDRESS (0x0A44)
+#define HAL_LL_TIM6_INTCTRLA_REG_ADDRESS (0x0A46)
+#define HAL_LL_TIM6_INTCTRLB_REG_ADDRESS (0x0A47)
+#define HAL_LL_TIM6_CTRLFCLR_REG_ADDRESS (0x0A48)
+#define HAL_LL_TIM6_CTRLFSET_REG_ADDRESS (0x0A49)
+#define HAL_LL_TIM6_CTRLGCLR_REG_ADDRESS (0x0A4A)
+#define HAL_LL_TIM6_CTRLGSET_REG_ADDRESS (0x0A4B)
+#define HAL_LL_TIM6_INTFLAGS_REG_ADDRESS (0x0A4C)
+#define HAL_LL_TIM6_TEMP_REG_ADDRESS (0x0A4F)
+#define HAL_LL_TIM6_CNTL_REG_ADDRESS (0x0A60)
+#define HAL_LL_TIM6_CNTH_REG_ADDRESS (0x0A61)
+#define HAL_LL_TIM6_PERL_REG_ADDRESS (0x0A66)
+#define HAL_LL_TIM6_PERH_REG_ADDRESS (0x0A67)
+#define HAL_LL_TIM6_CCAL_REG_ADDRESS (0x0A68)
+#define HAL_LL_TIM6_CCAH_REG_ADDRESS (0x0A69)
+#define HAL_LL_TIM6_CCBL_REG_ADDRESS (0x0A6A)
+#define HAL_LL_TIM6_CCBH_REG_ADDRESS (0x0A6B)
+#define HAL_LL_TIM6_PERBUFL_REG_ADDRESS (0x0A66)
+#define HAL_LL_TIM6_PERBUFH_REG_ADDRESS (0x0A67)
+#define HAL_LL_TIM6_CCABUF_REG_ADDRESS (0x0A68)
+#define HAL_LL_TIM6_CCABUFL_REG_ADDRESS (0x0A68)
+#define HAL_LL_TIM6_CCABUFH_REG_ADDRESS (0x0A69)
+#define HAL_LL_TIM6_CCBBUF_REG_ADDRESS (0x0A6A)
+#define HAL_LL_TIM6_CCBBUFL_REG_ADDRESS (0x0A6A)
+#define HAL_LL_TIM6_CCBBUFH_REG_ADDRESS (0x0A6B)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTE1_RXC_IVT (61)
+#define HAL_LL_USARTE1_DRE_IVT (62)
+#define HAL_LL_USARTE1_TXC_IVT (63)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+#define HAL_LL_USARTF0_RXC_IVT (119)
+#define HAL_LL_USARTF0_DRE_IVT (120)
+#define HAL_LL_USARTF0_TXC_IVT (121)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTE1_RXC_IVT_ADDRESS (0x7A)
+#define HAL_LL_USARTE1_DRE_IVT_ADDRESS (0x7C)
+#define HAL_LL_USARTE1_TXC_IVT_ADDRESS (0x7E)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+#define HAL_LL_USARTF0_RXC_IVT_ADDRESS (0xEE)
+#define HAL_LL_USARTF0_DRE_IVT_ADDRESS (0xF0)
+#define HAL_LL_USARTF0_TXC_IVT_ADDRESS (0xF2)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA192A3U/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA192A3U/mcu_definitions.h
new file mode 100644
index 000000000..57d3aff20
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA192A3U/mcu_definitions.h
@@ -0,0 +1,721 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH0
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH1
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB2_CH2
+#define ADC0_PB3_CH11
+#define ADC0_PB3_CH3
+#define ADC0_PB4_CH12
+#define ADC0_PB4_CH4
+#define ADC0_PB5_CH13
+#define ADC0_PB5_CH5
+#define ADC0_PB6_CH14
+#define ADC0_PB6_CH6
+#define ADC0_PB7_CH15
+#define ADC0_PB7_CH7
+#define ADC1_PA0_CH0
+#define ADC1_PB0_CH0
+#define ADC1_PB0_CH8
+#define ADC1_PB1_CH1
+#define ADC1_PB1_CH9
+#define ADC1_PB2_CH10
+#define ADC1_PB2_CH2
+#define ADC1_PB3_CH11
+#define ADC1_PB3_CH3
+#define ADC1_PB4_CH12
+#define ADC1_PB4_CH4
+#define ADC1_PB5_CH13
+#define ADC1_PB5_CH5
+#define ADC1_PB6_CH14
+#define ADC1_PB6_CH6
+#define ADC1_PB7_CH15
+#define ADC1_PB7_CH7
+
+#define ADC_MODULE_0 (1)
+#define ADC_MODULE_1 (2)
+
+#define HAL_LL_AN_COUNT (41)
+#define ADC_MODULE_COUNT (2)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+#define HAL_LL_ADC1_CTRLA_REG_ADDRESS (0x240)
+#define HAL_LL_ADC1_BASE_ADDRESS (HAL_LL_ADC1_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC1_CTRLB_REG_ADDRESS (0x241)
+#define HAL_LL_ADC1_REFCTRL_REG_ADDRESS (0x242)
+#define HAL_LL_ADC1_EVCTRL_REG_ADDRESS (0x243)
+#define HAL_LL_ADC1_PRESCALER_REG_ADDRESS (0x244)
+#define HAL_LL_ADC1_INTFLAGS_REG_ADDRESS (0x246)
+#define HAL_LL_ADC1_TEMP_REG_ADDRESS (0x247)
+#define HAL_LL_ADC1_CH0RESL_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0RESH_REG_ADDRESS (0x251)
+#define HAL_LL_ADC1_CH0RES_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH1RESL_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH1RESH_REG_ADDRESS (0x253)
+#define HAL_LL_ADC1_CH1RES_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH2RESL_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH2RESH_REG_ADDRESS (0x255)
+#define HAL_LL_ADC1_CH2RES_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH3RESL_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH3RESH_REG_ADDRESS (0x257)
+#define HAL_LL_ADC1_CH3RES_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH0CTRL_REG_ADDRESS (0x260)
+#define HAL_LL_ADC1_CH0MUXCTRL_REG_ADDRESS (0x261)
+#define HAL_LL_ADC1_CH0INTCTRL_REG_ADDRESS (0x262)
+#define HAL_LL_ADC1_CH0INTFLAGS_REG_ADDRESS (0x263)
+#define HAL_LL_ADC1_CH1CTRL_REG_ADDRESS (0x268)
+#define HAL_LL_ADC1_CH1MUXCTRL_REG_ADDRESS (0x269)
+#define HAL_LL_ADC1_CH1INTCTRL_REG_ADDRESS (0x26A)
+#define HAL_LL_ADC1_CH1INTFLAGS_REG_ADDRESS (0x26B)
+#define HAL_LL_ADC1_CH2CTRL_REG_ADDRESS (0x270)
+#define HAL_LL_ADC1_CH2MUXCTRL_REG_ADDRESS (0x271)
+#define HAL_LL_ADC1_CH2INTCTRL_REG_ADDRESS (0x272)
+#define HAL_LL_ADC1_CH2INTFLAGS_REG_ADDRESS (0x273)
+#define HAL_LL_ADC1_CH3CTRL_REG_ADDRESS (0x278)
+#define HAL_LL_ADC1_CH3MUXCTRL_REG_ADDRESS (0x279)
+#define HAL_LL_ADC1_CH3INTCTRL_REG_ADDRESS (0x27A)
+#define HAL_LL_ADC1_CH3INTFLAGS_REG_ADDRESS (0x27B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_RXD_PD6_ALT
+#define USARTD0_TXD_PD3
+#define USARTD0_TXD_PD7_ALT
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_RXD_PE6_ALT
+#define USARTE0_TXD_PE3
+#define USARTE0_TXD_PE7_ALT
+#define USARTE1_RXD_PE6
+#define USARTE1_TXD_PE7
+#define USARTF0_RXD_PF2
+#define USARTF0_RXD_PF6_ALT
+#define USARTF0_TXD_PF3
+#define USARTF0_TXD_PF7_ALT
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_E1 (6)
+#define UART_MODULE_5 (UART_MODULE_E1)
+#define UART_MODULE_F0 (7)
+#define UART_MODULE_6 (UART_MODULE_F0)
+#define UART_MODULE_COUNT (7)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+#define HAL_LL_USARTE1_DATA_REG_ADDRESS (0xAB0)
+#define HAL_LL_USARTE1_STATUS_REG_ADDRESS (0xAB1)
+#define HAL_LL_USARTE1_CTRLA_REG_ADDRESS (0xAB3)
+#define HAL_LL_USARTE1_CTRLB_REG_ADDRESS (0xAB4)
+#define HAL_LL_USARTE1_CTRLC_REG_ADDRESS (0xAB5)
+#define HAL_LL_USARTE1_BAUDCTRLA_REG_ADDRESS (0xAB6)
+#define HAL_LL_USARTE1_BAUDCTRLB_REG_ADDRESS (0xAB7)
+#define HAL_LL_USARTF0_DATA_REG_ADDRESS (0xBA0)
+#define HAL_LL_USARTF0_STATUS_REG_ADDRESS (0xBA1)
+#define HAL_LL_USARTF0_CTRLA_REG_ADDRESS (0xBA3)
+#define HAL_LL_USARTF0_CTRLB_REG_ADDRESS (0xBA4)
+#define HAL_LL_USARTF0_CTRLC_REG_ADDRESS (0xBA5)
+#define HAL_LL_USARTF0_BAUDCTRLA_REG_ADDRESS (0xBA6)
+#define HAL_LL_USARTF0_BAUDCTRLB_REG_ADDRESS (0xBA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_MOSI_PD7
+#define SPI1_SCK_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+#define SPI2_MISO_PE6
+#define SPI2_MOSI_PE5
+#define SPI2_MOSI_PE7
+#define SPI2_SCK_PE5
+#define SPI2_SCK_PE7
+#define SPI2_SS_PE4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_2 (3)
+#define SPI_MODULE_COUNT (3)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+#define HAL_LL_SPI2_CTRL_REG_ADDRESS (0xAC0)
+#define HAL_LL_SPI2_INTCTRL_REG_ADDRESS (0xAC1)
+#define HAL_LL_SPI2_STATUS_REG_ADDRESS (0xAC2)
+#define HAL_LL_SPI2_DATA_REG_ADDRESS (0xAC3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+#define TIM0_PC4_CH_A
+#define TIM0_PC5_CH_B
+#define TIM0_PC6_CH_C
+#define TIM0_PC7_CH_D
+#define TIM1_PC4_CH_A
+#define TIM1_PC5_CH_B
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM1_PD4_CH_A
+#define TIM1_PD5_CH_B
+#define TIM1_PD6_CH_C
+#define TIM1_PD7_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM2_PE4_CH_A
+#define TIM2_PE5_CH_B
+#define TIM2_PE6_CH_C
+#define TIM2_PE7_CH_D
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+#define TIM6_PE4_CH_A
+#define TIM6_PE5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_5 (5)
+#define TIM_MODULE_6 (6)
+#define TIM_MODULE_COUNT (6)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x94A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x94B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x94C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x94F)
+#define HAL_LL_TIM5_CNT_REG_ADDRESS (0x960)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x967)
+#define HAL_LL_TIM5_PER_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_CCA_REG_ADDRESS (0x968)
+#define HAL_LL_TIM5_CCB_REG_ADDRESS (0x96A)
+#define HAL_LL_TIM5_PERBUF_REG_ADDRESS (0x976)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x978)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x97A)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM6_CTRLA_REG_ADDRESS (0xA40)
+#define HAL_LL_TIM6_CTRLB_REG_ADDRESS (0xA41)
+#define HAL_LL_TIM6_CTRLC_REG_ADDRESS (0xA42)
+#define HAL_LL_TIM6_CTRLD_REG_ADDRESS (0xA43)
+#define HAL_LL_TIM6_CTRLE_REG_ADDRESS (0xA44)
+#define HAL_LL_TIM6_INTCTRLA_REG_ADDRESS (0xA46)
+#define HAL_LL_TIM6_INTCTRLB_REG_ADDRESS (0xA47)
+#define HAL_LL_TIM6_CTRLFCLR_REG_ADDRESS (0xA48)
+#define HAL_LL_TIM6_CTRLFSET_REG_ADDRESS (0xA49)
+#define HAL_LL_TIM6_CTRLGCLR_REG_ADDRESS (0xA4A)
+#define HAL_LL_TIM6_CTRLGSET_REG_ADDRESS (0xA4B)
+#define HAL_LL_TIM6_INTFLAGS_REG_ADDRESS (0xA4C)
+#define HAL_LL_TIM6_TEMP_REG_ADDRESS (0xA4F)
+#define HAL_LL_TIM6_CNT_REG_ADDRESS (0xA60)
+#define HAL_LL_TIM6_PERL_REG_ADDRESS (0xA66)
+#define HAL_LL_TIM6_PERH_REG_ADDRESS (0xA67)
+#define HAL_LL_TIM6_PER_REG_ADDRESS (0xA66)
+#define HAL_LL_TIM6_CCA_REG_ADDRESS (0xA68)
+#define HAL_LL_TIM6_CCB_REG_ADDRESS (0xA6A)
+#define HAL_LL_TIM6_PERBUF_REG_ADDRESS (0xA76)
+#define HAL_LL_TIM6_CCABUF_REG_ADDRESS (0xA78)
+#define HAL_LL_TIM6_CCBBUF_REG_ADDRESS (0xA7A)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0xB00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0xB01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0xB02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0xB03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0xB04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0xB06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0xB07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0xB08)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0xB0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0xB0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0xB0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0xB0F)
+#define HAL_LL_TIM3_PERBUF_REG_ADDRESS (0xB36)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0xB38)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0xB3A)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0xB3C)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0xB3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM3_CNT_REG_ADDRESS (0xB20)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0xB26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0xB27)
+#define HAL_LL_TIM3_CCA_REG_ADDRESS (0xB28)
+#define HAL_LL_TIM3_CCB_REG_ADDRESS (0xB2A)
+#define HAL_LL_TIM3_CCC_REG_ADDRESS (0xB2C)
+#define HAL_LL_TIM3_CCD_REG_ADDRESS (0xB2E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTF_REMAP_REG_ADDRESS (0x6AE)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTE1_RXC_IVT (61)
+#define HAL_LL_USARTE1_DRE_IVT (62)
+#define HAL_LL_USARTE1_TXC_IVT (63)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+#define HAL_LL_USARTF0_RXC_IVT (119)
+#define HAL_LL_USARTF0_DRE_IVT (120)
+#define HAL_LL_USARTF0_TXC_IVT (121)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTE1_RXC_IVT_ADDRESS (0x7A)
+#define HAL_LL_USARTE1_DRE_IVT_ADDRESS (0x7C)
+#define HAL_LL_USARTE1_TXC_IVT_ADDRESS (0x7E)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+#define HAL_LL_USARTF0_RXC_IVT_ADDRESS (0xEE)
+#define HAL_LL_USARTF0_DRE_IVT_ADDRESS (0xF0)
+#define HAL_LL_USARTF0_TXC_IVT_ADDRESS (0xF2)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA192D3/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA192D3/mcu_definitions.h
new file mode 100644
index 000000000..459c73d5c
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA192D3/mcu_definitions.h
@@ -0,0 +1,498 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB3_CH11
+#define ADC0_PB4_CH12
+#define ADC0_PB5_CH13
+#define ADC0_PB6_CH14
+#define ADC0_PB7_CH15
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (16)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_D0 (2)
+#define UART_MODULE_1 (UART_MODULE_D0)
+#define UART_MODULE_E0 (3)
+#define UART_MODULE_2 (UART_MODULE_E0)
+#define UART_MODULE_COUNT (3)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+#define HAL_LL_SPI2_CTRL_REG_ADDRESS (0xAC0)
+#define HAL_LL_SPI2_INTCTRL_REG_ADDRESS (0xAC1)
+#define HAL_LL_SPI2_STATUS_REG_ADDRESS (0xAC2)
+#define HAL_LL_SPI2_DATA_REG_ADDRESS (0xAC3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+// TODO - Alternate pins to be implemented in a future release
+// #define TIM0_PC4_CH_A_ALT
+// #define TIM0_PC5_CH_B_ALT
+// #define TIM0_PC6_CH_C_ALT
+// #define TIM0_PC7_CH_D_ALT
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_4 (5)
+#define TIM_MODULE_COUNT (5)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0xB00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0xB01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0xB02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0xB03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0xB04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0xB06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0xB07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0xB08)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0xB0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0xB0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0xB0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0xB0F)
+#define HAL_LL_TIM3_PERBUF_REG_ADDRESS (0xB36)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0xB38)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0xB3A)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0xB3C)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0xB3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM3_CNT_REG_ADDRESS (0xB20)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0xB26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0xB27)
+#define HAL_LL_TIM3_CCA_REG_ADDRESS (0xB28)
+#define HAL_LL_TIM3_CCB_REG_ADDRESS (0xB2A)
+#define HAL_LL_TIM3_CCC_REG_ADDRESS (0xB2C)
+#define HAL_LL_TIM3_CCD_REG_ADDRESS (0xB2E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTF_REMAP_REG_ADDRESS (0x6AE)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA256A3/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA256A3/mcu_definitions.h
new file mode 100644
index 000000000..4183b74d5
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA256A3/mcu_definitions.h
@@ -0,0 +1,752 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC1_PB0_CH0
+#define ADC1_PB1_CH1
+#define ADC1_PB2_CH2
+#define ADC1_PB3_CH3
+#define ADC1_PB4_CH4
+#define ADC1_PB5_CH5
+#define ADC1_PB6_CH6
+#define ADC1_PB7_CH7
+
+#define ADC_MODULE_0 (1)
+#define ADC_MODULE_1 (2)
+
+#define HAL_LL_AN_COUNT (16)
+#define ADC_MODULE_COUNT (2)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+#define HAL_LL_ADC1_CTRLA_REG_ADDRESS (0x240)
+#define HAL_LL_ADC1_BASE_ADDRESS (HAL_LL_ADC1_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC1_CTRLB_REG_ADDRESS (0x241)
+#define HAL_LL_ADC1_REFCTRL_REG_ADDRESS (0x242)
+#define HAL_LL_ADC1_EVCTRL_REG_ADDRESS (0x243)
+#define HAL_LL_ADC1_PRESCALER_REG_ADDRESS (0x244)
+#define HAL_LL_ADC1_INTFLAGS_REG_ADDRESS (0x246)
+#define HAL_LL_ADC1_TEMP_REG_ADDRESS (0x247)
+#define HAL_LL_ADC1_CH0RESL_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0RESH_REG_ADDRESS (0x251)
+#define HAL_LL_ADC1_CH0RES_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH1RESL_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH1RESH_REG_ADDRESS (0x253)
+#define HAL_LL_ADC1_CH1RES_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH2RESL_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH2RESH_REG_ADDRESS (0x255)
+#define HAL_LL_ADC1_CH2RES_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH3RESL_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH3RESH_REG_ADDRESS (0x257)
+#define HAL_LL_ADC1_CH3RES_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH0CTRL_REG_ADDRESS (0x260)
+#define HAL_LL_ADC1_CH0MUXCTRL_REG_ADDRESS (0x261)
+#define HAL_LL_ADC1_CH0INTCTRL_REG_ADDRESS (0x262)
+#define HAL_LL_ADC1_CH0INTFLAGS_REG_ADDRESS (0x263)
+#define HAL_LL_ADC1_CH1CTRL_REG_ADDRESS (0x268)
+#define HAL_LL_ADC1_CH1MUXCTRL_REG_ADDRESS (0x269)
+#define HAL_LL_ADC1_CH1INTCTRL_REG_ADDRESS (0x26A)
+#define HAL_LL_ADC1_CH1INTFLAGS_REG_ADDRESS (0x26B)
+#define HAL_LL_ADC1_CH2CTRL_REG_ADDRESS (0x270)
+#define HAL_LL_ADC1_CH2MUXCTRL_REG_ADDRESS (0x271)
+#define HAL_LL_ADC1_CH2INTCTRL_REG_ADDRESS (0x272)
+#define HAL_LL_ADC1_CH2INTFLAGS_REG_ADDRESS (0x273)
+#define HAL_LL_ADC1_CH3CTRL_REG_ADDRESS (0x278)
+#define HAL_LL_ADC1_CH3MUXCTRL_REG_ADDRESS (0x279)
+#define HAL_LL_ADC1_CH3INTCTRL_REG_ADDRESS (0x27A)
+#define HAL_LL_ADC1_CH3INTFLAGS_REG_ADDRESS (0x27B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_TXD_PC3
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+#define USARTE1_RXD_PE6
+#define USARTE1_TXD_PE7
+#define USARTF0_RXD_PF2
+#define USARTF0_TXD_PF3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_E1 (6)
+#define UART_MODULE_5 (UART_MODULE_E1)
+#define UART_MODULE_F0 (7)
+#define UART_MODULE_6 (UART_MODULE_F0)
+#define UART_MODULE_COUNT (7)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+#define HAL_LL_USARTE1_DATA_REG_ADDRESS (0xAB0)
+#define HAL_LL_USARTE1_STATUS_REG_ADDRESS (0xAB1)
+#define HAL_LL_USARTE1_CTRLA_REG_ADDRESS (0xAB3)
+#define HAL_LL_USARTE1_CTRLB_REG_ADDRESS (0xAB4)
+#define HAL_LL_USARTE1_CTRLC_REG_ADDRESS (0xAB5)
+#define HAL_LL_USARTE1_BAUDCTRLA_REG_ADDRESS (0xAB6)
+#define HAL_LL_USARTE1_BAUDCTRLB_REG_ADDRESS (0xAB7)
+#define HAL_LL_USARTF0_DATA_REG_ADDRESS (0xBA0)
+#define HAL_LL_USARTF0_STATUS_REG_ADDRESS (0xBA1)
+#define HAL_LL_USARTF0_CTRLA_REG_ADDRESS (0xBA3)
+#define HAL_LL_USARTF0_CTRLB_REG_ADDRESS (0xBA4)
+#define HAL_LL_USARTF0_CTRLC_REG_ADDRESS (0xBA5)
+#define HAL_LL_USARTF0_BAUDCTRLA_REG_ADDRESS (0xBA6)
+#define HAL_LL_USARTF0_BAUDCTRLB_REG_ADDRESS (0xBA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PC4
+#define SPI0_MOSI_PC5
+#define SPI0_MISO_PC6
+#define SPI0_SCK_PC7
+#define SPI1_SS_PD4
+#define SPI1_MOSI_PD5
+#define SPI1_MISO_PD6
+#define SPI1_SCK_PD7
+#define SPI2_SS_PE4
+#define SPI2_MOSI_PE5
+#define SPI2_MISO_PE6
+#define SPI2_SCK_PE7
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_2 (3)
+#define SPI_MODULE_COUNT (3)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x08C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x08C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x08C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x08C3)
+
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x09C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x09C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x09C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x09C3)
+
+#define HAL_LL_SPI2_CTRL_REG_ADDRESS (0x0AC0)
+#define HAL_LL_SPI2_INTCTRL_REG_ADDRESS (0x0AC1)
+#define HAL_LL_SPI2_STATUS_REG_ADDRESS (0x0AC2)
+#define HAL_LL_SPI2_DATA_REG_ADDRESS (0x0AC3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// TCC0 (Timer/Counter0 on PORTC)
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+// TCD0 (Timer/Counter0 on PORTD)
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+// TCE0 (Timer/Counter0 on PORTE)
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+// TCF0 (Timer/Counter0 on PORTF)
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+// TCC1 (Timer/Counter1 on PORTC)
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+// TCD1 (Timer/Counter1 on PORTD)
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+// TCE1 (Timer/Counter1 on PORTE)
+#define TIM6_PE4_CH_A
+#define TIM6_PE5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_4 (5)
+#define TIM_MODULE_5 (6)
+#define TIM_MODULE_6 (7)
+
+#define TIM_MODULE_COUNT (7)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x0800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x0801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x0802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x0803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x0804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x0806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x0807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x0808)
+#define HAL_LL_TIM0_CTRLFSET_REG_ADDRESS (0x0809)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x080A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x080B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x080C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x080F)
+#define HAL_LL_TIM0_CNTL_REG_ADDRESS (0x0820)
+#define HAL_LL_TIM0_CNTH_REG_ADDRESS (0x0821)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x0826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x0827)
+#define HAL_LL_TIM0_CCAL_REG_ADDRESS (0x0828)
+#define HAL_LL_TIM0_CCAH_REG_ADDRESS (0x0829)
+#define HAL_LL_TIM0_CCBL_REG_ADDRESS (0x082A)
+#define HAL_LL_TIM0_CCBH_REG_ADDRESS (0x082B)
+#define HAL_LL_TIM0_CCCL_REG_ADDRESS (0x082C)
+#define HAL_LL_TIM0_CCCH_REG_ADDRESS (0x082D)
+#define HAL_LL_TIM0_CCDL_REG_ADDRESS (0x082E)
+#define HAL_LL_TIM0_CCDH_REG_ADDRESS (0x082F)
+#define HAL_LL_TIM0_PERBUFL_REG_ADDRESS (0x0836)
+#define HAL_LL_TIM0_PERBUFH_REG_ADDRESS (0x0837)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x0838)
+#define HAL_LL_TIM0_CCABUFL_REG_ADDRESS (0x0838)
+#define HAL_LL_TIM0_CCABUFH_REG_ADDRESS (0x0839)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x083A)
+#define HAL_LL_TIM0_CCBBUFL_REG_ADDRESS (0x083A)
+#define HAL_LL_TIM0_CCBBUFH_REG_ADDRESS (0x083B)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x083C)
+#define HAL_LL_TIM0_CCCBUFL_REG_ADDRESS (0x083C)
+#define HAL_LL_TIM0_CCCBUFH_REG_ADDRESS (0x083D)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x083E)
+#define HAL_LL_TIM0_CCDBUFL_REG_ADDRESS (0x083E)
+#define HAL_LL_TIM0_CCDBUFH_REG_ADDRESS (0x083F)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x0900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x0901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x0902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x0903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x0904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x0906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x0907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x0908)
+#define HAL_LL_TIM1_CTRLFSET_REG_ADDRESS (0x0909)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x090A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x090B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x090C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x090F)
+#define HAL_LL_TIM1_CNTL_REG_ADDRESS (0x0920)
+#define HAL_LL_TIM1_CNTH_REG_ADDRESS (0x0921)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x0926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x0927)
+#define HAL_LL_TIM1_CCAL_REG_ADDRESS (0x0928)
+#define HAL_LL_TIM1_CCAH_REG_ADDRESS (0x0929)
+#define HAL_LL_TIM1_CCBL_REG_ADDRESS (0x092A)
+#define HAL_LL_TIM1_CCBH_REG_ADDRESS (0x092B)
+#define HAL_LL_TIM1_CCCL_REG_ADDRESS (0x092C)
+#define HAL_LL_TIM1_CCCH_REG_ADDRESS (0x092D)
+#define HAL_LL_TIM1_CCDL_REG_ADDRESS (0x092E)
+#define HAL_LL_TIM1_CCDH_REG_ADDRESS (0x092F)
+#define HAL_LL_TIM1_PERBUFL_REG_ADDRESS (0x0936)
+#define HAL_LL_TIM1_PERBUFH_REG_ADDRESS (0x0937)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x0938)
+#define HAL_LL_TIM1_CCABUFL_REG_ADDRESS (0x0938)
+#define HAL_LL_TIM1_CCABUFH_REG_ADDRESS (0x0939)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x093A)
+#define HAL_LL_TIM1_CCBBUFL_REG_ADDRESS (0x093A)
+#define HAL_LL_TIM1_CCBBUFH_REG_ADDRESS (0x093B)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x093C)
+#define HAL_LL_TIM1_CCCBUFL_REG_ADDRESS (0x093C)
+#define HAL_LL_TIM1_CCCBUFH_REG_ADDRESS (0x093D)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x093E)
+#define HAL_LL_TIM1_CCDBUFL_REG_ADDRESS (0x093E)
+#define HAL_LL_TIM1_CCDBUFH_REG_ADDRESS (0x093F)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0x0A00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0x0A01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0x0A02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0x0A03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0x0A04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0x0A06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0x0A07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0x0A08)
+#define HAL_LL_TIM2_CTRLFSET_REG_ADDRESS (0x0A09)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0x0A0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0x0A0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0x0A0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0x0A0F)
+#define HAL_LL_TIM2_CNTL_REG_ADDRESS (0x0A20)
+#define HAL_LL_TIM2_CNTH_REG_ADDRESS (0x0A21)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0x0A26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0x0A27)
+#define HAL_LL_TIM2_CCAL_REG_ADDRESS (0x0A28)
+#define HAL_LL_TIM2_CCAH_REG_ADDRESS (0x0A29)
+#define HAL_LL_TIM2_CCBL_REG_ADDRESS (0x0A2A)
+#define HAL_LL_TIM2_CCBH_REG_ADDRESS (0x0A2B)
+#define HAL_LL_TIM2_CCCL_REG_ADDRESS (0x0A2C)
+#define HAL_LL_TIM2_CCCH_REG_ADDRESS (0x0A2D)
+#define HAL_LL_TIM2_CCDL_REG_ADDRESS (0x0A2E)
+#define HAL_LL_TIM2_CCDH_REG_ADDRESS (0x0A2F)
+#define HAL_LL_TIM2_PERBUFL_REG_ADDRESS (0x0A36)
+#define HAL_LL_TIM2_PERBUFH_REG_ADDRESS (0x0A37)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0x0A38)
+#define HAL_LL_TIM2_CCABUFL_REG_ADDRESS (0x0A38)
+#define HAL_LL_TIM2_CCABUFH_REG_ADDRESS (0x0A39)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0x0A3A)
+#define HAL_LL_TIM2_CCBBUFL_REG_ADDRESS (0x0A3A)
+#define HAL_LL_TIM2_CCBBUFH_REG_ADDRESS (0x0A3B)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0x0A3C)
+#define HAL_LL_TIM2_CCCBUFL_REG_ADDRESS (0x0A3C)
+#define HAL_LL_TIM2_CCCBUFH_REG_ADDRESS (0x0A3D)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0x0A3E)
+#define HAL_LL_TIM2_CCDBUFL_REG_ADDRESS (0x0A3E)
+#define HAL_LL_TIM2_CCDBUFH_REG_ADDRESS (0x0A3F)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0x0B00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0x0B01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0x0B02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0x0B03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0x0B04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0x0B06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0x0B07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0x0B08)
+#define HAL_LL_TIM3_CTRLFSET_REG_ADDRESS (0x0B09)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0x0B0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0x0B0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0x0B0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0x0B0F)
+#define HAL_LL_TIM3_CNTL_REG_ADDRESS (0x0B20)
+#define HAL_LL_TIM3_CNTH_REG_ADDRESS (0x0B21)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0x0B26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0x0B27)
+#define HAL_LL_TIM3_CCAL_REG_ADDRESS (0x0B28)
+#define HAL_LL_TIM3_CCAH_REG_ADDRESS (0x0B29)
+#define HAL_LL_TIM3_CCBL_REG_ADDRESS (0x0B2A)
+#define HAL_LL_TIM3_CCBH_REG_ADDRESS (0x0B2B)
+#define HAL_LL_TIM3_CCCL_REG_ADDRESS (0x0B2C)
+#define HAL_LL_TIM3_CCCH_REG_ADDRESS (0x0B2D)
+#define HAL_LL_TIM3_CCDL_REG_ADDRESS (0x0B2E)
+#define HAL_LL_TIM3_CCDH_REG_ADDRESS (0x0B2F)
+#define HAL_LL_TIM3_PERBUFL_REG_ADDRESS (0x0B36)
+#define HAL_LL_TIM3_PERBUFH_REG_ADDRESS (0x0B37)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0x0B38)
+#define HAL_LL_TIM3_CCABUFL_REG_ADDRESS (0x0B38)
+#define HAL_LL_TIM3_CCABUFH_REG_ADDRESS (0x0B39)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0x0B3A)
+#define HAL_LL_TIM3_CCBBUFL_REG_ADDRESS (0x0B3A)
+#define HAL_LL_TIM3_CCBBUFH_REG_ADDRESS (0x0B3B)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0x0B3C)
+#define HAL_LL_TIM3_CCCBUFL_REG_ADDRESS (0x0B3C)
+#define HAL_LL_TIM3_CCCBUFH_REG_ADDRESS (0x0B3D)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0x0B3E)
+#define HAL_LL_TIM3_CCDBUFL_REG_ADDRESS (0x0B3E)
+#define HAL_LL_TIM3_CCDBUFH_REG_ADDRESS (0x0B3F)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x0840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x0841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x0842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x0843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x0844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x0846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x0847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x0848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x0849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x084A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x084B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x084C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x084F)
+#define HAL_LL_TIM4_CNTL_REG_ADDRESS (0x0840)
+#define HAL_LL_TIM4_CNTH_REG_ADDRESS (0x0841)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x0846)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x0847)
+#define HAL_LL_TIM4_CCAL_REG_ADDRESS (0x0848)
+#define HAL_LL_TIM4_CCAH_REG_ADDRESS (0x0849)
+#define HAL_LL_TIM4_CCBL_REG_ADDRESS (0x084A)
+#define HAL_LL_TIM4_CCBH_REG_ADDRESS (0x084B)
+#define HAL_LL_TIM4_PERBUFL_REG_ADDRESS (0x0866)
+#define HAL_LL_TIM4_PERBUFH_REG_ADDRESS (0x0867)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x0868)
+#define HAL_LL_TIM4_CCABUFL_REG_ADDRESS (0x0868)
+#define HAL_LL_TIM4_CCABUFH_REG_ADDRESS (0x0869)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x086A)
+#define HAL_LL_TIM4_CCBBUFL_REG_ADDRESS (0x086A)
+#define HAL_LL_TIM4_CCBBUFH_REG_ADDRESS (0x086B)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x0940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x0941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x0942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x0943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x0944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x0946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x0947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x0948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x0949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x094A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x094B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x094C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x094F)
+#define HAL_LL_TIM5_CNTL_REG_ADDRESS (0x0960)
+#define HAL_LL_TIM5_CNTH_REG_ADDRESS (0x0961)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x0966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x0967)
+#define HAL_LL_TIM5_CCAL_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCAH_REG_ADDRESS (0x0969)
+#define HAL_LL_TIM5_CCBL_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBH_REG_ADDRESS (0x096B)
+#define HAL_LL_TIM5_PERBUFL_REG_ADDRESS (0x0966)
+#define HAL_LL_TIM5_PERBUFH_REG_ADDRESS (0x0967)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCABUFL_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCABUFH_REG_ADDRESS (0x0969)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBBUFL_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBBUFH_REG_ADDRESS (0x096B)
+#define HAL_LL_TIM6_CTRLA_REG_ADDRESS (0x0A40)
+#define HAL_LL_TIM6_CTRLB_REG_ADDRESS (0x0A41)
+#define HAL_LL_TIM6_CTRLC_REG_ADDRESS (0x0A42)
+#define HAL_LL_TIM6_CTRLD_REG_ADDRESS (0x0A43)
+#define HAL_LL_TIM6_CTRLE_REG_ADDRESS (0x0A44)
+#define HAL_LL_TIM6_INTCTRLA_REG_ADDRESS (0x0A46)
+#define HAL_LL_TIM6_INTCTRLB_REG_ADDRESS (0x0A47)
+#define HAL_LL_TIM6_CTRLFCLR_REG_ADDRESS (0x0A48)
+#define HAL_LL_TIM6_CTRLFSET_REG_ADDRESS (0x0A49)
+#define HAL_LL_TIM6_CTRLGCLR_REG_ADDRESS (0x0A4A)
+#define HAL_LL_TIM6_CTRLGSET_REG_ADDRESS (0x0A4B)
+#define HAL_LL_TIM6_INTFLAGS_REG_ADDRESS (0x0A4C)
+#define HAL_LL_TIM6_TEMP_REG_ADDRESS (0x0A4F)
+#define HAL_LL_TIM6_CNTL_REG_ADDRESS (0x0A60)
+#define HAL_LL_TIM6_CNTH_REG_ADDRESS (0x0A61)
+#define HAL_LL_TIM6_PERL_REG_ADDRESS (0x0A66)
+#define HAL_LL_TIM6_PERH_REG_ADDRESS (0x0A67)
+#define HAL_LL_TIM6_CCAL_REG_ADDRESS (0x0A68)
+#define HAL_LL_TIM6_CCAH_REG_ADDRESS (0x0A69)
+#define HAL_LL_TIM6_CCBL_REG_ADDRESS (0x0A6A)
+#define HAL_LL_TIM6_CCBH_REG_ADDRESS (0x0A6B)
+#define HAL_LL_TIM6_PERBUFL_REG_ADDRESS (0x0A66)
+#define HAL_LL_TIM6_PERBUFH_REG_ADDRESS (0x0A67)
+#define HAL_LL_TIM6_CCABUF_REG_ADDRESS (0x0A68)
+#define HAL_LL_TIM6_CCABUFL_REG_ADDRESS (0x0A68)
+#define HAL_LL_TIM6_CCABUFH_REG_ADDRESS (0x0A69)
+#define HAL_LL_TIM6_CCBBUF_REG_ADDRESS (0x0A6A)
+#define HAL_LL_TIM6_CCBBUFL_REG_ADDRESS (0x0A6A)
+#define HAL_LL_TIM6_CCBBUFH_REG_ADDRESS (0x0A6B)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTE1_RXC_IVT (61)
+#define HAL_LL_USARTE1_DRE_IVT (62)
+#define HAL_LL_USARTE1_TXC_IVT (63)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+#define HAL_LL_USARTF0_RXC_IVT (119)
+#define HAL_LL_USARTF0_DRE_IVT (120)
+#define HAL_LL_USARTF0_TXC_IVT (121)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTE1_RXC_IVT_ADDRESS (0x7A)
+#define HAL_LL_USARTE1_DRE_IVT_ADDRESS (0x7C)
+#define HAL_LL_USARTE1_TXC_IVT_ADDRESS (0x7E)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+#define HAL_LL_USARTF0_RXC_IVT_ADDRESS (0xEE)
+#define HAL_LL_USARTF0_DRE_IVT_ADDRESS (0xF0)
+#define HAL_LL_USARTF0_TXC_IVT_ADDRESS (0xF2)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA256A3B/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA256A3B/mcu_definitions.h
new file mode 100644
index 000000000..a30a42210
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA256A3B/mcu_definitions.h
@@ -0,0 +1,735 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC1_PB0_CH0
+#define ADC1_PB1_CH1
+#define ADC1_PB2_CH2
+#define ADC1_PB3_CH3
+#define ADC1_PB4_CH4
+#define ADC1_PB5_CH5
+#define ADC1_PB6_CH6
+#define ADC1_PB7_CH7
+
+#define ADC_MODULE_0 (1)
+#define ADC_MODULE_1 (2)
+
+#define HAL_LL_AN_COUNT (16)
+#define ADC_MODULE_COUNT (2)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+#define HAL_LL_ADC1_CTRLA_REG_ADDRESS (0x240)
+#define HAL_LL_ADC1_BASE_ADDRESS (HAL_LL_ADC1_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC1_CTRLB_REG_ADDRESS (0x241)
+#define HAL_LL_ADC1_REFCTRL_REG_ADDRESS (0x242)
+#define HAL_LL_ADC1_EVCTRL_REG_ADDRESS (0x243)
+#define HAL_LL_ADC1_PRESCALER_REG_ADDRESS (0x244)
+#define HAL_LL_ADC1_INTFLAGS_REG_ADDRESS (0x246)
+#define HAL_LL_ADC1_TEMP_REG_ADDRESS (0x247)
+#define HAL_LL_ADC1_CH0RESL_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0RESH_REG_ADDRESS (0x251)
+#define HAL_LL_ADC1_CH0RES_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH1RESL_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH1RESH_REG_ADDRESS (0x253)
+#define HAL_LL_ADC1_CH1RES_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH2RESL_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH2RESH_REG_ADDRESS (0x255)
+#define HAL_LL_ADC1_CH2RES_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH3RESL_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH3RESH_REG_ADDRESS (0x257)
+#define HAL_LL_ADC1_CH3RES_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH0CTRL_REG_ADDRESS (0x260)
+#define HAL_LL_ADC1_CH0MUXCTRL_REG_ADDRESS (0x261)
+#define HAL_LL_ADC1_CH0INTCTRL_REG_ADDRESS (0x262)
+#define HAL_LL_ADC1_CH0INTFLAGS_REG_ADDRESS (0x263)
+#define HAL_LL_ADC1_CH1CTRL_REG_ADDRESS (0x268)
+#define HAL_LL_ADC1_CH1MUXCTRL_REG_ADDRESS (0x269)
+#define HAL_LL_ADC1_CH1INTCTRL_REG_ADDRESS (0x26A)
+#define HAL_LL_ADC1_CH1INTFLAGS_REG_ADDRESS (0x26B)
+#define HAL_LL_ADC1_CH2CTRL_REG_ADDRESS (0x270)
+#define HAL_LL_ADC1_CH2MUXCTRL_REG_ADDRESS (0x271)
+#define HAL_LL_ADC1_CH2INTCTRL_REG_ADDRESS (0x272)
+#define HAL_LL_ADC1_CH2INTFLAGS_REG_ADDRESS (0x273)
+#define HAL_LL_ADC1_CH3CTRL_REG_ADDRESS (0x278)
+#define HAL_LL_ADC1_CH3MUXCTRL_REG_ADDRESS (0x279)
+#define HAL_LL_ADC1_CH3INTCTRL_REG_ADDRESS (0x27A)
+#define HAL_LL_ADC1_CH3INTFLAGS_REG_ADDRESS (0x27B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_TXD_PC3
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+#define USARTF0_RXD_PF2
+#define USARTF0_TXD_PF3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_F0 (6)
+#define UART_MODULE_5 (UART_MODULE_F0)
+#define UART_MODULE_COUNT (6)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+#define HAL_LL_USARTF0_DATA_REG_ADDRESS (0xBA0)
+#define HAL_LL_USARTF0_STATUS_REG_ADDRESS (0xBA1)
+#define HAL_LL_USARTF0_CTRLA_REG_ADDRESS (0xBA3)
+#define HAL_LL_USARTF0_CTRLB_REG_ADDRESS (0xBA4)
+#define HAL_LL_USARTF0_CTRLC_REG_ADDRESS (0xBA5)
+#define HAL_LL_USARTF0_BAUDCTRLA_REG_ADDRESS (0xBA6)
+#define HAL_LL_USARTF0_BAUDCTRLB_REG_ADDRESS (0xBA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PC4
+#define SPI0_MOSI_PC5
+#define SPI0_MISO_PC6
+#define SPI0_SCK_PC7
+#define SPI1_SS_PD4
+#define SPI1_MOSI_PD5
+#define SPI1_MISO_PD6
+#define SPI1_SCK_PD7
+#define SPI2_SS_PE4
+#define SPI2_MOSI_PE5
+#define SPI2_MISO_PE6
+#define SPI2_SCK_PE7
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_2 (3)
+#define SPI_MODULE_COUNT (3)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x08C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x08C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x08C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x08C3)
+
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x09C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x09C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x09C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x09C3)
+
+#define HAL_LL_SPI2_CTRL_REG_ADDRESS (0x0AC0)
+#define HAL_LL_SPI2_INTCTRL_REG_ADDRESS (0x0AC1)
+#define HAL_LL_SPI2_STATUS_REG_ADDRESS (0x0AC2)
+#define HAL_LL_SPI2_DATA_REG_ADDRESS (0x0AC3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// TCC0 (Timer/Counter0 on PORTC)
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+// TCD0 (Timer/Counter0 on PORTD)
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+// TCE0 (Timer/Counter0 on PORTE)
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+// TCF0 (Timer/Counter0 on PORTF)
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+// TCC1 (Timer/Counter1 on PORTC)
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+// TCD1 (Timer/Counter1 on PORTD)
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+// TCE1 (Timer/Counter1 on PORTE)
+#define TIM6_PE4_CH_A
+#define TIM6_PE5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_4 (5)
+#define TIM_MODULE_5 (6)
+#define TIM_MODULE_6 (7)
+
+#define TIM_MODULE_COUNT (7)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x0800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x0801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x0802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x0803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x0804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x0806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x0807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x0808)
+#define HAL_LL_TIM0_CTRLFSET_REG_ADDRESS (0x0809)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x080A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x080B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x080C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x080F)
+#define HAL_LL_TIM0_CNTL_REG_ADDRESS (0x0820)
+#define HAL_LL_TIM0_CNTH_REG_ADDRESS (0x0821)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x0826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x0827)
+#define HAL_LL_TIM0_CCAL_REG_ADDRESS (0x0828)
+#define HAL_LL_TIM0_CCAH_REG_ADDRESS (0x0829)
+#define HAL_LL_TIM0_CCBL_REG_ADDRESS (0x082A)
+#define HAL_LL_TIM0_CCBH_REG_ADDRESS (0x082B)
+#define HAL_LL_TIM0_CCCL_REG_ADDRESS (0x082C)
+#define HAL_LL_TIM0_CCCH_REG_ADDRESS (0x082D)
+#define HAL_LL_TIM0_CCDL_REG_ADDRESS (0x082E)
+#define HAL_LL_TIM0_CCDH_REG_ADDRESS (0x082F)
+#define HAL_LL_TIM0_PERBUFL_REG_ADDRESS (0x0836)
+#define HAL_LL_TIM0_PERBUFH_REG_ADDRESS (0x0837)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x0838)
+#define HAL_LL_TIM0_CCABUFL_REG_ADDRESS (0x0838)
+#define HAL_LL_TIM0_CCABUFH_REG_ADDRESS (0x0839)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x083A)
+#define HAL_LL_TIM0_CCBBUFL_REG_ADDRESS (0x083A)
+#define HAL_LL_TIM0_CCBBUFH_REG_ADDRESS (0x083B)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x083C)
+#define HAL_LL_TIM0_CCCBUFL_REG_ADDRESS (0x083C)
+#define HAL_LL_TIM0_CCCBUFH_REG_ADDRESS (0x083D)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x083E)
+#define HAL_LL_TIM0_CCDBUFL_REG_ADDRESS (0x083E)
+#define HAL_LL_TIM0_CCDBUFH_REG_ADDRESS (0x083F)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x0900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x0901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x0902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x0903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x0904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x0906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x0907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x0908)
+#define HAL_LL_TIM1_CTRLFSET_REG_ADDRESS (0x0909)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x090A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x090B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x090C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x090F)
+#define HAL_LL_TIM1_CNTL_REG_ADDRESS (0x0920)
+#define HAL_LL_TIM1_CNTH_REG_ADDRESS (0x0921)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x0926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x0927)
+#define HAL_LL_TIM1_CCAL_REG_ADDRESS (0x0928)
+#define HAL_LL_TIM1_CCAH_REG_ADDRESS (0x0929)
+#define HAL_LL_TIM1_CCBL_REG_ADDRESS (0x092A)
+#define HAL_LL_TIM1_CCBH_REG_ADDRESS (0x092B)
+#define HAL_LL_TIM1_CCCL_REG_ADDRESS (0x092C)
+#define HAL_LL_TIM1_CCCH_REG_ADDRESS (0x092D)
+#define HAL_LL_TIM1_CCDL_REG_ADDRESS (0x092E)
+#define HAL_LL_TIM1_CCDH_REG_ADDRESS (0x092F)
+#define HAL_LL_TIM1_PERBUFL_REG_ADDRESS (0x0936)
+#define HAL_LL_TIM1_PERBUFH_REG_ADDRESS (0x0937)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x0938)
+#define HAL_LL_TIM1_CCABUFL_REG_ADDRESS (0x0938)
+#define HAL_LL_TIM1_CCABUFH_REG_ADDRESS (0x0939)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x093A)
+#define HAL_LL_TIM1_CCBBUFL_REG_ADDRESS (0x093A)
+#define HAL_LL_TIM1_CCBBUFH_REG_ADDRESS (0x093B)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x093C)
+#define HAL_LL_TIM1_CCCBUFL_REG_ADDRESS (0x093C)
+#define HAL_LL_TIM1_CCCBUFH_REG_ADDRESS (0x093D)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x093E)
+#define HAL_LL_TIM1_CCDBUFL_REG_ADDRESS (0x093E)
+#define HAL_LL_TIM1_CCDBUFH_REG_ADDRESS (0x093F)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0x0A00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0x0A01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0x0A02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0x0A03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0x0A04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0x0A06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0x0A07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0x0A08)
+#define HAL_LL_TIM2_CTRLFSET_REG_ADDRESS (0x0A09)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0x0A0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0x0A0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0x0A0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0x0A0F)
+#define HAL_LL_TIM2_CNTL_REG_ADDRESS (0x0A20)
+#define HAL_LL_TIM2_CNTH_REG_ADDRESS (0x0A21)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0x0A26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0x0A27)
+#define HAL_LL_TIM2_CCAL_REG_ADDRESS (0x0A28)
+#define HAL_LL_TIM2_CCAH_REG_ADDRESS (0x0A29)
+#define HAL_LL_TIM2_CCBL_REG_ADDRESS (0x0A2A)
+#define HAL_LL_TIM2_CCBH_REG_ADDRESS (0x0A2B)
+#define HAL_LL_TIM2_CCCL_REG_ADDRESS (0x0A2C)
+#define HAL_LL_TIM2_CCCH_REG_ADDRESS (0x0A2D)
+#define HAL_LL_TIM2_CCDL_REG_ADDRESS (0x0A2E)
+#define HAL_LL_TIM2_CCDH_REG_ADDRESS (0x0A2F)
+#define HAL_LL_TIM2_PERBUFL_REG_ADDRESS (0x0A36)
+#define HAL_LL_TIM2_PERBUFH_REG_ADDRESS (0x0A37)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0x0A38)
+#define HAL_LL_TIM2_CCABUFL_REG_ADDRESS (0x0A38)
+#define HAL_LL_TIM2_CCABUFH_REG_ADDRESS (0x0A39)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0x0A3A)
+#define HAL_LL_TIM2_CCBBUFL_REG_ADDRESS (0x0A3A)
+#define HAL_LL_TIM2_CCBBUFH_REG_ADDRESS (0x0A3B)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0x0A3C)
+#define HAL_LL_TIM2_CCCBUFL_REG_ADDRESS (0x0A3C)
+#define HAL_LL_TIM2_CCCBUFH_REG_ADDRESS (0x0A3D)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0x0A3E)
+#define HAL_LL_TIM2_CCDBUFL_REG_ADDRESS (0x0A3E)
+#define HAL_LL_TIM2_CCDBUFH_REG_ADDRESS (0x0A3F)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0x0B00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0x0B01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0x0B02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0x0B03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0x0B04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0x0B06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0x0B07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0x0B08)
+#define HAL_LL_TIM3_CTRLFSET_REG_ADDRESS (0x0B09)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0x0B0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0x0B0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0x0B0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0x0B0F)
+#define HAL_LL_TIM3_CNTL_REG_ADDRESS (0x0B20)
+#define HAL_LL_TIM3_CNTH_REG_ADDRESS (0x0B21)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0x0B26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0x0B27)
+#define HAL_LL_TIM3_CCAL_REG_ADDRESS (0x0B28)
+#define HAL_LL_TIM3_CCAH_REG_ADDRESS (0x0B29)
+#define HAL_LL_TIM3_CCBL_REG_ADDRESS (0x0B2A)
+#define HAL_LL_TIM3_CCBH_REG_ADDRESS (0x0B2B)
+#define HAL_LL_TIM3_CCCL_REG_ADDRESS (0x0B2C)
+#define HAL_LL_TIM3_CCCH_REG_ADDRESS (0x0B2D)
+#define HAL_LL_TIM3_CCDL_REG_ADDRESS (0x0B2E)
+#define HAL_LL_TIM3_CCDH_REG_ADDRESS (0x0B2F)
+#define HAL_LL_TIM3_PERBUFL_REG_ADDRESS (0x0B36)
+#define HAL_LL_TIM3_PERBUFH_REG_ADDRESS (0x0B37)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0x0B38)
+#define HAL_LL_TIM3_CCABUFL_REG_ADDRESS (0x0B38)
+#define HAL_LL_TIM3_CCABUFH_REG_ADDRESS (0x0B39)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0x0B3A)
+#define HAL_LL_TIM3_CCBBUFL_REG_ADDRESS (0x0B3A)
+#define HAL_LL_TIM3_CCBBUFH_REG_ADDRESS (0x0B3B)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0x0B3C)
+#define HAL_LL_TIM3_CCCBUFL_REG_ADDRESS (0x0B3C)
+#define HAL_LL_TIM3_CCCBUFH_REG_ADDRESS (0x0B3D)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0x0B3E)
+#define HAL_LL_TIM3_CCDBUFL_REG_ADDRESS (0x0B3E)
+#define HAL_LL_TIM3_CCDBUFH_REG_ADDRESS (0x0B3F)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x0840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x0841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x0842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x0843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x0844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x0846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x0847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x0848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x0849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x084A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x084B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x084C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x084F)
+#define HAL_LL_TIM4_CNTL_REG_ADDRESS (0x0840)
+#define HAL_LL_TIM4_CNTH_REG_ADDRESS (0x0841)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x0846)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x0847)
+#define HAL_LL_TIM4_CCAL_REG_ADDRESS (0x0848)
+#define HAL_LL_TIM4_CCAH_REG_ADDRESS (0x0849)
+#define HAL_LL_TIM4_CCBL_REG_ADDRESS (0x084A)
+#define HAL_LL_TIM4_CCBH_REG_ADDRESS (0x084B)
+#define HAL_LL_TIM4_PERBUFL_REG_ADDRESS (0x0866)
+#define HAL_LL_TIM4_PERBUFH_REG_ADDRESS (0x0867)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x0868)
+#define HAL_LL_TIM4_CCABUFL_REG_ADDRESS (0x0868)
+#define HAL_LL_TIM4_CCABUFH_REG_ADDRESS (0x0869)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x086A)
+#define HAL_LL_TIM4_CCBBUFL_REG_ADDRESS (0x086A)
+#define HAL_LL_TIM4_CCBBUFH_REG_ADDRESS (0x086B)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x0940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x0941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x0942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x0943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x0944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x0946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x0947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x0948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x0949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x094A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x094B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x094C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x094F)
+#define HAL_LL_TIM5_CNTL_REG_ADDRESS (0x0960)
+#define HAL_LL_TIM5_CNTH_REG_ADDRESS (0x0961)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x0966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x0967)
+#define HAL_LL_TIM5_CCAL_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCAH_REG_ADDRESS (0x0969)
+#define HAL_LL_TIM5_CCBL_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBH_REG_ADDRESS (0x096B)
+#define HAL_LL_TIM5_PERBUFL_REG_ADDRESS (0x0966)
+#define HAL_LL_TIM5_PERBUFH_REG_ADDRESS (0x0967)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCABUFL_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCABUFH_REG_ADDRESS (0x0969)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBBUFL_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBBUFH_REG_ADDRESS (0x096B)
+#define HAL_LL_TIM6_CTRLA_REG_ADDRESS (0x0A40)
+#define HAL_LL_TIM6_CTRLB_REG_ADDRESS (0x0A41)
+#define HAL_LL_TIM6_CTRLC_REG_ADDRESS (0x0A42)
+#define HAL_LL_TIM6_CTRLD_REG_ADDRESS (0x0A43)
+#define HAL_LL_TIM6_CTRLE_REG_ADDRESS (0x0A44)
+#define HAL_LL_TIM6_INTCTRLA_REG_ADDRESS (0x0A46)
+#define HAL_LL_TIM6_INTCTRLB_REG_ADDRESS (0x0A47)
+#define HAL_LL_TIM6_CTRLFCLR_REG_ADDRESS (0x0A48)
+#define HAL_LL_TIM6_CTRLFSET_REG_ADDRESS (0x0A49)
+#define HAL_LL_TIM6_CTRLGCLR_REG_ADDRESS (0x0A4A)
+#define HAL_LL_TIM6_CTRLGSET_REG_ADDRESS (0x0A4B)
+#define HAL_LL_TIM6_INTFLAGS_REG_ADDRESS (0x0A4C)
+#define HAL_LL_TIM6_TEMP_REG_ADDRESS (0x0A4F)
+#define HAL_LL_TIM6_CNTL_REG_ADDRESS (0x0A60)
+#define HAL_LL_TIM6_CNTH_REG_ADDRESS (0x0A61)
+#define HAL_LL_TIM6_PERL_REG_ADDRESS (0x0A66)
+#define HAL_LL_TIM6_PERH_REG_ADDRESS (0x0A67)
+#define HAL_LL_TIM6_CCAL_REG_ADDRESS (0x0A68)
+#define HAL_LL_TIM6_CCAH_REG_ADDRESS (0x0A69)
+#define HAL_LL_TIM6_CCBL_REG_ADDRESS (0x0A6A)
+#define HAL_LL_TIM6_CCBH_REG_ADDRESS (0x0A6B)
+#define HAL_LL_TIM6_PERBUFL_REG_ADDRESS (0x0A66)
+#define HAL_LL_TIM6_PERBUFH_REG_ADDRESS (0x0A67)
+#define HAL_LL_TIM6_CCABUF_REG_ADDRESS (0x0A68)
+#define HAL_LL_TIM6_CCABUFL_REG_ADDRESS (0x0A68)
+#define HAL_LL_TIM6_CCABUFH_REG_ADDRESS (0x0A69)
+#define HAL_LL_TIM6_CCBBUF_REG_ADDRESS (0x0A6A)
+#define HAL_LL_TIM6_CCBBUFL_REG_ADDRESS (0x0A6A)
+#define HAL_LL_TIM6_CCBBUFH_REG_ADDRESS (0x0A6B)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+#define HAL_LL_USARTF0_RXC_IVT (119)
+#define HAL_LL_USARTF0_DRE_IVT (120)
+#define HAL_LL_USARTF0_TXC_IVT (121)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+#define HAL_LL_USARTF0_RXC_IVT_ADDRESS (0xEE)
+#define HAL_LL_USARTF0_DRE_IVT_ADDRESS (0xF0)
+#define HAL_LL_USARTF0_TXC_IVT_ADDRESS (0xF2)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA256A3BU/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA256A3BU/mcu_definitions.h
new file mode 100644
index 000000000..9e31b286d
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA256A3BU/mcu_definitions.h
@@ -0,0 +1,682 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH0
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH1
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB2_CH2
+#define ADC0_PB3_CH11
+#define ADC0_PB3_CH3
+#define ADC0_PB4_CH12
+#define ADC0_PB4_CH4
+#define ADC0_PB5_CH13
+#define ADC0_PB5_CH5
+#define ADC0_PB6_CH14
+#define ADC0_PB6_CH6
+#define ADC0_PB7_CH15
+#define ADC0_PB7_CH7
+#define ADC1_PA0_CH0
+#define ADC1_PB0_CH0
+#define ADC1_PB0_CH8
+#define ADC1_PB1_CH1
+#define ADC1_PB1_CH9
+#define ADC1_PB2_CH10
+#define ADC1_PB2_CH2
+#define ADC1_PB3_CH11
+#define ADC1_PB3_CH3
+#define ADC1_PB4_CH12
+#define ADC1_PB4_CH4
+#define ADC1_PB5_CH13
+#define ADC1_PB5_CH5
+#define ADC1_PB6_CH14
+#define ADC1_PB6_CH6
+#define ADC1_PB7_CH15
+#define ADC1_PB7_CH7
+
+#define ADC_MODULE_0 (1)
+#define ADC_MODULE_1 (2)
+
+#define HAL_LL_AN_COUNT (41)
+#define ADC_MODULE_COUNT (2)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+#define HAL_LL_ADC1_CTRLA_REG_ADDRESS (0x240)
+#define HAL_LL_ADC1_BASE_ADDRESS (HAL_LL_ADC1_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC1_CTRLB_REG_ADDRESS (0x241)
+#define HAL_LL_ADC1_REFCTRL_REG_ADDRESS (0x242)
+#define HAL_LL_ADC1_EVCTRL_REG_ADDRESS (0x243)
+#define HAL_LL_ADC1_PRESCALER_REG_ADDRESS (0x244)
+#define HAL_LL_ADC1_INTFLAGS_REG_ADDRESS (0x246)
+#define HAL_LL_ADC1_TEMP_REG_ADDRESS (0x247)
+#define HAL_LL_ADC1_CH0RESL_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0RESH_REG_ADDRESS (0x251)
+#define HAL_LL_ADC1_CH0RES_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH1RESL_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH1RESH_REG_ADDRESS (0x253)
+#define HAL_LL_ADC1_CH1RES_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH2RESL_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH2RESH_REG_ADDRESS (0x255)
+#define HAL_LL_ADC1_CH2RES_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH3RESL_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH3RESH_REG_ADDRESS (0x257)
+#define HAL_LL_ADC1_CH3RES_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH0CTRL_REG_ADDRESS (0x260)
+#define HAL_LL_ADC1_CH0MUXCTRL_REG_ADDRESS (0x261)
+#define HAL_LL_ADC1_CH0INTCTRL_REG_ADDRESS (0x262)
+#define HAL_LL_ADC1_CH0INTFLAGS_REG_ADDRESS (0x263)
+#define HAL_LL_ADC1_CH1CTRL_REG_ADDRESS (0x268)
+#define HAL_LL_ADC1_CH1MUXCTRL_REG_ADDRESS (0x269)
+#define HAL_LL_ADC1_CH1INTCTRL_REG_ADDRESS (0x26A)
+#define HAL_LL_ADC1_CH1INTFLAGS_REG_ADDRESS (0x26B)
+#define HAL_LL_ADC1_CH2CTRL_REG_ADDRESS (0x270)
+#define HAL_LL_ADC1_CH2MUXCTRL_REG_ADDRESS (0x271)
+#define HAL_LL_ADC1_CH2INTCTRL_REG_ADDRESS (0x272)
+#define HAL_LL_ADC1_CH2INTFLAGS_REG_ADDRESS (0x273)
+#define HAL_LL_ADC1_CH3CTRL_REG_ADDRESS (0x278)
+#define HAL_LL_ADC1_CH3MUXCTRL_REG_ADDRESS (0x279)
+#define HAL_LL_ADC1_CH3INTCTRL_REG_ADDRESS (0x27A)
+#define HAL_LL_ADC1_CH3INTFLAGS_REG_ADDRESS (0x27B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_RXD_PD6_ALT
+#define USARTD0_TXD_PD3
+#define USARTD0_TXD_PD7_ALT
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+#define USARTF0_RXD_PF2
+#define USARTF0_TXD_PF3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_F0 (6)
+#define UART_MODULE_5 (UART_MODULE_F0)
+#define UART_MODULE_COUNT (6)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+#define HAL_LL_USARTF0_DATA_REG_ADDRESS (0xBA0)
+#define HAL_LL_USARTF0_STATUS_REG_ADDRESS (0xBA1)
+#define HAL_LL_USARTF0_CTRLA_REG_ADDRESS (0xBA3)
+#define HAL_LL_USARTF0_CTRLB_REG_ADDRESS (0xBA4)
+#define HAL_LL_USARTF0_CTRLC_REG_ADDRESS (0xBA5)
+#define HAL_LL_USARTF0_BAUDCTRLA_REG_ADDRESS (0xBA6)
+#define HAL_LL_USARTF0_BAUDCTRLB_REG_ADDRESS (0xBA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_MOSI_PD7
+#define SPI1_SCK_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+#define TIM0_PC4_CH_A
+#define TIM0_PC5_CH_B
+#define TIM0_PC6_CH_C
+#define TIM0_PC7_CH_D
+#define TIM1_PC4_CH_A
+#define TIM1_PC5_CH_B
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM1_PD4_CH_A
+#define TIM1_PD5_CH_B
+#define TIM1_PD6_CH_C
+#define TIM1_PD7_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+#define TIM6_PE4_CH_A
+#define TIM6_PE5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_5 (5)
+#define TIM_MODULE_6 (6)
+#define TIM_MODULE_COUNT (6)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x94A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x94B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x94C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x94F)
+#define HAL_LL_TIM5_CNT_REG_ADDRESS (0x960)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x967)
+#define HAL_LL_TIM5_PER_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_CCA_REG_ADDRESS (0x968)
+#define HAL_LL_TIM5_CCB_REG_ADDRESS (0x96A)
+#define HAL_LL_TIM5_PERBUF_REG_ADDRESS (0x976)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x978)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x97A)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM6_CTRLA_REG_ADDRESS (0xA40)
+#define HAL_LL_TIM6_CTRLB_REG_ADDRESS (0xA41)
+#define HAL_LL_TIM6_CTRLC_REG_ADDRESS (0xA42)
+#define HAL_LL_TIM6_CTRLD_REG_ADDRESS (0xA43)
+#define HAL_LL_TIM6_CTRLE_REG_ADDRESS (0xA44)
+#define HAL_LL_TIM6_INTCTRLA_REG_ADDRESS (0xA46)
+#define HAL_LL_TIM6_INTCTRLB_REG_ADDRESS (0xA47)
+#define HAL_LL_TIM6_CTRLFCLR_REG_ADDRESS (0xA48)
+#define HAL_LL_TIM6_CTRLFSET_REG_ADDRESS (0xA49)
+#define HAL_LL_TIM6_CTRLGCLR_REG_ADDRESS (0xA4A)
+#define HAL_LL_TIM6_CTRLGSET_REG_ADDRESS (0xA4B)
+#define HAL_LL_TIM6_INTFLAGS_REG_ADDRESS (0xA4C)
+#define HAL_LL_TIM6_TEMP_REG_ADDRESS (0xA4F)
+#define HAL_LL_TIM6_CNT_REG_ADDRESS (0xA60)
+#define HAL_LL_TIM6_PERL_REG_ADDRESS (0xA66)
+#define HAL_LL_TIM6_PERH_REG_ADDRESS (0xA67)
+#define HAL_LL_TIM6_PER_REG_ADDRESS (0xA66)
+#define HAL_LL_TIM6_CCA_REG_ADDRESS (0xA68)
+#define HAL_LL_TIM6_CCB_REG_ADDRESS (0xA6A)
+#define HAL_LL_TIM6_PERBUF_REG_ADDRESS (0xA76)
+#define HAL_LL_TIM6_CCABUF_REG_ADDRESS (0xA78)
+#define HAL_LL_TIM6_CCBBUF_REG_ADDRESS (0xA7A)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0xB00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0xB01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0xB02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0xB03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0xB04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0xB06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0xB07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0xB08)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0xB0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0xB0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0xB0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0xB0F)
+#define HAL_LL_TIM3_PERBUF_REG_ADDRESS (0xB36)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0xB38)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0xB3A)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0xB3C)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0xB3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM3_CNT_REG_ADDRESS (0xB20)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0xB26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0xB27)
+#define HAL_LL_TIM3_CCA_REG_ADDRESS (0xB28)
+#define HAL_LL_TIM3_CCB_REG_ADDRESS (0xB2A)
+#define HAL_LL_TIM3_CCC_REG_ADDRESS (0xB2C)
+#define HAL_LL_TIM3_CCD_REG_ADDRESS (0xB2E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTF_REMAP_REG_ADDRESS (0x6AE)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+#define HAL_LL_USARTF0_RXC_IVT (119)
+#define HAL_LL_USARTF0_DRE_IVT (120)
+#define HAL_LL_USARTF0_TXC_IVT (121)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+#define HAL_LL_USARTF0_RXC_IVT_ADDRESS (0xEE)
+#define HAL_LL_USARTF0_DRE_IVT_ADDRESS (0xF0)
+#define HAL_LL_USARTF0_TXC_IVT_ADDRESS (0xF2)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA256A3U/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA256A3U/mcu_definitions.h
new file mode 100644
index 000000000..57d3aff20
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA256A3U/mcu_definitions.h
@@ -0,0 +1,721 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH0
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH1
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB2_CH2
+#define ADC0_PB3_CH11
+#define ADC0_PB3_CH3
+#define ADC0_PB4_CH12
+#define ADC0_PB4_CH4
+#define ADC0_PB5_CH13
+#define ADC0_PB5_CH5
+#define ADC0_PB6_CH14
+#define ADC0_PB6_CH6
+#define ADC0_PB7_CH15
+#define ADC0_PB7_CH7
+#define ADC1_PA0_CH0
+#define ADC1_PB0_CH0
+#define ADC1_PB0_CH8
+#define ADC1_PB1_CH1
+#define ADC1_PB1_CH9
+#define ADC1_PB2_CH10
+#define ADC1_PB2_CH2
+#define ADC1_PB3_CH11
+#define ADC1_PB3_CH3
+#define ADC1_PB4_CH12
+#define ADC1_PB4_CH4
+#define ADC1_PB5_CH13
+#define ADC1_PB5_CH5
+#define ADC1_PB6_CH14
+#define ADC1_PB6_CH6
+#define ADC1_PB7_CH15
+#define ADC1_PB7_CH7
+
+#define ADC_MODULE_0 (1)
+#define ADC_MODULE_1 (2)
+
+#define HAL_LL_AN_COUNT (41)
+#define ADC_MODULE_COUNT (2)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+#define HAL_LL_ADC1_CTRLA_REG_ADDRESS (0x240)
+#define HAL_LL_ADC1_BASE_ADDRESS (HAL_LL_ADC1_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC1_CTRLB_REG_ADDRESS (0x241)
+#define HAL_LL_ADC1_REFCTRL_REG_ADDRESS (0x242)
+#define HAL_LL_ADC1_EVCTRL_REG_ADDRESS (0x243)
+#define HAL_LL_ADC1_PRESCALER_REG_ADDRESS (0x244)
+#define HAL_LL_ADC1_INTFLAGS_REG_ADDRESS (0x246)
+#define HAL_LL_ADC1_TEMP_REG_ADDRESS (0x247)
+#define HAL_LL_ADC1_CH0RESL_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0RESH_REG_ADDRESS (0x251)
+#define HAL_LL_ADC1_CH0RES_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH1RESL_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH1RESH_REG_ADDRESS (0x253)
+#define HAL_LL_ADC1_CH1RES_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH2RESL_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH2RESH_REG_ADDRESS (0x255)
+#define HAL_LL_ADC1_CH2RES_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH3RESL_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH3RESH_REG_ADDRESS (0x257)
+#define HAL_LL_ADC1_CH3RES_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH0CTRL_REG_ADDRESS (0x260)
+#define HAL_LL_ADC1_CH0MUXCTRL_REG_ADDRESS (0x261)
+#define HAL_LL_ADC1_CH0INTCTRL_REG_ADDRESS (0x262)
+#define HAL_LL_ADC1_CH0INTFLAGS_REG_ADDRESS (0x263)
+#define HAL_LL_ADC1_CH1CTRL_REG_ADDRESS (0x268)
+#define HAL_LL_ADC1_CH1MUXCTRL_REG_ADDRESS (0x269)
+#define HAL_LL_ADC1_CH1INTCTRL_REG_ADDRESS (0x26A)
+#define HAL_LL_ADC1_CH1INTFLAGS_REG_ADDRESS (0x26B)
+#define HAL_LL_ADC1_CH2CTRL_REG_ADDRESS (0x270)
+#define HAL_LL_ADC1_CH2MUXCTRL_REG_ADDRESS (0x271)
+#define HAL_LL_ADC1_CH2INTCTRL_REG_ADDRESS (0x272)
+#define HAL_LL_ADC1_CH2INTFLAGS_REG_ADDRESS (0x273)
+#define HAL_LL_ADC1_CH3CTRL_REG_ADDRESS (0x278)
+#define HAL_LL_ADC1_CH3MUXCTRL_REG_ADDRESS (0x279)
+#define HAL_LL_ADC1_CH3INTCTRL_REG_ADDRESS (0x27A)
+#define HAL_LL_ADC1_CH3INTFLAGS_REG_ADDRESS (0x27B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_RXD_PD6_ALT
+#define USARTD0_TXD_PD3
+#define USARTD0_TXD_PD7_ALT
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_RXD_PE6_ALT
+#define USARTE0_TXD_PE3
+#define USARTE0_TXD_PE7_ALT
+#define USARTE1_RXD_PE6
+#define USARTE1_TXD_PE7
+#define USARTF0_RXD_PF2
+#define USARTF0_RXD_PF6_ALT
+#define USARTF0_TXD_PF3
+#define USARTF0_TXD_PF7_ALT
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_E1 (6)
+#define UART_MODULE_5 (UART_MODULE_E1)
+#define UART_MODULE_F0 (7)
+#define UART_MODULE_6 (UART_MODULE_F0)
+#define UART_MODULE_COUNT (7)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+#define HAL_LL_USARTE1_DATA_REG_ADDRESS (0xAB0)
+#define HAL_LL_USARTE1_STATUS_REG_ADDRESS (0xAB1)
+#define HAL_LL_USARTE1_CTRLA_REG_ADDRESS (0xAB3)
+#define HAL_LL_USARTE1_CTRLB_REG_ADDRESS (0xAB4)
+#define HAL_LL_USARTE1_CTRLC_REG_ADDRESS (0xAB5)
+#define HAL_LL_USARTE1_BAUDCTRLA_REG_ADDRESS (0xAB6)
+#define HAL_LL_USARTE1_BAUDCTRLB_REG_ADDRESS (0xAB7)
+#define HAL_LL_USARTF0_DATA_REG_ADDRESS (0xBA0)
+#define HAL_LL_USARTF0_STATUS_REG_ADDRESS (0xBA1)
+#define HAL_LL_USARTF0_CTRLA_REG_ADDRESS (0xBA3)
+#define HAL_LL_USARTF0_CTRLB_REG_ADDRESS (0xBA4)
+#define HAL_LL_USARTF0_CTRLC_REG_ADDRESS (0xBA5)
+#define HAL_LL_USARTF0_BAUDCTRLA_REG_ADDRESS (0xBA6)
+#define HAL_LL_USARTF0_BAUDCTRLB_REG_ADDRESS (0xBA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_MOSI_PD7
+#define SPI1_SCK_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+#define SPI2_MISO_PE6
+#define SPI2_MOSI_PE5
+#define SPI2_MOSI_PE7
+#define SPI2_SCK_PE5
+#define SPI2_SCK_PE7
+#define SPI2_SS_PE4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_2 (3)
+#define SPI_MODULE_COUNT (3)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+#define HAL_LL_SPI2_CTRL_REG_ADDRESS (0xAC0)
+#define HAL_LL_SPI2_INTCTRL_REG_ADDRESS (0xAC1)
+#define HAL_LL_SPI2_STATUS_REG_ADDRESS (0xAC2)
+#define HAL_LL_SPI2_DATA_REG_ADDRESS (0xAC3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+#define TIM0_PC4_CH_A
+#define TIM0_PC5_CH_B
+#define TIM0_PC6_CH_C
+#define TIM0_PC7_CH_D
+#define TIM1_PC4_CH_A
+#define TIM1_PC5_CH_B
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM1_PD4_CH_A
+#define TIM1_PD5_CH_B
+#define TIM1_PD6_CH_C
+#define TIM1_PD7_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM2_PE4_CH_A
+#define TIM2_PE5_CH_B
+#define TIM2_PE6_CH_C
+#define TIM2_PE7_CH_D
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+#define TIM6_PE4_CH_A
+#define TIM6_PE5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_5 (5)
+#define TIM_MODULE_6 (6)
+#define TIM_MODULE_COUNT (6)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x94A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x94B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x94C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x94F)
+#define HAL_LL_TIM5_CNT_REG_ADDRESS (0x960)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x967)
+#define HAL_LL_TIM5_PER_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_CCA_REG_ADDRESS (0x968)
+#define HAL_LL_TIM5_CCB_REG_ADDRESS (0x96A)
+#define HAL_LL_TIM5_PERBUF_REG_ADDRESS (0x976)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x978)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x97A)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM6_CTRLA_REG_ADDRESS (0xA40)
+#define HAL_LL_TIM6_CTRLB_REG_ADDRESS (0xA41)
+#define HAL_LL_TIM6_CTRLC_REG_ADDRESS (0xA42)
+#define HAL_LL_TIM6_CTRLD_REG_ADDRESS (0xA43)
+#define HAL_LL_TIM6_CTRLE_REG_ADDRESS (0xA44)
+#define HAL_LL_TIM6_INTCTRLA_REG_ADDRESS (0xA46)
+#define HAL_LL_TIM6_INTCTRLB_REG_ADDRESS (0xA47)
+#define HAL_LL_TIM6_CTRLFCLR_REG_ADDRESS (0xA48)
+#define HAL_LL_TIM6_CTRLFSET_REG_ADDRESS (0xA49)
+#define HAL_LL_TIM6_CTRLGCLR_REG_ADDRESS (0xA4A)
+#define HAL_LL_TIM6_CTRLGSET_REG_ADDRESS (0xA4B)
+#define HAL_LL_TIM6_INTFLAGS_REG_ADDRESS (0xA4C)
+#define HAL_LL_TIM6_TEMP_REG_ADDRESS (0xA4F)
+#define HAL_LL_TIM6_CNT_REG_ADDRESS (0xA60)
+#define HAL_LL_TIM6_PERL_REG_ADDRESS (0xA66)
+#define HAL_LL_TIM6_PERH_REG_ADDRESS (0xA67)
+#define HAL_LL_TIM6_PER_REG_ADDRESS (0xA66)
+#define HAL_LL_TIM6_CCA_REG_ADDRESS (0xA68)
+#define HAL_LL_TIM6_CCB_REG_ADDRESS (0xA6A)
+#define HAL_LL_TIM6_PERBUF_REG_ADDRESS (0xA76)
+#define HAL_LL_TIM6_CCABUF_REG_ADDRESS (0xA78)
+#define HAL_LL_TIM6_CCBBUF_REG_ADDRESS (0xA7A)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0xB00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0xB01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0xB02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0xB03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0xB04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0xB06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0xB07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0xB08)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0xB0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0xB0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0xB0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0xB0F)
+#define HAL_LL_TIM3_PERBUF_REG_ADDRESS (0xB36)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0xB38)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0xB3A)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0xB3C)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0xB3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM3_CNT_REG_ADDRESS (0xB20)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0xB26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0xB27)
+#define HAL_LL_TIM3_CCA_REG_ADDRESS (0xB28)
+#define HAL_LL_TIM3_CCB_REG_ADDRESS (0xB2A)
+#define HAL_LL_TIM3_CCC_REG_ADDRESS (0xB2C)
+#define HAL_LL_TIM3_CCD_REG_ADDRESS (0xB2E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTF_REMAP_REG_ADDRESS (0x6AE)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTE1_RXC_IVT (61)
+#define HAL_LL_USARTE1_DRE_IVT (62)
+#define HAL_LL_USARTE1_TXC_IVT (63)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+#define HAL_LL_USARTF0_RXC_IVT (119)
+#define HAL_LL_USARTF0_DRE_IVT (120)
+#define HAL_LL_USARTF0_TXC_IVT (121)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTE1_RXC_IVT_ADDRESS (0x7A)
+#define HAL_LL_USARTE1_DRE_IVT_ADDRESS (0x7C)
+#define HAL_LL_USARTE1_TXC_IVT_ADDRESS (0x7E)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+#define HAL_LL_USARTF0_RXC_IVT_ADDRESS (0xEE)
+#define HAL_LL_USARTF0_DRE_IVT_ADDRESS (0xF0)
+#define HAL_LL_USARTF0_TXC_IVT_ADDRESS (0xF2)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA256D3/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA256D3/mcu_definitions.h
new file mode 100644
index 000000000..459c73d5c
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA256D3/mcu_definitions.h
@@ -0,0 +1,498 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB3_CH11
+#define ADC0_PB4_CH12
+#define ADC0_PB5_CH13
+#define ADC0_PB6_CH14
+#define ADC0_PB7_CH15
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (16)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_D0 (2)
+#define UART_MODULE_1 (UART_MODULE_D0)
+#define UART_MODULE_E0 (3)
+#define UART_MODULE_2 (UART_MODULE_E0)
+#define UART_MODULE_COUNT (3)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+#define HAL_LL_SPI2_CTRL_REG_ADDRESS (0xAC0)
+#define HAL_LL_SPI2_INTCTRL_REG_ADDRESS (0xAC1)
+#define HAL_LL_SPI2_STATUS_REG_ADDRESS (0xAC2)
+#define HAL_LL_SPI2_DATA_REG_ADDRESS (0xAC3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+// TODO - Alternate pins to be implemented in a future release
+// #define TIM0_PC4_CH_A_ALT
+// #define TIM0_PC5_CH_B_ALT
+// #define TIM0_PC6_CH_C_ALT
+// #define TIM0_PC7_CH_D_ALT
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_4 (5)
+#define TIM_MODULE_COUNT (5)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0xB00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0xB01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0xB02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0xB03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0xB04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0xB06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0xB07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0xB08)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0xB0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0xB0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0xB0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0xB0F)
+#define HAL_LL_TIM3_PERBUF_REG_ADDRESS (0xB36)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0xB38)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0xB3A)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0xB3C)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0xB3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM3_CNT_REG_ADDRESS (0xB20)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0xB26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0xB27)
+#define HAL_LL_TIM3_CCA_REG_ADDRESS (0xB28)
+#define HAL_LL_TIM3_CCB_REG_ADDRESS (0xB2A)
+#define HAL_LL_TIM3_CCC_REG_ADDRESS (0xB2C)
+#define HAL_LL_TIM3_CCD_REG_ADDRESS (0xB2E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTF_REMAP_REG_ADDRESS (0x6AE)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA32A4/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA32A4/mcu_definitions.h
new file mode 100644
index 000000000..73307f259
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA32A4/mcu_definitions.h
@@ -0,0 +1,591 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB3_CH11
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (12)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS_ALTERNATE (0x224)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS_ALTERNATE (0x224)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS_ALTERNATE (0x225)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS_ALTERNATE (0x22C)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS_ALTERNATE (0x22C)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS_ALTERNATE (0x22)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS_ALTERNATE (0x234)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS_ALTERNATE (0x234)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS_ALTERNATE (0x235)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS_ALTERNATE (0x23C)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS_ALTERNATE (0x23C)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS_ALTERNATE (0x23)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_TXD_PC3
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_COUNT (5)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PC4
+#define SPI0_MOSI_PC5
+#define SPI0_MISO_PC6
+#define SPI0_SCK_PC7
+#define SPI1_SS_PD4
+#define SPI1_MOSI_PD5
+#define SPI1_MISO_PD6
+#define SPI1_SCK_PD7
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x08C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x08C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x08C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x08C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x09C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x09C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x09C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x09C3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// NOTE: This family has 5 Timer/Counter modules, and the main diff is
+// three of them utilize 4 Output Compare (OC) channels (A, B, C and D),
+// unlike the other two module which utilize only two channels (A and B).
+
+// TCC0 (Timer/Counter0 on PORTC)
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+// TCD0 (Timer/Counter0 on PORTD)
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+// TCE0 (Timer/Counter0 on PORTE)
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+// TCC1 (Timer/Counter1 on PORTC)
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+// TCD1 (Timer/Counter1 on PORTD)
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_4 (4)
+#define TIM_MODULE_5 (5)
+#define TIM_MODULE_COUNT (5)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x0800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x0801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x0802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x0803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x0804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x0806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x0807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x0808)
+#define HAL_LL_TIM0_CTRLFSET_REG_ADDRESS (0x0809)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x080A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x080B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x080C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x080F)
+#define HAL_LL_TIM0_CNTL_REG_ADDRESS (0x0820)
+#define HAL_LL_TIM0_CNTH_REG_ADDRESS (0x0821)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x0826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x0827)
+#define HAL_LL_TIM0_CCAL_REG_ADDRESS (0x0828)
+#define HAL_LL_TIM0_CCAH_REG_ADDRESS (0x0829)
+#define HAL_LL_TIM0_CCBL_REG_ADDRESS (0x082A)
+#define HAL_LL_TIM0_CCBH_REG_ADDRESS (0x082B)
+#define HAL_LL_TIM0_CCCL_REG_ADDRESS (0x082C)
+#define HAL_LL_TIM0_CCCH_REG_ADDRESS (0x082D)
+#define HAL_LL_TIM0_CCDL_REG_ADDRESS (0x082E)
+#define HAL_LL_TIM0_CCDH_REG_ADDRESS (0x082F)
+#define HAL_LL_TIM0_PERBUFL_REG_ADDRESS (0x0836)
+#define HAL_LL_TIM0_PERBUFH_REG_ADDRESS (0x0837)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x0838)
+#define HAL_LL_TIM0_CCABUFL_REG_ADDRESS (0x0838)
+#define HAL_LL_TIM0_CCABUFH_REG_ADDRESS (0x0839)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x083A)
+#define HAL_LL_TIM0_CCBBUFL_REG_ADDRESS (0x083A)
+#define HAL_LL_TIM0_CCBBUFH_REG_ADDRESS (0x083B)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x083C)
+#define HAL_LL_TIM0_CCCBUFL_REG_ADDRESS (0x083C)
+#define HAL_LL_TIM0_CCCBUFH_REG_ADDRESS (0x083D)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x083E)
+#define HAL_LL_TIM0_CCDBUFL_REG_ADDRESS (0x083E)
+#define HAL_LL_TIM0_CCDBUFH_REG_ADDRESS (0x083F)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x0900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x0901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x0902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x0903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x0904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x0906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x0907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x0908)
+#define HAL_LL_TIM1_CTRLFSET_REG_ADDRESS (0x0909)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x090A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x090B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x090C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x090F)
+#define HAL_LL_TIM1_CNTL_REG_ADDRESS (0x0920)
+#define HAL_LL_TIM1_CNTH_REG_ADDRESS (0x0921)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x0926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x0927)
+#define HAL_LL_TIM1_CCAL_REG_ADDRESS (0x0928)
+#define HAL_LL_TIM1_CCAH_REG_ADDRESS (0x0929)
+#define HAL_LL_TIM1_CCBL_REG_ADDRESS (0x092A)
+#define HAL_LL_TIM1_CCBH_REG_ADDRESS (0x092B)
+#define HAL_LL_TIM1_CCCL_REG_ADDRESS (0x092C)
+#define HAL_LL_TIM1_CCCH_REG_ADDRESS (0x092D)
+#define HAL_LL_TIM1_CCDL_REG_ADDRESS (0x092E)
+#define HAL_LL_TIM1_CCDH_REG_ADDRESS (0x092F)
+#define HAL_LL_TIM1_PERBUFL_REG_ADDRESS (0x0936)
+#define HAL_LL_TIM1_PERBUFH_REG_ADDRESS (0x0937)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x0938)
+#define HAL_LL_TIM1_CCABUFL_REG_ADDRESS (0x0938)
+#define HAL_LL_TIM1_CCABUFH_REG_ADDRESS (0x0939)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x093A)
+#define HAL_LL_TIM1_CCBBUFL_REG_ADDRESS (0x093A)
+#define HAL_LL_TIM1_CCBBUFH_REG_ADDRESS (0x093B)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x093C)
+#define HAL_LL_TIM1_CCCBUFL_REG_ADDRESS (0x093C)
+#define HAL_LL_TIM1_CCCBUFH_REG_ADDRESS (0x093D)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x093E)
+#define HAL_LL_TIM1_CCDBUFL_REG_ADDRESS (0x093E)
+#define HAL_LL_TIM1_CCDBUFH_REG_ADDRESS (0x093F)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0x0A00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0x0A01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0x0A02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0x0A03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0x0A04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0x0A06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0x0A07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0x0A08)
+#define HAL_LL_TIM2_CTRLFSET_REG_ADDRESS (0x0A09)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0x0A0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0x0A0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0x0A0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0x0A0F)
+#define HAL_LL_TIM2_CNTL_REG_ADDRESS (0x0A20)
+#define HAL_LL_TIM2_CNTH_REG_ADDRESS (0x0A21)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0x0A26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0x0A27)
+#define HAL_LL_TIM2_CCAL_REG_ADDRESS (0x0A28)
+#define HAL_LL_TIM2_CCAH_REG_ADDRESS (0x0A29)
+#define HAL_LL_TIM2_CCBL_REG_ADDRESS (0x0A2A)
+#define HAL_LL_TIM2_CCBH_REG_ADDRESS (0x0A2B)
+#define HAL_LL_TIM2_CCCL_REG_ADDRESS (0x0A2C)
+#define HAL_LL_TIM2_CCCH_REG_ADDRESS (0x0A2D)
+#define HAL_LL_TIM2_CCDL_REG_ADDRESS (0x0A2E)
+#define HAL_LL_TIM2_CCDH_REG_ADDRESS (0x0A2F)
+#define HAL_LL_TIM2_PERBUFL_REG_ADDRESS (0x0A36)
+#define HAL_LL_TIM2_PERBUFH_REG_ADDRESS (0x0A37)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0x0A38)
+#define HAL_LL_TIM2_CCABUFL_REG_ADDRESS (0x0A38)
+#define HAL_LL_TIM2_CCABUFH_REG_ADDRESS (0x0A39)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0x0A3A)
+#define HAL_LL_TIM2_CCBBUFL_REG_ADDRESS (0x0A3A)
+#define HAL_LL_TIM2_CCBBUFH_REG_ADDRESS (0x0A3B)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0x0A3C)
+#define HAL_LL_TIM2_CCCBUFL_REG_ADDRESS (0x0A3C)
+#define HAL_LL_TIM2_CCCBUFH_REG_ADDRESS (0x0A3D)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0x0A3E)
+#define HAL_LL_TIM2_CCDBUFL_REG_ADDRESS (0x0A3E)
+#define HAL_LL_TIM2_CCDBUFH_REG_ADDRESS (0x0A3F)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x0840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x0841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x0842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x0843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x0844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x0846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x0847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x0848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x0849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x084A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x084B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x084C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x084F)
+#define HAL_LL_TIM4_CNTL_REG_ADDRESS (0x0840)
+#define HAL_LL_TIM4_CNTH_REG_ADDRESS (0x0841)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x0846)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x0847)
+#define HAL_LL_TIM4_CCAL_REG_ADDRESS (0x0848)
+#define HAL_LL_TIM4_CCAH_REG_ADDRESS (0x0849)
+#define HAL_LL_TIM4_CCBL_REG_ADDRESS (0x084A)
+#define HAL_LL_TIM4_CCBH_REG_ADDRESS (0x084B)
+#define HAL_LL_TIM4_PERBUFL_REG_ADDRESS (0x0866)
+#define HAL_LL_TIM4_PERBUFH_REG_ADDRESS (0x0867)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x0868)
+#define HAL_LL_TIM4_CCABUFL_REG_ADDRESS (0x0868)
+#define HAL_LL_TIM4_CCABUFH_REG_ADDRESS (0x0869)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x086A)
+#define HAL_LL_TIM4_CCBBUFL_REG_ADDRESS (0x086A)
+#define HAL_LL_TIM4_CCBBUFH_REG_ADDRESS (0x086B)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x0940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x0941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x0942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x0943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x0944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x0946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x0947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x0948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x0949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x094A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x094B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x094C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x094F)
+#define HAL_LL_TIM5_CNTL_REG_ADDRESS (0x0960)
+#define HAL_LL_TIM5_CNTH_REG_ADDRESS (0x0961)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x0966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x0967)
+#define HAL_LL_TIM5_CCAL_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCAH_REG_ADDRESS (0x0969)
+#define HAL_LL_TIM5_CCBL_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBH_REG_ADDRESS (0x096B)
+#define HAL_LL_TIM5_PERBUFL_REG_ADDRESS (0x0966)
+#define HAL_LL_TIM5_PERBUFH_REG_ADDRESS (0x0967)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCABUFL_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCABUFH_REG_ADDRESS (0x0969)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBBUFL_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBBUFH_REG_ADDRESS (0x096B)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (5)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA32A4U/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA32A4U/mcu_definitions.h
new file mode 100644
index 000000000..88558ebc8
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA32A4U/mcu_definitions.h
@@ -0,0 +1,529 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB3_CH11
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (12)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_RXD_PD6_ALT
+#define USARTD0_TXD_PD3
+#define USARTD0_TXD_PD7_ALT
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_COUNT (5)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_MOSI_PD7
+#define SPI1_SCK_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+#define TIM0_PC4_CH_A
+#define TIM0_PC5_CH_B
+#define TIM0_PC6_CH_C
+#define TIM0_PC7_CH_D
+#define TIM1_PC4_CH_A
+#define TIM1_PC5_CH_B
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM1_PD4_CH_A
+#define TIM1_PD5_CH_B
+#define TIM1_PD6_CH_C
+#define TIM1_PD7_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_5 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x94A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x94B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x94C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x94F)
+#define HAL_LL_TIM5_CNT_REG_ADDRESS (0x960)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x967)
+#define HAL_LL_TIM5_PER_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_CCA_REG_ADDRESS (0x968)
+#define HAL_LL_TIM5_CCB_REG_ADDRESS (0x96A)
+#define HAL_LL_TIM5_PERBUF_REG_ADDRESS (0x976)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x978)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x97A)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLFSET_REG_ADDRESS (0xA09)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_PER_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA32D3/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA32D3/mcu_definitions.h
new file mode 100644
index 000000000..459c73d5c
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA32D3/mcu_definitions.h
@@ -0,0 +1,498 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB3_CH11
+#define ADC0_PB4_CH12
+#define ADC0_PB5_CH13
+#define ADC0_PB6_CH14
+#define ADC0_PB7_CH15
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (16)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_D0 (2)
+#define UART_MODULE_1 (UART_MODULE_D0)
+#define UART_MODULE_E0 (3)
+#define UART_MODULE_2 (UART_MODULE_E0)
+#define UART_MODULE_COUNT (3)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+#define HAL_LL_SPI2_CTRL_REG_ADDRESS (0xAC0)
+#define HAL_LL_SPI2_INTCTRL_REG_ADDRESS (0xAC1)
+#define HAL_LL_SPI2_STATUS_REG_ADDRESS (0xAC2)
+#define HAL_LL_SPI2_DATA_REG_ADDRESS (0xAC3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+// TODO - Alternate pins to be implemented in a future release
+// #define TIM0_PC4_CH_A_ALT
+// #define TIM0_PC5_CH_B_ALT
+// #define TIM0_PC6_CH_C_ALT
+// #define TIM0_PC7_CH_D_ALT
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_4 (5)
+#define TIM_MODULE_COUNT (5)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0xB00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0xB01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0xB02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0xB03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0xB04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0xB06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0xB07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0xB08)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0xB0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0xB0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0xB0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0xB0F)
+#define HAL_LL_TIM3_PERBUF_REG_ADDRESS (0xB36)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0xB38)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0xB3A)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0xB3C)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0xB3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM3_CNT_REG_ADDRESS (0xB20)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0xB26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0xB27)
+#define HAL_LL_TIM3_CCA_REG_ADDRESS (0xB28)
+#define HAL_LL_TIM3_CCB_REG_ADDRESS (0xB2A)
+#define HAL_LL_TIM3_CCC_REG_ADDRESS (0xB2C)
+#define HAL_LL_TIM3_CCD_REG_ADDRESS (0xB2E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTF_REMAP_REG_ADDRESS (0x6AE)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA32D4/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA32D4/mcu_definitions.h
new file mode 100644
index 000000000..ed95a36b1
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA32D4/mcu_definitions.h
@@ -0,0 +1,448 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB3_CH11
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (12)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_D0 (2)
+#define UART_MODULE_1 (UART_MODULE_D0)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+// TODO - Alternate pins to be implemented in a future release
+// #define TIM0_PC4_CH_A_ALT
+// #define TIM0_PC5_CH_B_ALT
+// #define TIM0_PC6_CH_C_ALT
+// #define TIM0_PC7_CH_D_ALT
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_4 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLFSET_REG_ADDRESS (0x909)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_PER_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLFSET_REG_ADDRESS (0xA09)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_PER_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA32E5/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA32E5/mcu_definitions.h
new file mode 100644
index 000000000..7bde5b0ec
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA32E5/mcu_definitions.h
@@ -0,0 +1,344 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PD0_CH8
+#define ADC0_PD1_CH9
+#define ADC0_PD2_CH10
+#define ADC0_PD3_CH11
+#define ADC0_PD4_CH12
+#define ADC0_PD5_CH13
+#define ADC0_PD6_CH14
+#define ADC0_PD7_CH15
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (16)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SCL_PD1
+#define TWIC_SDA_PC0
+#define TWIC_SDA_PD0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIC_TIMEOUTTOS_REG_ADDRESS (0x48E)
+#define HAL_LL_TWIC_TIMEOUTTOCONF_REG_ADDRESS (0x48F)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8C0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8C1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8C2)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8C3)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8C4)
+#define HAL_LL_USARTC0_CTRLD_REG_ADDRESS (0x8C5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8C6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8C7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9C0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9C1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9C2)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9C3)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9C4)
+#define HAL_LL_USARTD0_CTRLD_REG_ADDRESS (0x9C5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9C6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9C7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SS_PC4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8E0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8E1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8E2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8E3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+#define TIM0_PC4_CH_A
+#define TIM0_PC5_CH_B
+#define TIM0_PC6_CH_C
+#define TIM0_PC7_CH_D
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_4 (2)
+#define TIM_MODULE_5 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_CTRLF_REG_ADDRESS (0x805)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x809)
+#define HAL_LL_TIM0_CTRLHCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLHSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_PER_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_CTRLF_REG_ADDRESS (0x845)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLHCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLHSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x944)
+#define HAL_LL_TIM5_CTRLF_REG_ADDRESS (0x945)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x947)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x948)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x949)
+#define HAL_LL_TIM5_CTRLHCLR_REG_ADDRESS (0x94A)
+#define HAL_LL_TIM5_CTRLHSET_REG_ADDRESS (0x94B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x94C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x94F)
+#define HAL_LL_TIM5_CNT_REG_ADDRESS (0x960)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x967)
+#define HAL_LL_TIM5_PER_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_CCA_REG_ADDRESS (0x968)
+#define HAL_LL_TIM5_CCB_REG_ADDRESS (0x96A)
+#define HAL_LL_TIM5_PERBUF_REG_ADDRESS (0x976)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x978)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x97A)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (4)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (23)
+#define HAL_LL_USARTC0_DRE_IVT (24)
+#define HAL_LL_USARTC0_TXC_IVT (26)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x2E)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x30)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x34)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA384D3/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA384D3/mcu_definitions.h
new file mode 100644
index 000000000..d4a504a51
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA384D3/mcu_definitions.h
@@ -0,0 +1,494 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB3_CH11
+#define ADC0_PB4_CH12
+#define ADC0_PB5_CH13
+#define ADC0_PB6_CH14
+#define ADC0_PB7_CH15
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (16)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_D0 (2)
+#define UART_MODULE_1 (UART_MODULE_D0)
+#define UART_MODULE_E0 (3)
+#define UART_MODULE_2 (UART_MODULE_E0)
+#define UART_MODULE_COUNT (3)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+// TODO - Alternate pins to be implemented in a future release
+// #define TIM0_PC4_CH_A_ALT
+// #define TIM0_PC5_CH_B_ALT
+// #define TIM0_PC6_CH_C_ALT
+// #define TIM0_PC7_CH_D_ALT
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_4 (5)
+#define TIM_MODULE_COUNT (5)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0xB00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0xB01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0xB02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0xB03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0xB04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0xB06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0xB07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0xB08)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0xB0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0xB0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0xB0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0xB0F)
+#define HAL_LL_TIM3_PERBUF_REG_ADDRESS (0xB36)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0xB38)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0xB3A)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0xB3C)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0xB3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM3_CNT_REG_ADDRESS (0xB20)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0xB26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0xB27)
+#define HAL_LL_TIM3_CCA_REG_ADDRESS (0xB28)
+#define HAL_LL_TIM3_CCB_REG_ADDRESS (0xB2A)
+#define HAL_LL_TIM3_CCC_REG_ADDRESS (0xB2C)
+#define HAL_LL_TIM3_CCD_REG_ADDRESS (0xB2E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTF_REMAP_REG_ADDRESS (0x6AE)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64A1U/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64A1U/mcu_definitions.h
new file mode 100644
index 000000000..6c995df11
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64A1U/mcu_definitions.h
@@ -0,0 +1,837 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH0
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH1
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB2_CH2
+#define ADC0_PB3_CH11
+#define ADC0_PB3_CH3
+#define ADC0_PB4_CH12
+#define ADC0_PB4_CH4
+#define ADC0_PB5_CH13
+#define ADC0_PB5_CH5
+#define ADC0_PB6_CH14
+#define ADC0_PB6_CH6
+#define ADC0_PB7_CH15
+#define ADC0_PB7_CH7
+#define ADC1_PA0_CH0
+#define ADC1_PB0_CH0
+#define ADC1_PB0_CH8
+#define ADC1_PB1_CH1
+#define ADC1_PB1_CH9
+#define ADC1_PB2_CH10
+#define ADC1_PB2_CH2
+#define ADC1_PB3_CH11
+#define ADC1_PB3_CH3
+#define ADC1_PB4_CH12
+#define ADC1_PB4_CH4
+#define ADC1_PB5_CH13
+#define ADC1_PB5_CH5
+#define ADC1_PB6_CH14
+#define ADC1_PB6_CH6
+#define ADC1_PB7_CH15
+#define ADC1_PB7_CH7
+
+#define ADC_MODULE_0 (1)
+#define ADC_MODULE_1 (2)
+
+#define HAL_LL_AN_COUNT (41)
+#define ADC_MODULE_COUNT (2)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+#define HAL_LL_ADC1_CTRLA_REG_ADDRESS (0x240)
+#define HAL_LL_ADC1_BASE_ADDRESS (HAL_LL_ADC1_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC1_CTRLB_REG_ADDRESS (0x241)
+#define HAL_LL_ADC1_REFCTRL_REG_ADDRESS (0x242)
+#define HAL_LL_ADC1_EVCTRL_REG_ADDRESS (0x243)
+#define HAL_LL_ADC1_PRESCALER_REG_ADDRESS (0x244)
+#define HAL_LL_ADC1_INTFLAGS_REG_ADDRESS (0x246)
+#define HAL_LL_ADC1_TEMP_REG_ADDRESS (0x247)
+#define HAL_LL_ADC1_CH0RESL_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0RESH_REG_ADDRESS (0x251)
+#define HAL_LL_ADC1_CH0RES_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH1RESL_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH1RESH_REG_ADDRESS (0x253)
+#define HAL_LL_ADC1_CH1RES_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH2RESL_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH2RESH_REG_ADDRESS (0x255)
+#define HAL_LL_ADC1_CH2RES_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH3RESL_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH3RESH_REG_ADDRESS (0x257)
+#define HAL_LL_ADC1_CH3RES_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH0CTRL_REG_ADDRESS (0x260)
+#define HAL_LL_ADC1_CH0MUXCTRL_REG_ADDRESS (0x261)
+#define HAL_LL_ADC1_CH0INTCTRL_REG_ADDRESS (0x262)
+#define HAL_LL_ADC1_CH0INTFLAGS_REG_ADDRESS (0x263)
+#define HAL_LL_ADC1_CH1CTRL_REG_ADDRESS (0x268)
+#define HAL_LL_ADC1_CH1MUXCTRL_REG_ADDRESS (0x269)
+#define HAL_LL_ADC1_CH1INTCTRL_REG_ADDRESS (0x26A)
+#define HAL_LL_ADC1_CH1INTFLAGS_REG_ADDRESS (0x26B)
+#define HAL_LL_ADC1_CH2CTRL_REG_ADDRESS (0x270)
+#define HAL_LL_ADC1_CH2MUXCTRL_REG_ADDRESS (0x271)
+#define HAL_LL_ADC1_CH2INTCTRL_REG_ADDRESS (0x272)
+#define HAL_LL_ADC1_CH2INTFLAGS_REG_ADDRESS (0x273)
+#define HAL_LL_ADC1_CH3CTRL_REG_ADDRESS (0x278)
+#define HAL_LL_ADC1_CH3MUXCTRL_REG_ADDRESS (0x279)
+#define HAL_LL_ADC1_CH3INTCTRL_REG_ADDRESS (0x27A)
+#define HAL_LL_ADC1_CH3INTFLAGS_REG_ADDRESS (0x27B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWID_SCL_PD1
+#define TWID_SDA_PD0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+#define TWIF_SCL_PF1
+#define TWIF_SDA_PF0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_D (2)
+#define I2C_MODULE_1 (TWI_MODULE_D)
+#define TWI_MODULE_E (3)
+#define I2C_MODULE_2 (TWI_MODULE_E)
+#define TWI_MODULE_F (4)
+#define I2C_MODULE_3 (TWI_MODULE_F)
+#define TWI_MODULE_COUNT (4)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWID_CTRL_REG_ADDRESS (0x490)
+#define HAL_LL_I2C1_BASE_ADDRESS (HAL_LL_TWID_CTRL_REG_ADDRESS)
+#define HAL_LL_TWID_MASTERCTRLA_REG_ADDRESS (0x491)
+#define HAL_LL_TWID_MASTERCTRLB_REG_ADDRESS (0x492)
+#define HAL_LL_TWID_MASTERCTRLC_REG_ADDRESS (0x493)
+#define HAL_LL_TWID_MASTERSTATUS_REG_ADDRESS (0x494)
+#define HAL_LL_TWID_MASTERBAUD_REG_ADDRESS (0x495)
+#define HAL_LL_TWID_MASTERADDR_REG_ADDRESS (0x496)
+#define HAL_LL_TWID_MASTERDATA_REG_ADDRESS (0x497)
+#define HAL_LL_TWID_SLAVECTRLA_REG_ADDRESS (0x498)
+#define HAL_LL_TWID_SLAVECTRLB_REG_ADDRESS (0x499)
+#define HAL_LL_TWID_SLAVESTATUS_REG_ADDRESS (0x49A)
+#define HAL_LL_TWID_SLAVEADDR_REG_ADDRESS (0x49B)
+#define HAL_LL_TWID_SLAVEDATA_REG_ADDRESS (0x49C)
+#define HAL_LL_TWID_SLAVEADDRMASK_REG_ADDRESS (0x49D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+#define HAL_LL_TWIF_CTRL_REG_ADDRESS (0x4B0)
+#define HAL_LL_I2C3_BASE_ADDRESS (HAL_LL_TWIF_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIF_MASTERCTRLA_REG_ADDRESS (0x4B1)
+#define HAL_LL_TWIF_MASTERCTRLB_REG_ADDRESS (0x4B2)
+#define HAL_LL_TWIF_MASTERCTRLC_REG_ADDRESS (0x4B3)
+#define HAL_LL_TWIF_MASTERSTATUS_REG_ADDRESS (0x4B4)
+#define HAL_LL_TWIF_MASTERBAUD_REG_ADDRESS (0x4B5)
+#define HAL_LL_TWIF_MASTERADDR_REG_ADDRESS (0x4B6)
+#define HAL_LL_TWIF_MASTERDATA_REG_ADDRESS (0x4B7)
+#define HAL_LL_TWIF_SLAVECTRLA_REG_ADDRESS (0x4B8)
+#define HAL_LL_TWIF_SLAVECTRLB_REG_ADDRESS (0x4B9)
+#define HAL_LL_TWIF_SLAVESTATUS_REG_ADDRESS (0x4BA)
+#define HAL_LL_TWIF_SLAVEADDR_REG_ADDRESS (0x4BB)
+#define HAL_LL_TWIF_SLAVEDATA_REG_ADDRESS (0x4BC)
+#define HAL_LL_TWIF_SLAVEADDRMASK_REG_ADDRESS (0x4BD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+#define USARTE1_RXD_PE6
+#define USARTE1_TXD_PE7
+#define USARTF0_RXD_PF2
+#define USARTF0_TXD_PF3
+#define USARTF1_RXD_PF6
+#define USARTF1_TXD_PF7
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_E1 (6)
+#define UART_MODULE_5 (UART_MODULE_E1)
+#define UART_MODULE_F0 (7)
+#define UART_MODULE_6 (UART_MODULE_F0)
+#define UART_MODULE_F1 (8)
+#define UART_MODULE_7 (UART_MODULE_F1)
+#define UART_MODULE_COUNT (8)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+#define HAL_LL_USARTE1_DATA_REG_ADDRESS (0xAB0)
+#define HAL_LL_USARTE1_STATUS_REG_ADDRESS (0xAB1)
+#define HAL_LL_USARTE1_CTRLA_REG_ADDRESS (0xAB3)
+#define HAL_LL_USARTE1_CTRLB_REG_ADDRESS (0xAB4)
+#define HAL_LL_USARTE1_CTRLC_REG_ADDRESS (0xAB5)
+#define HAL_LL_USARTE1_BAUDCTRLA_REG_ADDRESS (0xAB6)
+#define HAL_LL_USARTE1_BAUDCTRLB_REG_ADDRESS (0xAB7)
+#define HAL_LL_USARTF0_DATA_REG_ADDRESS (0xBA0)
+#define HAL_LL_USARTF0_STATUS_REG_ADDRESS (0xBA1)
+#define HAL_LL_USARTF0_CTRLA_REG_ADDRESS (0xBA3)
+#define HAL_LL_USARTF0_CTRLB_REG_ADDRESS (0xBA4)
+#define HAL_LL_USARTF0_CTRLC_REG_ADDRESS (0xBA5)
+#define HAL_LL_USARTF0_BAUDCTRLA_REG_ADDRESS (0xBA6)
+#define HAL_LL_USARTF0_BAUDCTRLB_REG_ADDRESS (0xBA7)
+#define HAL_LL_USARTF1_DATA_REG_ADDRESS (0xBB0)
+#define HAL_LL_USARTF1_STATUS_REG_ADDRESS (0xBB1)
+#define HAL_LL_USARTF1_CTRLA_REG_ADDRESS (0xBB3)
+#define HAL_LL_USARTF1_CTRLB_REG_ADDRESS (0xBB4)
+#define HAL_LL_USARTF1_CTRLC_REG_ADDRESS (0xBB5)
+#define HAL_LL_USARTF1_BAUDCTRLA_REG_ADDRESS (0xBB6)
+#define HAL_LL_USARTF1_BAUDCTRLB_REG_ADDRESS (0xBB7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+#define SPI2_MISO_PE6
+#define SPI2_MOSI_PE5
+#define SPI2_SCK_PE7
+#define SPI2_SS_PE4
+#define SPI3_MISO_PF6
+#define SPI3_MOSI_PF5
+#define SPI3_SCK_PF7
+#define SPI3_SS_PF4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_2 (3)
+#define SPI_MODULE_3 (4)
+#define SPI_MODULE_COUNT (4)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+#define HAL_LL_SPI2_CTRL_REG_ADDRESS (0xAC0)
+#define HAL_LL_SPI2_INTCTRL_REG_ADDRESS (0xAC1)
+#define HAL_LL_SPI2_STATUS_REG_ADDRESS (0xAC2)
+#define HAL_LL_SPI2_DATA_REG_ADDRESS (0xAC3)
+#define HAL_LL_SPI3_CTRL_REG_ADDRESS (0xBC0)
+#define HAL_LL_SPI3_INTCTRL_REG_ADDRESS (0xBC1)
+#define HAL_LL_SPI3_STATUS_REG_ADDRESS (0xBC2)
+#define HAL_LL_SPI3_DATA_REG_ADDRESS (0xBC3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+#define TIM0_PC4_CH_A
+#define TIM0_PC5_CH_B
+#define TIM0_PC6_CH_C
+#define TIM0_PC7_CH_D
+#define TIM1_PC4_CH_A
+#define TIM1_PC5_CH_B
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+#define TIM6_PE4_CH_A
+#define TIM6_PE5_CH_B
+#define TIM7_PF4_CH_A
+#define TIM7_PF5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_5 (5)
+#define TIM_MODULE_6 (6)
+#define TIM_MODULE_7 (7)
+#define TIM_MODULE_COUNT (7)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x94A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x94B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x94C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x94F)
+#define HAL_LL_TIM5_CNT_REG_ADDRESS (0x960)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x967)
+#define HAL_LL_TIM5_PER_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_CCA_REG_ADDRESS (0x968)
+#define HAL_LL_TIM5_CCB_REG_ADDRESS (0x96A)
+#define HAL_LL_TIM5_PERBUF_REG_ADDRESS (0x976)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x978)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x97A)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM6_CTRLA_REG_ADDRESS (0xA40)
+#define HAL_LL_TIM6_CTRLB_REG_ADDRESS (0xA41)
+#define HAL_LL_TIM6_CTRLC_REG_ADDRESS (0xA42)
+#define HAL_LL_TIM6_CTRLD_REG_ADDRESS (0xA43)
+#define HAL_LL_TIM6_CTRLE_REG_ADDRESS (0xA44)
+#define HAL_LL_TIM6_INTCTRLA_REG_ADDRESS (0xA46)
+#define HAL_LL_TIM6_INTCTRLB_REG_ADDRESS (0xA47)
+#define HAL_LL_TIM6_CTRLFCLR_REG_ADDRESS (0xA48)
+#define HAL_LL_TIM6_CTRLFSET_REG_ADDRESS (0xA49)
+#define HAL_LL_TIM6_CTRLGCLR_REG_ADDRESS (0xA4A)
+#define HAL_LL_TIM6_CTRLGSET_REG_ADDRESS (0xA4B)
+#define HAL_LL_TIM6_INTFLAGS_REG_ADDRESS (0xA4C)
+#define HAL_LL_TIM6_TEMP_REG_ADDRESS (0xA4F)
+#define HAL_LL_TIM6_CNT_REG_ADDRESS (0xA60)
+#define HAL_LL_TIM6_PERL_REG_ADDRESS (0xA66)
+#define HAL_LL_TIM6_PERH_REG_ADDRESS (0xA67)
+#define HAL_LL_TIM6_PER_REG_ADDRESS (0xA66)
+#define HAL_LL_TIM6_CCA_REG_ADDRESS (0xA68)
+#define HAL_LL_TIM6_CCB_REG_ADDRESS (0xA6A)
+#define HAL_LL_TIM6_PERBUF_REG_ADDRESS (0xA76)
+#define HAL_LL_TIM6_CCABUF_REG_ADDRESS (0xA78)
+#define HAL_LL_TIM6_CCBBUF_REG_ADDRESS (0xA7A)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0xB00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0xB01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0xB02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0xB03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0xB04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0xB06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0xB07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0xB08)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0xB0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0xB0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0xB0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0xB0F)
+#define HAL_LL_TIM3_PERBUF_REG_ADDRESS (0xB36)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0xB38)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0xB3A)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0xB3C)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0xB3E)
+#define HAL_LL_TIM7_CTRLA_REG_ADDRESS (0xB40)
+#define HAL_LL_TIM7_CTRLB_REG_ADDRESS (0xB41)
+#define HAL_LL_TIM7_CTRLC_REG_ADDRESS (0xB42)
+#define HAL_LL_TIM7_CTRLD_REG_ADDRESS (0xB43)
+#define HAL_LL_TIM7_CTRLE_REG_ADDRESS (0xB44)
+#define HAL_LL_TIM7_INTCTRLA_REG_ADDRESS (0xB46)
+#define HAL_LL_TIM7_INTCTRLB_REG_ADDRESS (0xB47)
+#define HAL_LL_TIM7_CTRLFCLR_REG_ADDRESS (0xB48)
+#define HAL_LL_TIM7_CTRLFSET_REG_ADDRESS (0xB49)
+#define HAL_LL_TIM7_CTRLGCLR_REG_ADDRESS (0xB4A)
+#define HAL_LL_TIM7_CTRLGSET_REG_ADDRESS (0xB4B)
+#define HAL_LL_TIM7_INTFLAGS_REG_ADDRESS (0xB4C)
+#define HAL_LL_TIM7_TEMP_REG_ADDRESS (0xB4F)
+#define HAL_LL_TIM7_CNT_REG_ADDRESS (0xB60)
+#define HAL_LL_TIM7_PERL_REG_ADDRESS (0xB66)
+#define HAL_LL_TIM7_PERH_REG_ADDRESS (0xB67)
+#define HAL_LL_TIM7_PER_REG_ADDRESS (0xB66)
+#define HAL_LL_TIM7_CCA_REG_ADDRESS (0xB68)
+#define HAL_LL_TIM7_CCB_REG_ADDRESS (0xB6A)
+#define HAL_LL_TIM7_PERBUF_REG_ADDRESS (0xB76)
+#define HAL_LL_TIM7_CCABUF_REG_ADDRESS (0xB78)
+#define HAL_LL_TIM7_CCBBUF_REG_ADDRESS (0xB7A)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM3_CNT_REG_ADDRESS (0xB20)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0xB26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0xB27)
+#define HAL_LL_TIM3_CCA_REG_ADDRESS (0xB28)
+#define HAL_LL_TIM3_CCB_REG_ADDRESS (0xB2A)
+#define HAL_LL_TIM3_CCC_REG_ADDRESS (0xB2C)
+#define HAL_LL_TIM3_CCD_REG_ADDRESS (0xB2E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PH0_CN
+#define __PH1_CN
+#define __PH2_CN
+#define __PH3_CN
+#define __PH4_CN
+#define __PH5_CN
+#define __PH6_CN
+#define __PH7_CN
+#define __PJ0_CN
+#define __PJ1_CN
+#define __PJ2_CN
+#define __PJ3_CN
+#define __PJ4_CN
+#define __PJ5_CN
+#define __PJ6_CN
+#define __PJ7_CN
+#define __PK0_CN
+#define __PK1_CN
+#define __PK2_CN
+#define __PK3_CN
+#define __PK4_CN
+#define __PK5_CN
+#define __PK6_CN
+#define __PK7_CN
+#define __PQ0_CN
+#define __PQ1_CN
+#define __PQ2_CN
+#define __PQ3_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_H_CN
+#define __PORT_J_CN
+#define __PORT_K_CN
+#define __PORT_Q_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (11)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRH_REG_ADDRESS (0x6E0)
+#define PORTH_REG_ADDRESS (0x6E4)
+#define PINH_REG_ADDRESS (0x6E8)
+#define DDRJ_REG_ADDRESS (0x700)
+#define PORTJ_REG_ADDRESS (0x704)
+#define PINJ_REG_ADDRESS (0x708)
+#define DDRK_REG_ADDRESS (0x720)
+#define PORTK_REG_ADDRESS (0x724)
+#define PINK_REG_ADDRESS (0x728)
+#define DDRQ_REG_ADDRESS (0x7C0)
+#define PORTQ_REG_ADDRESS (0x7C4)
+#define PINQ_REG_ADDRESS (0x7C8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTF_REMAP_REG_ADDRESS (0x6AE)
+#define PORTH_REMAP_REG_ADDRESS (0x6EE)
+#define PORTJ_REMAP_REG_ADDRESS (0x70E)
+#define PORTK_REMAP_REG_ADDRESS (0x72E)
+#define PORTQ_REMAP_REG_ADDRESS (0x7CE)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTE1_RXC_IVT (61)
+#define HAL_LL_USARTE1_DRE_IVT (62)
+#define HAL_LL_USARTE1_TXC_IVT (63)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+#define HAL_LL_USARTF0_RXC_IVT (119)
+#define HAL_LL_USARTF0_DRE_IVT (120)
+#define HAL_LL_USARTF0_TXC_IVT (121)
+#define HAL_LL_USARTF1_RXC_IVT (122)
+#define HAL_LL_USARTF1_DRE_IVT (123)
+#define HAL_LL_USARTF1_TXC_IVT (124)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTE1_RXC_IVT_ADDRESS (0x7A)
+#define HAL_LL_USARTE1_DRE_IVT_ADDRESS (0x7C)
+#define HAL_LL_USARTE1_TXC_IVT_ADDRESS (0x7E)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+#define HAL_LL_USARTF0_RXC_IVT_ADDRESS (0xEE)
+#define HAL_LL_USARTF0_DRE_IVT_ADDRESS (0xF0)
+#define HAL_LL_USARTF0_TXC_IVT_ADDRESS (0xF2)
+#define HAL_LL_USARTF1_RXC_IVT_ADDRESS (0xF4)
+#define HAL_LL_USARTF1_DRE_IVT_ADDRESS (0xF6)
+#define HAL_LL_USARTF1_TXC_IVT_ADDRESS (0xF8)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64A3/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64A3/mcu_definitions.h
new file mode 100644
index 000000000..4183b74d5
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64A3/mcu_definitions.h
@@ -0,0 +1,752 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC1_PB0_CH0
+#define ADC1_PB1_CH1
+#define ADC1_PB2_CH2
+#define ADC1_PB3_CH3
+#define ADC1_PB4_CH4
+#define ADC1_PB5_CH5
+#define ADC1_PB6_CH6
+#define ADC1_PB7_CH7
+
+#define ADC_MODULE_0 (1)
+#define ADC_MODULE_1 (2)
+
+#define HAL_LL_AN_COUNT (16)
+#define ADC_MODULE_COUNT (2)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+#define HAL_LL_ADC1_CTRLA_REG_ADDRESS (0x240)
+#define HAL_LL_ADC1_BASE_ADDRESS (HAL_LL_ADC1_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC1_CTRLB_REG_ADDRESS (0x241)
+#define HAL_LL_ADC1_REFCTRL_REG_ADDRESS (0x242)
+#define HAL_LL_ADC1_EVCTRL_REG_ADDRESS (0x243)
+#define HAL_LL_ADC1_PRESCALER_REG_ADDRESS (0x244)
+#define HAL_LL_ADC1_INTFLAGS_REG_ADDRESS (0x246)
+#define HAL_LL_ADC1_TEMP_REG_ADDRESS (0x247)
+#define HAL_LL_ADC1_CH0RESL_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0RESH_REG_ADDRESS (0x251)
+#define HAL_LL_ADC1_CH0RES_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH1RESL_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH1RESH_REG_ADDRESS (0x253)
+#define HAL_LL_ADC1_CH1RES_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH2RESL_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH2RESH_REG_ADDRESS (0x255)
+#define HAL_LL_ADC1_CH2RES_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH3RESL_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH3RESH_REG_ADDRESS (0x257)
+#define HAL_LL_ADC1_CH3RES_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH0CTRL_REG_ADDRESS (0x260)
+#define HAL_LL_ADC1_CH0MUXCTRL_REG_ADDRESS (0x261)
+#define HAL_LL_ADC1_CH0INTCTRL_REG_ADDRESS (0x262)
+#define HAL_LL_ADC1_CH0INTFLAGS_REG_ADDRESS (0x263)
+#define HAL_LL_ADC1_CH1CTRL_REG_ADDRESS (0x268)
+#define HAL_LL_ADC1_CH1MUXCTRL_REG_ADDRESS (0x269)
+#define HAL_LL_ADC1_CH1INTCTRL_REG_ADDRESS (0x26A)
+#define HAL_LL_ADC1_CH1INTFLAGS_REG_ADDRESS (0x26B)
+#define HAL_LL_ADC1_CH2CTRL_REG_ADDRESS (0x270)
+#define HAL_LL_ADC1_CH2MUXCTRL_REG_ADDRESS (0x271)
+#define HAL_LL_ADC1_CH2INTCTRL_REG_ADDRESS (0x272)
+#define HAL_LL_ADC1_CH2INTFLAGS_REG_ADDRESS (0x273)
+#define HAL_LL_ADC1_CH3CTRL_REG_ADDRESS (0x278)
+#define HAL_LL_ADC1_CH3MUXCTRL_REG_ADDRESS (0x279)
+#define HAL_LL_ADC1_CH3INTCTRL_REG_ADDRESS (0x27A)
+#define HAL_LL_ADC1_CH3INTFLAGS_REG_ADDRESS (0x27B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_TXD_PC3
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+#define USARTE1_RXD_PE6
+#define USARTE1_TXD_PE7
+#define USARTF0_RXD_PF2
+#define USARTF0_TXD_PF3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_E1 (6)
+#define UART_MODULE_5 (UART_MODULE_E1)
+#define UART_MODULE_F0 (7)
+#define UART_MODULE_6 (UART_MODULE_F0)
+#define UART_MODULE_COUNT (7)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+#define HAL_LL_USARTE1_DATA_REG_ADDRESS (0xAB0)
+#define HAL_LL_USARTE1_STATUS_REG_ADDRESS (0xAB1)
+#define HAL_LL_USARTE1_CTRLA_REG_ADDRESS (0xAB3)
+#define HAL_LL_USARTE1_CTRLB_REG_ADDRESS (0xAB4)
+#define HAL_LL_USARTE1_CTRLC_REG_ADDRESS (0xAB5)
+#define HAL_LL_USARTE1_BAUDCTRLA_REG_ADDRESS (0xAB6)
+#define HAL_LL_USARTE1_BAUDCTRLB_REG_ADDRESS (0xAB7)
+#define HAL_LL_USARTF0_DATA_REG_ADDRESS (0xBA0)
+#define HAL_LL_USARTF0_STATUS_REG_ADDRESS (0xBA1)
+#define HAL_LL_USARTF0_CTRLA_REG_ADDRESS (0xBA3)
+#define HAL_LL_USARTF0_CTRLB_REG_ADDRESS (0xBA4)
+#define HAL_LL_USARTF0_CTRLC_REG_ADDRESS (0xBA5)
+#define HAL_LL_USARTF0_BAUDCTRLA_REG_ADDRESS (0xBA6)
+#define HAL_LL_USARTF0_BAUDCTRLB_REG_ADDRESS (0xBA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_SS_PC4
+#define SPI0_MOSI_PC5
+#define SPI0_MISO_PC6
+#define SPI0_SCK_PC7
+#define SPI1_SS_PD4
+#define SPI1_MOSI_PD5
+#define SPI1_MISO_PD6
+#define SPI1_SCK_PD7
+#define SPI2_SS_PE4
+#define SPI2_MOSI_PE5
+#define SPI2_MISO_PE6
+#define SPI2_SCK_PE7
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_2 (3)
+#define SPI_MODULE_COUNT (3)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x08C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x08C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x08C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x08C3)
+
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x09C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x09C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x09C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x09C3)
+
+#define HAL_LL_SPI2_CTRL_REG_ADDRESS (0x0AC0)
+#define HAL_LL_SPI2_INTCTRL_REG_ADDRESS (0x0AC1)
+#define HAL_LL_SPI2_STATUS_REG_ADDRESS (0x0AC2)
+#define HAL_LL_SPI2_DATA_REG_ADDRESS (0x0AC3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+// TCC0 (Timer/Counter0 on PORTC)
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+// TCD0 (Timer/Counter0 on PORTD)
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+// TCE0 (Timer/Counter0 on PORTE)
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+// TCF0 (Timer/Counter0 on PORTF)
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+// TCC1 (Timer/Counter1 on PORTC)
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+// TCD1 (Timer/Counter1 on PORTD)
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+// TCE1 (Timer/Counter1 on PORTE)
+#define TIM6_PE4_CH_A
+#define TIM6_PE5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_4 (5)
+#define TIM_MODULE_5 (6)
+#define TIM_MODULE_6 (7)
+
+#define TIM_MODULE_COUNT (7)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x0800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x0801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x0802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x0803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x0804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x0806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x0807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x0808)
+#define HAL_LL_TIM0_CTRLFSET_REG_ADDRESS (0x0809)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x080A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x080B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x080C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x080F)
+#define HAL_LL_TIM0_CNTL_REG_ADDRESS (0x0820)
+#define HAL_LL_TIM0_CNTH_REG_ADDRESS (0x0821)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x0826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x0827)
+#define HAL_LL_TIM0_CCAL_REG_ADDRESS (0x0828)
+#define HAL_LL_TIM0_CCAH_REG_ADDRESS (0x0829)
+#define HAL_LL_TIM0_CCBL_REG_ADDRESS (0x082A)
+#define HAL_LL_TIM0_CCBH_REG_ADDRESS (0x082B)
+#define HAL_LL_TIM0_CCCL_REG_ADDRESS (0x082C)
+#define HAL_LL_TIM0_CCCH_REG_ADDRESS (0x082D)
+#define HAL_LL_TIM0_CCDL_REG_ADDRESS (0x082E)
+#define HAL_LL_TIM0_CCDH_REG_ADDRESS (0x082F)
+#define HAL_LL_TIM0_PERBUFL_REG_ADDRESS (0x0836)
+#define HAL_LL_TIM0_PERBUFH_REG_ADDRESS (0x0837)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x0838)
+#define HAL_LL_TIM0_CCABUFL_REG_ADDRESS (0x0838)
+#define HAL_LL_TIM0_CCABUFH_REG_ADDRESS (0x0839)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x083A)
+#define HAL_LL_TIM0_CCBBUFL_REG_ADDRESS (0x083A)
+#define HAL_LL_TIM0_CCBBUFH_REG_ADDRESS (0x083B)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x083C)
+#define HAL_LL_TIM0_CCCBUFL_REG_ADDRESS (0x083C)
+#define HAL_LL_TIM0_CCCBUFH_REG_ADDRESS (0x083D)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x083E)
+#define HAL_LL_TIM0_CCDBUFL_REG_ADDRESS (0x083E)
+#define HAL_LL_TIM0_CCDBUFH_REG_ADDRESS (0x083F)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x0900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x0901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x0902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x0903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x0904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x0906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x0907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x0908)
+#define HAL_LL_TIM1_CTRLFSET_REG_ADDRESS (0x0909)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x090A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x090B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x090C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x090F)
+#define HAL_LL_TIM1_CNTL_REG_ADDRESS (0x0920)
+#define HAL_LL_TIM1_CNTH_REG_ADDRESS (0x0921)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x0926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x0927)
+#define HAL_LL_TIM1_CCAL_REG_ADDRESS (0x0928)
+#define HAL_LL_TIM1_CCAH_REG_ADDRESS (0x0929)
+#define HAL_LL_TIM1_CCBL_REG_ADDRESS (0x092A)
+#define HAL_LL_TIM1_CCBH_REG_ADDRESS (0x092B)
+#define HAL_LL_TIM1_CCCL_REG_ADDRESS (0x092C)
+#define HAL_LL_TIM1_CCCH_REG_ADDRESS (0x092D)
+#define HAL_LL_TIM1_CCDL_REG_ADDRESS (0x092E)
+#define HAL_LL_TIM1_CCDH_REG_ADDRESS (0x092F)
+#define HAL_LL_TIM1_PERBUFL_REG_ADDRESS (0x0936)
+#define HAL_LL_TIM1_PERBUFH_REG_ADDRESS (0x0937)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x0938)
+#define HAL_LL_TIM1_CCABUFL_REG_ADDRESS (0x0938)
+#define HAL_LL_TIM1_CCABUFH_REG_ADDRESS (0x0939)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x093A)
+#define HAL_LL_TIM1_CCBBUFL_REG_ADDRESS (0x093A)
+#define HAL_LL_TIM1_CCBBUFH_REG_ADDRESS (0x093B)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x093C)
+#define HAL_LL_TIM1_CCCBUFL_REG_ADDRESS (0x093C)
+#define HAL_LL_TIM1_CCCBUFH_REG_ADDRESS (0x093D)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x093E)
+#define HAL_LL_TIM1_CCDBUFL_REG_ADDRESS (0x093E)
+#define HAL_LL_TIM1_CCDBUFH_REG_ADDRESS (0x093F)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0x0A00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0x0A01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0x0A02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0x0A03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0x0A04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0x0A06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0x0A07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0x0A08)
+#define HAL_LL_TIM2_CTRLFSET_REG_ADDRESS (0x0A09)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0x0A0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0x0A0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0x0A0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0x0A0F)
+#define HAL_LL_TIM2_CNTL_REG_ADDRESS (0x0A20)
+#define HAL_LL_TIM2_CNTH_REG_ADDRESS (0x0A21)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0x0A26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0x0A27)
+#define HAL_LL_TIM2_CCAL_REG_ADDRESS (0x0A28)
+#define HAL_LL_TIM2_CCAH_REG_ADDRESS (0x0A29)
+#define HAL_LL_TIM2_CCBL_REG_ADDRESS (0x0A2A)
+#define HAL_LL_TIM2_CCBH_REG_ADDRESS (0x0A2B)
+#define HAL_LL_TIM2_CCCL_REG_ADDRESS (0x0A2C)
+#define HAL_LL_TIM2_CCCH_REG_ADDRESS (0x0A2D)
+#define HAL_LL_TIM2_CCDL_REG_ADDRESS (0x0A2E)
+#define HAL_LL_TIM2_CCDH_REG_ADDRESS (0x0A2F)
+#define HAL_LL_TIM2_PERBUFL_REG_ADDRESS (0x0A36)
+#define HAL_LL_TIM2_PERBUFH_REG_ADDRESS (0x0A37)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0x0A38)
+#define HAL_LL_TIM2_CCABUFL_REG_ADDRESS (0x0A38)
+#define HAL_LL_TIM2_CCABUFH_REG_ADDRESS (0x0A39)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0x0A3A)
+#define HAL_LL_TIM2_CCBBUFL_REG_ADDRESS (0x0A3A)
+#define HAL_LL_TIM2_CCBBUFH_REG_ADDRESS (0x0A3B)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0x0A3C)
+#define HAL_LL_TIM2_CCCBUFL_REG_ADDRESS (0x0A3C)
+#define HAL_LL_TIM2_CCCBUFH_REG_ADDRESS (0x0A3D)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0x0A3E)
+#define HAL_LL_TIM2_CCDBUFL_REG_ADDRESS (0x0A3E)
+#define HAL_LL_TIM2_CCDBUFH_REG_ADDRESS (0x0A3F)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0x0B00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0x0B01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0x0B02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0x0B03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0x0B04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0x0B06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0x0B07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0x0B08)
+#define HAL_LL_TIM3_CTRLFSET_REG_ADDRESS (0x0B09)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0x0B0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0x0B0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0x0B0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0x0B0F)
+#define HAL_LL_TIM3_CNTL_REG_ADDRESS (0x0B20)
+#define HAL_LL_TIM3_CNTH_REG_ADDRESS (0x0B21)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0x0B26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0x0B27)
+#define HAL_LL_TIM3_CCAL_REG_ADDRESS (0x0B28)
+#define HAL_LL_TIM3_CCAH_REG_ADDRESS (0x0B29)
+#define HAL_LL_TIM3_CCBL_REG_ADDRESS (0x0B2A)
+#define HAL_LL_TIM3_CCBH_REG_ADDRESS (0x0B2B)
+#define HAL_LL_TIM3_CCCL_REG_ADDRESS (0x0B2C)
+#define HAL_LL_TIM3_CCCH_REG_ADDRESS (0x0B2D)
+#define HAL_LL_TIM3_CCDL_REG_ADDRESS (0x0B2E)
+#define HAL_LL_TIM3_CCDH_REG_ADDRESS (0x0B2F)
+#define HAL_LL_TIM3_PERBUFL_REG_ADDRESS (0x0B36)
+#define HAL_LL_TIM3_PERBUFH_REG_ADDRESS (0x0B37)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0x0B38)
+#define HAL_LL_TIM3_CCABUFL_REG_ADDRESS (0x0B38)
+#define HAL_LL_TIM3_CCABUFH_REG_ADDRESS (0x0B39)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0x0B3A)
+#define HAL_LL_TIM3_CCBBUFL_REG_ADDRESS (0x0B3A)
+#define HAL_LL_TIM3_CCBBUFH_REG_ADDRESS (0x0B3B)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0x0B3C)
+#define HAL_LL_TIM3_CCCBUFL_REG_ADDRESS (0x0B3C)
+#define HAL_LL_TIM3_CCCBUFH_REG_ADDRESS (0x0B3D)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0x0B3E)
+#define HAL_LL_TIM3_CCDBUFL_REG_ADDRESS (0x0B3E)
+#define HAL_LL_TIM3_CCDBUFH_REG_ADDRESS (0x0B3F)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x0840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x0841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x0842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x0843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x0844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x0846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x0847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x0848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x0849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x084A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x084B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x084C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x084F)
+#define HAL_LL_TIM4_CNTL_REG_ADDRESS (0x0840)
+#define HAL_LL_TIM4_CNTH_REG_ADDRESS (0x0841)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x0846)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x0847)
+#define HAL_LL_TIM4_CCAL_REG_ADDRESS (0x0848)
+#define HAL_LL_TIM4_CCAH_REG_ADDRESS (0x0849)
+#define HAL_LL_TIM4_CCBL_REG_ADDRESS (0x084A)
+#define HAL_LL_TIM4_CCBH_REG_ADDRESS (0x084B)
+#define HAL_LL_TIM4_PERBUFL_REG_ADDRESS (0x0866)
+#define HAL_LL_TIM4_PERBUFH_REG_ADDRESS (0x0867)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x0868)
+#define HAL_LL_TIM4_CCABUFL_REG_ADDRESS (0x0868)
+#define HAL_LL_TIM4_CCABUFH_REG_ADDRESS (0x0869)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x086A)
+#define HAL_LL_TIM4_CCBBUFL_REG_ADDRESS (0x086A)
+#define HAL_LL_TIM4_CCBBUFH_REG_ADDRESS (0x086B)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x0940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x0941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x0942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x0943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x0944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x0946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x0947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x0948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x0949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x094A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x094B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x094C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x094F)
+#define HAL_LL_TIM5_CNTL_REG_ADDRESS (0x0960)
+#define HAL_LL_TIM5_CNTH_REG_ADDRESS (0x0961)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x0966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x0967)
+#define HAL_LL_TIM5_CCAL_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCAH_REG_ADDRESS (0x0969)
+#define HAL_LL_TIM5_CCBL_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBH_REG_ADDRESS (0x096B)
+#define HAL_LL_TIM5_PERBUFL_REG_ADDRESS (0x0966)
+#define HAL_LL_TIM5_PERBUFH_REG_ADDRESS (0x0967)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCABUFL_REG_ADDRESS (0x0968)
+#define HAL_LL_TIM5_CCABUFH_REG_ADDRESS (0x0969)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBBUFL_REG_ADDRESS (0x096A)
+#define HAL_LL_TIM5_CCBBUFH_REG_ADDRESS (0x096B)
+#define HAL_LL_TIM6_CTRLA_REG_ADDRESS (0x0A40)
+#define HAL_LL_TIM6_CTRLB_REG_ADDRESS (0x0A41)
+#define HAL_LL_TIM6_CTRLC_REG_ADDRESS (0x0A42)
+#define HAL_LL_TIM6_CTRLD_REG_ADDRESS (0x0A43)
+#define HAL_LL_TIM6_CTRLE_REG_ADDRESS (0x0A44)
+#define HAL_LL_TIM6_INTCTRLA_REG_ADDRESS (0x0A46)
+#define HAL_LL_TIM6_INTCTRLB_REG_ADDRESS (0x0A47)
+#define HAL_LL_TIM6_CTRLFCLR_REG_ADDRESS (0x0A48)
+#define HAL_LL_TIM6_CTRLFSET_REG_ADDRESS (0x0A49)
+#define HAL_LL_TIM6_CTRLGCLR_REG_ADDRESS (0x0A4A)
+#define HAL_LL_TIM6_CTRLGSET_REG_ADDRESS (0x0A4B)
+#define HAL_LL_TIM6_INTFLAGS_REG_ADDRESS (0x0A4C)
+#define HAL_LL_TIM6_TEMP_REG_ADDRESS (0x0A4F)
+#define HAL_LL_TIM6_CNTL_REG_ADDRESS (0x0A60)
+#define HAL_LL_TIM6_CNTH_REG_ADDRESS (0x0A61)
+#define HAL_LL_TIM6_PERL_REG_ADDRESS (0x0A66)
+#define HAL_LL_TIM6_PERH_REG_ADDRESS (0x0A67)
+#define HAL_LL_TIM6_CCAL_REG_ADDRESS (0x0A68)
+#define HAL_LL_TIM6_CCAH_REG_ADDRESS (0x0A69)
+#define HAL_LL_TIM6_CCBL_REG_ADDRESS (0x0A6A)
+#define HAL_LL_TIM6_CCBH_REG_ADDRESS (0x0A6B)
+#define HAL_LL_TIM6_PERBUFL_REG_ADDRESS (0x0A66)
+#define HAL_LL_TIM6_PERBUFH_REG_ADDRESS (0x0A67)
+#define HAL_LL_TIM6_CCABUF_REG_ADDRESS (0x0A68)
+#define HAL_LL_TIM6_CCABUFL_REG_ADDRESS (0x0A68)
+#define HAL_LL_TIM6_CCABUFH_REG_ADDRESS (0x0A69)
+#define HAL_LL_TIM6_CCBBUF_REG_ADDRESS (0x0A6A)
+#define HAL_LL_TIM6_CCBBUFL_REG_ADDRESS (0x0A6A)
+#define HAL_LL_TIM6_CCBBUFH_REG_ADDRESS (0x0A6B)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (false)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTE1_RXC_IVT (61)
+#define HAL_LL_USARTE1_DRE_IVT (62)
+#define HAL_LL_USARTE1_TXC_IVT (63)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+#define HAL_LL_USARTF0_RXC_IVT (119)
+#define HAL_LL_USARTF0_DRE_IVT (120)
+#define HAL_LL_USARTF0_TXC_IVT (121)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTE1_RXC_IVT_ADDRESS (0x7A)
+#define HAL_LL_USARTE1_DRE_IVT_ADDRESS (0x7C)
+#define HAL_LL_USARTE1_TXC_IVT_ADDRESS (0x7E)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+#define HAL_LL_USARTF0_RXC_IVT_ADDRESS (0xEE)
+#define HAL_LL_USARTF0_DRE_IVT_ADDRESS (0xF0)
+#define HAL_LL_USARTF0_TXC_IVT_ADDRESS (0xF2)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64A3U/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64A3U/mcu_definitions.h
new file mode 100644
index 000000000..57d3aff20
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64A3U/mcu_definitions.h
@@ -0,0 +1,721 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH0
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH1
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB2_CH2
+#define ADC0_PB3_CH11
+#define ADC0_PB3_CH3
+#define ADC0_PB4_CH12
+#define ADC0_PB4_CH4
+#define ADC0_PB5_CH13
+#define ADC0_PB5_CH5
+#define ADC0_PB6_CH14
+#define ADC0_PB6_CH6
+#define ADC0_PB7_CH15
+#define ADC0_PB7_CH7
+#define ADC1_PA0_CH0
+#define ADC1_PB0_CH0
+#define ADC1_PB0_CH8
+#define ADC1_PB1_CH1
+#define ADC1_PB1_CH9
+#define ADC1_PB2_CH10
+#define ADC1_PB2_CH2
+#define ADC1_PB3_CH11
+#define ADC1_PB3_CH3
+#define ADC1_PB4_CH12
+#define ADC1_PB4_CH4
+#define ADC1_PB5_CH13
+#define ADC1_PB5_CH5
+#define ADC1_PB6_CH14
+#define ADC1_PB6_CH6
+#define ADC1_PB7_CH15
+#define ADC1_PB7_CH7
+
+#define ADC_MODULE_0 (1)
+#define ADC_MODULE_1 (2)
+
+#define HAL_LL_AN_COUNT (41)
+#define ADC_MODULE_COUNT (2)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+#define HAL_LL_ADC1_CTRLA_REG_ADDRESS (0x240)
+#define HAL_LL_ADC1_BASE_ADDRESS (HAL_LL_ADC1_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC1_CTRLB_REG_ADDRESS (0x241)
+#define HAL_LL_ADC1_REFCTRL_REG_ADDRESS (0x242)
+#define HAL_LL_ADC1_EVCTRL_REG_ADDRESS (0x243)
+#define HAL_LL_ADC1_PRESCALER_REG_ADDRESS (0x244)
+#define HAL_LL_ADC1_INTFLAGS_REG_ADDRESS (0x246)
+#define HAL_LL_ADC1_TEMP_REG_ADDRESS (0x247)
+#define HAL_LL_ADC1_CH0RESL_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0RESH_REG_ADDRESS (0x251)
+#define HAL_LL_ADC1_CH0RES_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH1RESL_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH1RESH_REG_ADDRESS (0x253)
+#define HAL_LL_ADC1_CH1RES_REG_ADDRESS (0x252)
+#define HAL_LL_ADC1_CH2RESL_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH2RESH_REG_ADDRESS (0x255)
+#define HAL_LL_ADC1_CH2RES_REG_ADDRESS (0x254)
+#define HAL_LL_ADC1_CH3RESL_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH3RESH_REG_ADDRESS (0x257)
+#define HAL_LL_ADC1_CH3RES_REG_ADDRESS (0x256)
+#define HAL_LL_ADC1_CH0CTRL_REG_ADDRESS (0x260)
+#define HAL_LL_ADC1_CH0MUXCTRL_REG_ADDRESS (0x261)
+#define HAL_LL_ADC1_CH0INTCTRL_REG_ADDRESS (0x262)
+#define HAL_LL_ADC1_CH0INTFLAGS_REG_ADDRESS (0x263)
+#define HAL_LL_ADC1_CH1CTRL_REG_ADDRESS (0x268)
+#define HAL_LL_ADC1_CH1MUXCTRL_REG_ADDRESS (0x269)
+#define HAL_LL_ADC1_CH1INTCTRL_REG_ADDRESS (0x26A)
+#define HAL_LL_ADC1_CH1INTFLAGS_REG_ADDRESS (0x26B)
+#define HAL_LL_ADC1_CH2CTRL_REG_ADDRESS (0x270)
+#define HAL_LL_ADC1_CH2MUXCTRL_REG_ADDRESS (0x271)
+#define HAL_LL_ADC1_CH2INTCTRL_REG_ADDRESS (0x272)
+#define HAL_LL_ADC1_CH2INTFLAGS_REG_ADDRESS (0x273)
+#define HAL_LL_ADC1_CH3CTRL_REG_ADDRESS (0x278)
+#define HAL_LL_ADC1_CH3MUXCTRL_REG_ADDRESS (0x279)
+#define HAL_LL_ADC1_CH3INTCTRL_REG_ADDRESS (0x27A)
+#define HAL_LL_ADC1_CH3INTFLAGS_REG_ADDRESS (0x27B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_RXD_PD6_ALT
+#define USARTD0_TXD_PD3
+#define USARTD0_TXD_PD7_ALT
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_RXD_PE6_ALT
+#define USARTE0_TXD_PE3
+#define USARTE0_TXD_PE7_ALT
+#define USARTE1_RXD_PE6
+#define USARTE1_TXD_PE7
+#define USARTF0_RXD_PF2
+#define USARTF0_RXD_PF6_ALT
+#define USARTF0_TXD_PF3
+#define USARTF0_TXD_PF7_ALT
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_E1 (6)
+#define UART_MODULE_5 (UART_MODULE_E1)
+#define UART_MODULE_F0 (7)
+#define UART_MODULE_6 (UART_MODULE_F0)
+#define UART_MODULE_COUNT (7)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+#define HAL_LL_USARTE1_DATA_REG_ADDRESS (0xAB0)
+#define HAL_LL_USARTE1_STATUS_REG_ADDRESS (0xAB1)
+#define HAL_LL_USARTE1_CTRLA_REG_ADDRESS (0xAB3)
+#define HAL_LL_USARTE1_CTRLB_REG_ADDRESS (0xAB4)
+#define HAL_LL_USARTE1_CTRLC_REG_ADDRESS (0xAB5)
+#define HAL_LL_USARTE1_BAUDCTRLA_REG_ADDRESS (0xAB6)
+#define HAL_LL_USARTE1_BAUDCTRLB_REG_ADDRESS (0xAB7)
+#define HAL_LL_USARTF0_DATA_REG_ADDRESS (0xBA0)
+#define HAL_LL_USARTF0_STATUS_REG_ADDRESS (0xBA1)
+#define HAL_LL_USARTF0_CTRLA_REG_ADDRESS (0xBA3)
+#define HAL_LL_USARTF0_CTRLB_REG_ADDRESS (0xBA4)
+#define HAL_LL_USARTF0_CTRLC_REG_ADDRESS (0xBA5)
+#define HAL_LL_USARTF0_BAUDCTRLA_REG_ADDRESS (0xBA6)
+#define HAL_LL_USARTF0_BAUDCTRLB_REG_ADDRESS (0xBA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_MOSI_PD7
+#define SPI1_SCK_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+#define SPI2_MISO_PE6
+#define SPI2_MOSI_PE5
+#define SPI2_MOSI_PE7
+#define SPI2_SCK_PE5
+#define SPI2_SCK_PE7
+#define SPI2_SS_PE4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_2 (3)
+#define SPI_MODULE_COUNT (3)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+#define HAL_LL_SPI2_CTRL_REG_ADDRESS (0xAC0)
+#define HAL_LL_SPI2_INTCTRL_REG_ADDRESS (0xAC1)
+#define HAL_LL_SPI2_STATUS_REG_ADDRESS (0xAC2)
+#define HAL_LL_SPI2_DATA_REG_ADDRESS (0xAC3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+#define TIM0_PC4_CH_A
+#define TIM0_PC5_CH_B
+#define TIM0_PC6_CH_C
+#define TIM0_PC7_CH_D
+#define TIM1_PC4_CH_A
+#define TIM1_PC5_CH_B
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM1_PD4_CH_A
+#define TIM1_PD5_CH_B
+#define TIM1_PD6_CH_C
+#define TIM1_PD7_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM2_PE4_CH_A
+#define TIM2_PE5_CH_B
+#define TIM2_PE6_CH_C
+#define TIM2_PE7_CH_D
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+#define TIM6_PE4_CH_A
+#define TIM6_PE5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_5 (5)
+#define TIM_MODULE_6 (6)
+#define TIM_MODULE_COUNT (6)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x94A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x94B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x94C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x94F)
+#define HAL_LL_TIM5_CNT_REG_ADDRESS (0x960)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x967)
+#define HAL_LL_TIM5_PER_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_CCA_REG_ADDRESS (0x968)
+#define HAL_LL_TIM5_CCB_REG_ADDRESS (0x96A)
+#define HAL_LL_TIM5_PERBUF_REG_ADDRESS (0x976)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x978)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x97A)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM6_CTRLA_REG_ADDRESS (0xA40)
+#define HAL_LL_TIM6_CTRLB_REG_ADDRESS (0xA41)
+#define HAL_LL_TIM6_CTRLC_REG_ADDRESS (0xA42)
+#define HAL_LL_TIM6_CTRLD_REG_ADDRESS (0xA43)
+#define HAL_LL_TIM6_CTRLE_REG_ADDRESS (0xA44)
+#define HAL_LL_TIM6_INTCTRLA_REG_ADDRESS (0xA46)
+#define HAL_LL_TIM6_INTCTRLB_REG_ADDRESS (0xA47)
+#define HAL_LL_TIM6_CTRLFCLR_REG_ADDRESS (0xA48)
+#define HAL_LL_TIM6_CTRLFSET_REG_ADDRESS (0xA49)
+#define HAL_LL_TIM6_CTRLGCLR_REG_ADDRESS (0xA4A)
+#define HAL_LL_TIM6_CTRLGSET_REG_ADDRESS (0xA4B)
+#define HAL_LL_TIM6_INTFLAGS_REG_ADDRESS (0xA4C)
+#define HAL_LL_TIM6_TEMP_REG_ADDRESS (0xA4F)
+#define HAL_LL_TIM6_CNT_REG_ADDRESS (0xA60)
+#define HAL_LL_TIM6_PERL_REG_ADDRESS (0xA66)
+#define HAL_LL_TIM6_PERH_REG_ADDRESS (0xA67)
+#define HAL_LL_TIM6_PER_REG_ADDRESS (0xA66)
+#define HAL_LL_TIM6_CCA_REG_ADDRESS (0xA68)
+#define HAL_LL_TIM6_CCB_REG_ADDRESS (0xA6A)
+#define HAL_LL_TIM6_PERBUF_REG_ADDRESS (0xA76)
+#define HAL_LL_TIM6_CCABUF_REG_ADDRESS (0xA78)
+#define HAL_LL_TIM6_CCBBUF_REG_ADDRESS (0xA7A)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0xB00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0xB01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0xB02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0xB03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0xB04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0xB06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0xB07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0xB08)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0xB0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0xB0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0xB0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0xB0F)
+#define HAL_LL_TIM3_PERBUF_REG_ADDRESS (0xB36)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0xB38)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0xB3A)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0xB3C)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0xB3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM3_CNT_REG_ADDRESS (0xB20)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0xB26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0xB27)
+#define HAL_LL_TIM3_CCA_REG_ADDRESS (0xB28)
+#define HAL_LL_TIM3_CCB_REG_ADDRESS (0xB2A)
+#define HAL_LL_TIM3_CCC_REG_ADDRESS (0xB2C)
+#define HAL_LL_TIM3_CCD_REG_ADDRESS (0xB2E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTF_REMAP_REG_ADDRESS (0x6AE)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTE1_RXC_IVT (61)
+#define HAL_LL_USARTE1_DRE_IVT (62)
+#define HAL_LL_USARTE1_TXC_IVT (63)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+#define HAL_LL_USARTF0_RXC_IVT (119)
+#define HAL_LL_USARTF0_DRE_IVT (120)
+#define HAL_LL_USARTF0_TXC_IVT (121)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTE1_RXC_IVT_ADDRESS (0x7A)
+#define HAL_LL_USARTE1_DRE_IVT_ADDRESS (0x7C)
+#define HAL_LL_USARTE1_TXC_IVT_ADDRESS (0x7E)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+#define HAL_LL_USARTF0_RXC_IVT_ADDRESS (0xEE)
+#define HAL_LL_USARTF0_DRE_IVT_ADDRESS (0xF0)
+#define HAL_LL_USARTF0_TXC_IVT_ADDRESS (0xF2)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64A4U/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64A4U/mcu_definitions.h
new file mode 100644
index 000000000..88558ebc8
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64A4U/mcu_definitions.h
@@ -0,0 +1,529 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB3_CH11
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (12)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH1RESL_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH1RESH_REG_ADDRESS (0x213)
+#define HAL_LL_ADC0_CH1RES_REG_ADDRESS (0x212)
+#define HAL_LL_ADC0_CH2RESL_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH2RESH_REG_ADDRESS (0x215)
+#define HAL_LL_ADC0_CH2RES_REG_ADDRESS (0x214)
+#define HAL_LL_ADC0_CH3RESL_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH3RESH_REG_ADDRESS (0x217)
+#define HAL_LL_ADC0_CH3RES_REG_ADDRESS (0x216)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC0_CH1CTRL_REG_ADDRESS (0x228)
+#define HAL_LL_ADC0_CH1MUXCTRL_REG_ADDRESS (0x229)
+#define HAL_LL_ADC0_CH1INTCTRL_REG_ADDRESS (0x22A)
+#define HAL_LL_ADC0_CH1INTFLAGS_REG_ADDRESS (0x22B)
+#define HAL_LL_ADC0_CH2CTRL_REG_ADDRESS (0x230)
+#define HAL_LL_ADC0_CH2MUXCTRL_REG_ADDRESS (0x231)
+#define HAL_LL_ADC0_CH2INTCTRL_REG_ADDRESS (0x232)
+#define HAL_LL_ADC0_CH2INTFLAGS_REG_ADDRESS (0x233)
+#define HAL_LL_ADC0_CH3CTRL_REG_ADDRESS (0x238)
+#define HAL_LL_ADC0_CH3MUXCTRL_REG_ADDRESS (0x239)
+#define HAL_LL_ADC0_CH3INTCTRL_REG_ADDRESS (0x23A)
+#define HAL_LL_ADC0_CH3INTFLAGS_REG_ADDRESS (0x23B)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTC1_RXD_PC6
+#define USARTC1_TXD_PC7
+#define USARTD0_RXD_PD2
+#define USARTD0_RXD_PD6_ALT
+#define USARTD0_TXD_PD3
+#define USARTD0_TXD_PD7_ALT
+#define USARTD1_RXD_PD6
+#define USARTD1_TXD_PD7
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_C1 (2)
+#define UART_MODULE_1 (UART_MODULE_C1)
+#define UART_MODULE_D0 (3)
+#define UART_MODULE_2 (UART_MODULE_D0)
+#define UART_MODULE_D1 (4)
+#define UART_MODULE_3 (UART_MODULE_D1)
+#define UART_MODULE_E0 (5)
+#define UART_MODULE_4 (UART_MODULE_E0)
+#define UART_MODULE_COUNT (5)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTC1_DATA_REG_ADDRESS (0x8B0)
+#define HAL_LL_USARTC1_STATUS_REG_ADDRESS (0x8B1)
+#define HAL_LL_USARTC1_CTRLA_REG_ADDRESS (0x8B3)
+#define HAL_LL_USARTC1_CTRLB_REG_ADDRESS (0x8B4)
+#define HAL_LL_USARTC1_CTRLC_REG_ADDRESS (0x8B5)
+#define HAL_LL_USARTC1_BAUDCTRLA_REG_ADDRESS (0x8B6)
+#define HAL_LL_USARTC1_BAUDCTRLB_REG_ADDRESS (0x8B7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTD1_DATA_REG_ADDRESS (0x9B0)
+#define HAL_LL_USARTD1_STATUS_REG_ADDRESS (0x9B1)
+#define HAL_LL_USARTD1_CTRLA_REG_ADDRESS (0x9B3)
+#define HAL_LL_USARTD1_CTRLB_REG_ADDRESS (0x9B4)
+#define HAL_LL_USARTD1_CTRLC_REG_ADDRESS (0x9B5)
+#define HAL_LL_USARTD1_BAUDCTRLA_REG_ADDRESS (0x9B6)
+#define HAL_LL_USARTD1_BAUDCTRLB_REG_ADDRESS (0x9B7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_MOSI_PD7
+#define SPI1_SCK_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+#define TIM0_PC4_CH_A
+#define TIM0_PC5_CH_B
+#define TIM0_PC6_CH_C
+#define TIM0_PC7_CH_D
+#define TIM1_PC4_CH_A
+#define TIM1_PC5_CH_B
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM1_PD4_CH_A
+#define TIM1_PD5_CH_B
+#define TIM1_PD6_CH_C
+#define TIM1_PD7_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM5_PD4_CH_A
+#define TIM5_PD5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_5 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM5_CTRLA_REG_ADDRESS (0x940)
+#define HAL_LL_TIM5_CTRLB_REG_ADDRESS (0x941)
+#define HAL_LL_TIM5_CTRLC_REG_ADDRESS (0x942)
+#define HAL_LL_TIM5_CTRLD_REG_ADDRESS (0x943)
+#define HAL_LL_TIM5_CTRLE_REG_ADDRESS (0x944)
+#define HAL_LL_TIM5_INTCTRLA_REG_ADDRESS (0x946)
+#define HAL_LL_TIM5_INTCTRLB_REG_ADDRESS (0x947)
+#define HAL_LL_TIM5_CTRLFCLR_REG_ADDRESS (0x948)
+#define HAL_LL_TIM5_CTRLFSET_REG_ADDRESS (0x949)
+#define HAL_LL_TIM5_CTRLGCLR_REG_ADDRESS (0x94A)
+#define HAL_LL_TIM5_CTRLGSET_REG_ADDRESS (0x94B)
+#define HAL_LL_TIM5_INTFLAGS_REG_ADDRESS (0x94C)
+#define HAL_LL_TIM5_TEMP_REG_ADDRESS (0x94F)
+#define HAL_LL_TIM5_CNT_REG_ADDRESS (0x960)
+#define HAL_LL_TIM5_PERL_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_PERH_REG_ADDRESS (0x967)
+#define HAL_LL_TIM5_PER_REG_ADDRESS (0x966)
+#define HAL_LL_TIM5_CCA_REG_ADDRESS (0x968)
+#define HAL_LL_TIM5_CCB_REG_ADDRESS (0x96A)
+#define HAL_LL_TIM5_PERBUF_REG_ADDRESS (0x976)
+#define HAL_LL_TIM5_CCABUF_REG_ADDRESS (0x978)
+#define HAL_LL_TIM5_CCBBUF_REG_ADDRESS (0x97A)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLFSET_REG_ADDRESS (0xA09)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_PER_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTC1_RXC_IVT (28)
+#define HAL_LL_USARTC1_DRE_IVT (29)
+#define HAL_LL_USARTC1_TXC_IVT (30)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+#define HAL_LL_USARTD1_RXC_IVT (91)
+#define HAL_LL_USARTD1_DRE_IVT (92)
+#define HAL_LL_USARTD1_TXC_IVT (93)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTC1_RXC_IVT_ADDRESS (0x38)
+#define HAL_LL_USARTC1_DRE_IVT_ADDRESS (0x3A)
+#define HAL_LL_USARTC1_TXC_IVT_ADDRESS (0x3C)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+#define HAL_LL_USARTD1_RXC_IVT_ADDRESS (0xB6)
+#define HAL_LL_USARTD1_DRE_IVT_ADDRESS (0xB8)
+#define HAL_LL_USARTD1_TXC_IVT_ADDRESS (0xBA)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64B1/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64B1/mcu_definitions.h
new file mode 100644
index 000000000..a7fb57ba1
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64B1/mcu_definitions.h
@@ -0,0 +1,435 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PB0_CH0
+#define ADC0_PB0_CH7
+#define ADC0_PB1_CH1
+#define ADC0_PB1_CH8
+#define ADC0_PB2_CH2
+#define ADC0_PB2_CH9
+#define ADC0_PB3_CH10
+#define ADC0_PB3_CH3
+#define ADC0_PB4_CH11
+#define ADC0_PB4_CH4
+#define ADC0_PB5_CH12
+#define ADC0_PB5_CH5
+#define ADC0_PB6_CH13
+#define ADC0_PB6_CH6
+#define ADC0_PB7_CH14
+#define ADC0_PB7_CH7
+#define ADC1_PA0_CH0
+#define ADC1_PB0_CH0
+#define ADC1_PB0_CH7
+#define ADC1_PB1_CH1
+#define ADC1_PB1_CH8
+#define ADC1_PB2_CH2
+#define ADC1_PB2_CH9
+#define ADC1_PB3_CH10
+#define ADC1_PB3_CH3
+#define ADC1_PB4_CH11
+#define ADC1_PB4_CH4
+#define ADC1_PB5_CH12
+#define ADC1_PB5_CH5
+#define ADC1_PB6_CH13
+#define ADC1_PB6_CH6
+#define ADC1_PB7_CH14
+#define ADC1_PB7_CH7
+
+#define ADC_MODULE_0 (1)
+#define ADC_MODULE_1 (2)
+
+#define HAL_LL_AN_COUNT (40)
+#define ADC_MODULE_COUNT (2)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+#define HAL_LL_ADC1_CTRLA_REG_ADDRESS (0x240)
+#define HAL_LL_ADC1_BASE_ADDRESS (HAL_LL_ADC1_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC1_CTRLB_REG_ADDRESS (0x241)
+#define HAL_LL_ADC1_REFCTRL_REG_ADDRESS (0x242)
+#define HAL_LL_ADC1_EVCTRL_REG_ADDRESS (0x243)
+#define HAL_LL_ADC1_PRESCALER_REG_ADDRESS (0x244)
+#define HAL_LL_ADC1_INTFLAGS_REG_ADDRESS (0x246)
+#define HAL_LL_ADC1_TEMP_REG_ADDRESS (0x247)
+#define HAL_LL_ADC1_CH0RESL_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0RESH_REG_ADDRESS (0x251)
+#define HAL_LL_ADC1_CH0RES_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0CTRL_REG_ADDRESS (0x260)
+#define HAL_LL_ADC1_CH0MUXCTRL_REG_ADDRESS (0x261)
+#define HAL_LL_ADC1_CH0INTCTRL_REG_ADDRESS (0x262)
+#define HAL_LL_ADC1_CH0INTFLAGS_REG_ADDRESS (0x263)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTE0_RXD_PE2
+#define USARTE0_RXD_PE6_ALT
+#define USARTE0_TXD_PE3
+#define USARTE0_TXD_PE7_ALT
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_E0 (2)
+#define UART_MODULE_1 (UART_MODULE_E0)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_2 (2)
+#define TIM_MODULE_4 (3)
+#define TIM_MODULE_COUNT (3)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+#define __PM0_CN
+#define __PM1_CN
+#define __PM2_CN
+#define __PM3_CN
+#define __PM4_CN
+#define __PM5_CN
+#define __PM6_CN
+#define __PM7_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_G_CN
+#define __PORT_M_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (8)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRG_REG_ADDRESS (0x6C0)
+#define PORTG_REG_ADDRESS (0x6C4)
+#define PING_REG_ADDRESS (0x6C8)
+#define DDRM_REG_ADDRESS (0x760)
+#define PORTM_REG_ADDRESS (0x764)
+#define PINM_REG_ADDRESS (0x768)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTG_REMAP_REG_ADDRESS (0x6CE)
+#define PORTM_REMAP_REG_ADDRESS (0x76E)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTE0_RXC_IVT (69)
+#define HAL_LL_USARTE0_DRE_IVT (70)
+#define HAL_LL_USARTE0_TXC_IVT (71)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x8A)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x8C)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x8E)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64B3/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64B3/mcu_definitions.h
new file mode 100644
index 000000000..f99228153
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64B3/mcu_definitions.h
@@ -0,0 +1,312 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC1_PB0_CH0
+#define ADC1_PB1_CH1
+#define ADC1_PB2_CH2
+#define ADC1_PB3_CH3
+#define ADC1_PB4_CH4
+#define ADC1_PB5_CH5
+#define ADC1_PB6_CH6
+#define ADC1_PB7_CH7
+
+#define ADC_MODULE_1 (1)
+
+#define HAL_LL_AN_COUNT (8)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC1_CTRLA_REG_ADDRESS (0x240)
+#define HAL_LL_ADC1_BASE_ADDRESS (HAL_LL_ADC1_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC1_CTRLB_REG_ADDRESS (0x241)
+#define HAL_LL_ADC1_REFCTRL_REG_ADDRESS (0x242)
+#define HAL_LL_ADC1_EVCTRL_REG_ADDRESS (0x243)
+#define HAL_LL_ADC1_PRESCALER_REG_ADDRESS (0x244)
+#define HAL_LL_ADC1_INTFLAGS_REG_ADDRESS (0x246)
+#define HAL_LL_ADC1_TEMP_REG_ADDRESS (0x247)
+#define HAL_LL_ADC1_CH0RESL_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0RESH_REG_ADDRESS (0x251)
+#define HAL_LL_ADC1_CH0RES_REG_ADDRESS (0x250)
+#define HAL_LL_ADC1_CH0CTRL_REG_ADDRESS (0x260)
+#define HAL_LL_ADC1_CH0MUXCTRL_REG_ADDRESS (0x261)
+#define HAL_LL_ADC1_CH0INTCTRL_REG_ADDRESS (0x262)
+#define HAL_LL_ADC1_CH0INTFLAGS_REG_ADDRESS (0x263)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_COUNT (1)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_COUNT (1)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_COUNT (1)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_4 (2)
+#define TIM_MODULE_COUNT (2)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PG0_CN
+#define __PG1_CN
+#define __PG2_CN
+#define __PG3_CN
+#define __PG4_CN
+#define __PG5_CN
+#define __PG6_CN
+#define __PG7_CN
+#define __PM0_CN
+#define __PM1_CN
+#define __PM2_CN
+#define __PM3_CN
+#define __PM4_CN
+#define __PM5_CN
+#define __PM6_CN
+#define __PM7_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_G_CN
+#define __PORT_M_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRG_REG_ADDRESS (0x6C0)
+#define PORTG_REG_ADDRESS (0x6C4)
+#define PING_REG_ADDRESS (0x6C8)
+#define DDRM_REG_ADDRESS (0x760)
+#define PORTM_REG_ADDRESS (0x764)
+#define PINM_REG_ADDRESS (0x768)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTG_REMAP_REG_ADDRESS (0x6CE)
+#define PORTM_REMAP_REG_ADDRESS (0x76E)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPB_REG_ADDRESS (0x72)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64D3/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64D3/mcu_definitions.h
new file mode 100644
index 000000000..459c73d5c
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64D3/mcu_definitions.h
@@ -0,0 +1,498 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB3_CH11
+#define ADC0_PB4_CH12
+#define ADC0_PB5_CH13
+#define ADC0_PB6_CH14
+#define ADC0_PB7_CH15
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (16)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+#define USARTE0_RXD_PE2
+#define USARTE0_TXD_PE3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_D0 (2)
+#define UART_MODULE_1 (UART_MODULE_D0)
+#define UART_MODULE_E0 (3)
+#define UART_MODULE_2 (UART_MODULE_E0)
+#define UART_MODULE_COUNT (3)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+#define HAL_LL_USARTE0_DATA_REG_ADDRESS (0xAA0)
+#define HAL_LL_USARTE0_STATUS_REG_ADDRESS (0xAA1)
+#define HAL_LL_USARTE0_CTRLA_REG_ADDRESS (0xAA3)
+#define HAL_LL_USARTE0_CTRLB_REG_ADDRESS (0xAA4)
+#define HAL_LL_USARTE0_CTRLC_REG_ADDRESS (0xAA5)
+#define HAL_LL_USARTE0_BAUDCTRLA_REG_ADDRESS (0xAA6)
+#define HAL_LL_USARTE0_BAUDCTRLB_REG_ADDRESS (0xAA7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+#define HAL_LL_SPI2_CTRL_REG_ADDRESS (0xAC0)
+#define HAL_LL_SPI2_INTCTRL_REG_ADDRESS (0xAC1)
+#define HAL_LL_SPI2_STATUS_REG_ADDRESS (0xAC2)
+#define HAL_LL_SPI2_DATA_REG_ADDRESS (0xAC3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+// TODO - Alternate pins to be implemented in a future release
+// #define TIM0_PC4_CH_A_ALT
+// #define TIM0_PC5_CH_B_ALT
+// #define TIM0_PC6_CH_C_ALT
+// #define TIM0_PC7_CH_D_ALT
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM3_PF0_CH_A
+#define TIM3_PF1_CH_B
+#define TIM3_PF2_CH_C
+#define TIM3_PF3_CH_D
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_3 (4)
+#define TIM_MODULE_4 (5)
+#define TIM_MODULE_COUNT (5)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM3_CTRLA_REG_ADDRESS (0xB00)
+#define HAL_LL_TIM3_CTRLB_REG_ADDRESS (0xB01)
+#define HAL_LL_TIM3_CTRLC_REG_ADDRESS (0xB02)
+#define HAL_LL_TIM3_CTRLD_REG_ADDRESS (0xB03)
+#define HAL_LL_TIM3_CTRLE_REG_ADDRESS (0xB04)
+#define HAL_LL_TIM3_INTCTRLA_REG_ADDRESS (0xB06)
+#define HAL_LL_TIM3_INTCTRLB_REG_ADDRESS (0xB07)
+#define HAL_LL_TIM3_CTRLFCLR_REG_ADDRESS (0xB08)
+#define HAL_LL_TIM3_CTRLGCLR_REG_ADDRESS (0xB0A)
+#define HAL_LL_TIM3_CTRLGSET_REG_ADDRESS (0xB0B)
+#define HAL_LL_TIM3_INTFLAGS_REG_ADDRESS (0xB0C)
+#define HAL_LL_TIM3_TEMP_REG_ADDRESS (0xB0F)
+#define HAL_LL_TIM3_PERBUF_REG_ADDRESS (0xB36)
+#define HAL_LL_TIM3_CCABUF_REG_ADDRESS (0xB38)
+#define HAL_LL_TIM3_CCBBUF_REG_ADDRESS (0xB3A)
+#define HAL_LL_TIM3_CCCBUF_REG_ADDRESS (0xB3C)
+#define HAL_LL_TIM3_CCDBUF_REG_ADDRESS (0xB3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM3_CNT_REG_ADDRESS (0xB20)
+#define HAL_LL_TIM3_PERL_REG_ADDRESS (0xB26)
+#define HAL_LL_TIM3_PERH_REG_ADDRESS (0xB27)
+#define HAL_LL_TIM3_CCA_REG_ADDRESS (0xB28)
+#define HAL_LL_TIM3_CCB_REG_ADDRESS (0xB2A)
+#define HAL_LL_TIM3_CCC_REG_ADDRESS (0xB2C)
+#define HAL_LL_TIM3_CCD_REG_ADDRESS (0xB2E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PB4_CN
+#define __PB5_CN
+#define __PB6_CN
+#define __PB7_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PE4_CN
+#define __PE5_CN
+#define __PE6_CN
+#define __PE7_CN
+#define __PF0_CN
+#define __PF1_CN
+#define __PF2_CN
+#define __PF3_CN
+#define __PF4_CN
+#define __PF5_CN
+#define __PF6_CN
+#define __PF7_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_F_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (7)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRF_REG_ADDRESS (0x6A0)
+#define PORTF_REG_ADDRESS (0x6A4)
+#define PINF_REG_ADDRESS (0x6A8)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTF_REMAP_REG_ADDRESS (0x6AE)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTE0_RXC_IVT (58)
+#define HAL_LL_USARTE0_DRE_IVT (59)
+#define HAL_LL_USARTE0_TXC_IVT (60)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTE0_RXC_IVT_ADDRESS (0x74)
+#define HAL_LL_USARTE0_DRE_IVT_ADDRESS (0x76)
+#define HAL_LL_USARTE0_TXC_IVT_ADDRESS (0x78)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64D4/mcu_definitions.h b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64D4/mcu_definitions.h
new file mode 100644
index 000000000..b5baf1612
--- /dev/null
+++ b/targets/avr_8bit/mikroe/common/include/mcu_definitions/ATXMEGA64D4/mcu_definitions.h
@@ -0,0 +1,425 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+* @file  mcu_definitions.h
+* @brief MCU specific pin and module definitions.
+*/
+
+#ifndef _MCU_DEFINITIONS_H_
+#define _MCU_DEFINITIONS_H_
+
+// ADC
+#define ADC0_PA0_CH0
+#define ADC0_PA1_CH1
+#define ADC0_PA2_CH2
+#define ADC0_PA3_CH3
+#define ADC0_PA4_CH4
+#define ADC0_PA5_CH5
+#define ADC0_PA6_CH6
+#define ADC0_PA7_CH7
+#define ADC0_PB0_CH8
+#define ADC0_PB1_CH9
+#define ADC0_PB2_CH10
+#define ADC0_PB3_CH11
+
+#define ADC_MODULE_0 (1)
+
+#define HAL_LL_AN_COUNT (12)
+#define ADC_MODULE_COUNT (1)
+
+// ADC Register addresses and offsets
+#define HAL_LL_ADC0_CTRLA_REG_ADDRESS (0x200)
+#define HAL_LL_ADC0_BASE_ADDRESS (HAL_LL_ADC0_CTRLA_REG_ADDRESS)
+#define HAL_LL_ADC0_CTRLB_REG_ADDRESS (0x201)
+#define HAL_LL_ADC0_REFCTRL_REG_ADDRESS (0x202)
+#define HAL_LL_ADC0_EVCTRL_REG_ADDRESS (0x203)
+#define HAL_LL_ADC0_PRESCALER_REG_ADDRESS (0x204)
+#define HAL_LL_ADC0_INTFLAGS_REG_ADDRESS (0x206)
+#define HAL_LL_ADC0_TEMP_REG_ADDRESS (0x207)
+#define HAL_LL_ADC0_CH0RESL_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0RESH_REG_ADDRESS (0x211)
+#define HAL_LL_ADC0_CH0RES_REG_ADDRESS (0x210)
+#define HAL_LL_ADC0_CH0CTRL_REG_ADDRESS (0x220)
+#define HAL_LL_ADC0_CH0MUXCTRL_REG_ADDRESS (0x221)
+#define HAL_LL_ADC0_CH0INTCTRL_REG_ADDRESS (0x222)
+#define HAL_LL_ADC0_CH0INTFLAGS_REG_ADDRESS (0x223)
+// EOF ADC Register addresses and offsets
+// EOF ADC
+
+// I2C
+#define TWIC_SCL_PC1
+#define TWIC_SDA_PC0
+#define TWIE_SCL_PE1
+#define TWIE_SDA_PE0
+
+#define TWI_MODULE_C (1)
+#define I2C_MODULE_0 (TWI_MODULE_C)
+#define TWI_MODULE_E (2)
+#define I2C_MODULE_1 (TWI_MODULE_E)
+#define TWI_MODULE_COUNT (2)
+#define I2C_MODULE_COUNT (TWI_MODULE_COUNT)
+
+// I2C Register addresses and offsets
+#define HAL_LL_TWIC_CTRL_REG_ADDRESS (0x480)
+#define HAL_LL_I2C0_BASE_ADDRESS (HAL_LL_TWIC_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIC_MASTERCTRLA_REG_ADDRESS (0x481)
+#define HAL_LL_TWIC_MASTERCTRLB_REG_ADDRESS (0x482)
+#define HAL_LL_TWIC_MASTERCTRLC_REG_ADDRESS (0x483)
+#define HAL_LL_TWIC_MASTERSTATUS_REG_ADDRESS (0x484)
+#define HAL_LL_TWIC_MASTERBAUD_REG_ADDRESS (0x485)
+#define HAL_LL_TWIC_MASTERADDR_REG_ADDRESS (0x486)
+#define HAL_LL_TWIC_MASTERDATA_REG_ADDRESS (0x487)
+#define HAL_LL_TWIC_SLAVECTRLA_REG_ADDRESS (0x488)
+#define HAL_LL_TWIC_SLAVECTRLB_REG_ADDRESS (0x489)
+#define HAL_LL_TWIC_SLAVESTATUS_REG_ADDRESS (0x48A)
+#define HAL_LL_TWIC_SLAVEADDR_REG_ADDRESS (0x48B)
+#define HAL_LL_TWIC_SLAVEDATA_REG_ADDRESS (0x48C)
+#define HAL_LL_TWIC_SLAVEADDRMASK_REG_ADDRESS (0x48D)
+#define HAL_LL_TWIE_CTRL_REG_ADDRESS (0x4A0)
+#define HAL_LL_I2C2_BASE_ADDRESS (HAL_LL_TWIE_CTRL_REG_ADDRESS)
+#define HAL_LL_TWIE_MASTERCTRLA_REG_ADDRESS (0x4A1)
+#define HAL_LL_TWIE_MASTERCTRLB_REG_ADDRESS (0x4A2)
+#define HAL_LL_TWIE_MASTERCTRLC_REG_ADDRESS (0x4A3)
+#define HAL_LL_TWIE_MASTERSTATUS_REG_ADDRESS (0x4A4)
+#define HAL_LL_TWIE_MASTERBAUD_REG_ADDRESS (0x4A5)
+#define HAL_LL_TWIE_MASTERADDR_REG_ADDRESS (0x4A6)
+#define HAL_LL_TWIE_MASTERDATA_REG_ADDRESS (0x4A7)
+#define HAL_LL_TWIE_SLAVECTRLA_REG_ADDRESS (0x4A8)
+#define HAL_LL_TWIE_SLAVECTRLB_REG_ADDRESS (0x4A9)
+#define HAL_LL_TWIE_SLAVESTATUS_REG_ADDRESS (0x4AA)
+#define HAL_LL_TWIE_SLAVEADDR_REG_ADDRESS (0x4AB)
+#define HAL_LL_TWIE_SLAVEDATA_REG_ADDRESS (0x4AC)
+#define HAL_LL_TWIE_SLAVEADDRMASK_REG_ADDRESS (0x4AD)
+// EOF I2C Register addresses and offsets
+// EOF I2C
+
+// U(S)ART
+#define USARTC0_RXD_PC2
+#define USARTC0_RXD_PC6_ALT
+#define USARTC0_TXD_PC3
+#define USARTC0_TXD_PC7_ALT
+#define USARTD0_RXD_PD2
+#define USARTD0_TXD_PD3
+
+#define UART_MODULE_C0 (1)
+#define UART_MODULE_0 (UART_MODULE_C0)
+#define UART_MODULE_D0 (2)
+#define UART_MODULE_1 (UART_MODULE_D0)
+#define UART_MODULE_COUNT (2)
+
+// U(S)ART Register addresses and offsets
+#define HAL_LL_USARTC0_DATA_REG_ADDRESS (0x8A0)
+#define HAL_LL_USARTC0_STATUS_REG_ADDRESS (0x8A1)
+#define HAL_LL_USARTC0_CTRLA_REG_ADDRESS (0x8A3)
+#define HAL_LL_USARTC0_CTRLB_REG_ADDRESS (0x8A4)
+#define HAL_LL_USARTC0_CTRLC_REG_ADDRESS (0x8A5)
+#define HAL_LL_USARTC0_BAUDCTRLA_REG_ADDRESS (0x8A6)
+#define HAL_LL_USARTC0_BAUDCTRLB_REG_ADDRESS (0x8A7)
+#define HAL_LL_USARTD0_DATA_REG_ADDRESS (0x9A0)
+#define HAL_LL_USARTD0_STATUS_REG_ADDRESS (0x9A1)
+#define HAL_LL_USARTD0_CTRLA_REG_ADDRESS (0x9A3)
+#define HAL_LL_USARTD0_CTRLB_REG_ADDRESS (0x9A4)
+#define HAL_LL_USARTD0_CTRLC_REG_ADDRESS (0x9A5)
+#define HAL_LL_USARTD0_BAUDCTRLA_REG_ADDRESS (0x9A6)
+#define HAL_LL_USARTD0_BAUDCTRLB_REG_ADDRESS (0x9A7)
+// EOF U(S)ART Register addresses and offsets
+// EOF U(S)ART
+
+// SPI
+#define SPI0_MISO_PC6
+#define SPI0_MOSI_PC5
+#define SPI0_MOSI_PC7
+#define SPI0_SCK_PC5
+#define SPI0_SCK_PC7
+#define SPI0_SS_PC4
+#define SPI1_MISO_PD6
+#define SPI1_MOSI_PD5
+#define SPI1_SCK_PD7
+#define SPI1_SS_PD4
+
+#define SPI_MODULE_0 (1)
+#define SPI_MODULE_1 (2)
+#define SPI_MODULE_COUNT (2)
+
+// SPI Register addresses and offsets
+#define HAL_LL_SPI0_CTRL_REG_ADDRESS (0x8C0)
+#define HAL_LL_SPI0_INTCTRL_REG_ADDRESS (0x8C1)
+#define HAL_LL_SPI0_STATUS_REG_ADDRESS (0x8C2)
+#define HAL_LL_SPI0_DATA_REG_ADDRESS (0x8C3)
+#define HAL_LL_SPI1_CTRL_REG_ADDRESS (0x9C0)
+#define HAL_LL_SPI1_INTCTRL_REG_ADDRESS (0x9C1)
+#define HAL_LL_SPI1_STATUS_REG_ADDRESS (0x9C2)
+#define HAL_LL_SPI1_DATA_REG_ADDRESS (0x9C3)
+// EOF SPI Register addresses and offsets
+// EOF SPI
+
+// TIM
+#define TIM0_PC0_CH_A
+#define TIM0_PC1_CH_B
+#define TIM0_PC2_CH_C
+#define TIM0_PC3_CH_D
+// TODO - Alternate pins to be implemented in a future release
+// #define TIM0_PC4_CH_A_ALT
+// #define TIM0_PC5_CH_B_ALT
+// #define TIM0_PC6_CH_C_ALT
+// #define TIM0_PC7_CH_D_ALT
+#define TIM1_PD0_CH_A
+#define TIM1_PD1_CH_B
+#define TIM1_PD2_CH_C
+#define TIM1_PD3_CH_D
+#define TIM2_PE0_CH_A
+#define TIM2_PE1_CH_B
+#define TIM2_PE2_CH_C
+#define TIM2_PE3_CH_D
+#define TIM4_PC4_CH_A
+#define TIM4_PC5_CH_B
+
+#define TIM_MODULE_0 (1)
+#define TIM_MODULE_1 (2)
+#define TIM_MODULE_2 (3)
+#define TIM_MODULE_4 (4)
+#define TIM_MODULE_COUNT (4)
+
+// TIM Register addresses and offsets
+#define HAL_LL_TIM0_CTRLA_REG_ADDRESS (0x800)
+#define HAL_LL_TIM0_CTRLB_REG_ADDRESS (0x801)
+#define HAL_LL_TIM0_CTRLC_REG_ADDRESS (0x802)
+#define HAL_LL_TIM0_CTRLD_REG_ADDRESS (0x803)
+#define HAL_LL_TIM0_CTRLE_REG_ADDRESS (0x804)
+#define HAL_LL_TIM0_INTCTRLA_REG_ADDRESS (0x806)
+#define HAL_LL_TIM0_INTCTRLB_REG_ADDRESS (0x807)
+#define HAL_LL_TIM0_CTRLFCLR_REG_ADDRESS (0x808)
+#define HAL_LL_TIM0_CTRLGCLR_REG_ADDRESS (0x80A)
+#define HAL_LL_TIM0_CTRLGSET_REG_ADDRESS (0x80B)
+#define HAL_LL_TIM0_INTFLAGS_REG_ADDRESS (0x80C)
+#define HAL_LL_TIM0_TEMP_REG_ADDRESS (0x80F)
+#define HAL_LL_TIM0_PERBUF_REG_ADDRESS (0x836)
+#define HAL_LL_TIM0_CCABUF_REG_ADDRESS (0x838)
+#define HAL_LL_TIM0_CCBBUF_REG_ADDRESS (0x83A)
+#define HAL_LL_TIM0_CCCBUF_REG_ADDRESS (0x83C)
+#define HAL_LL_TIM0_CCDBUF_REG_ADDRESS (0x83E)
+#define HAL_LL_TIM4_CTRLA_REG_ADDRESS (0x840)
+#define HAL_LL_TIM4_CTRLB_REG_ADDRESS (0x841)
+#define HAL_LL_TIM4_CTRLC_REG_ADDRESS (0x842)
+#define HAL_LL_TIM4_CTRLD_REG_ADDRESS (0x843)
+#define HAL_LL_TIM4_CTRLE_REG_ADDRESS (0x844)
+#define HAL_LL_TIM4_INTCTRLA_REG_ADDRESS (0x846)
+#define HAL_LL_TIM4_INTCTRLB_REG_ADDRESS (0x847)
+#define HAL_LL_TIM4_CTRLFCLR_REG_ADDRESS (0x848)
+#define HAL_LL_TIM4_CTRLFSET_REG_ADDRESS (0x849)
+#define HAL_LL_TIM4_CTRLGCLR_REG_ADDRESS (0x84A)
+#define HAL_LL_TIM4_CTRLGSET_REG_ADDRESS (0x84B)
+#define HAL_LL_TIM4_INTFLAGS_REG_ADDRESS (0x84C)
+#define HAL_LL_TIM4_TEMP_REG_ADDRESS (0x84F)
+#define HAL_LL_TIM4_CNT_REG_ADDRESS (0x860)
+#define HAL_LL_TIM4_PERL_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_PERH_REG_ADDRESS (0x867)
+#define HAL_LL_TIM4_PER_REG_ADDRESS (0x866)
+#define HAL_LL_TIM4_CCA_REG_ADDRESS (0x868)
+#define HAL_LL_TIM4_CCB_REG_ADDRESS (0x86A)
+#define HAL_LL_TIM4_PERBUF_REG_ADDRESS (0x876)
+#define HAL_LL_TIM4_CCABUF_REG_ADDRESS (0x878)
+#define HAL_LL_TIM4_CCBBUF_REG_ADDRESS (0x87A)
+#define HAL_LL_TIM1_CTRLA_REG_ADDRESS (0x900)
+#define HAL_LL_TIM1_CTRLB_REG_ADDRESS (0x901)
+#define HAL_LL_TIM1_CTRLC_REG_ADDRESS (0x902)
+#define HAL_LL_TIM1_CTRLD_REG_ADDRESS (0x903)
+#define HAL_LL_TIM1_CTRLE_REG_ADDRESS (0x904)
+#define HAL_LL_TIM1_INTCTRLA_REG_ADDRESS (0x906)
+#define HAL_LL_TIM1_INTCTRLB_REG_ADDRESS (0x907)
+#define HAL_LL_TIM1_CTRLFCLR_REG_ADDRESS (0x908)
+#define HAL_LL_TIM1_CTRLGCLR_REG_ADDRESS (0x90A)
+#define HAL_LL_TIM1_CTRLGSET_REG_ADDRESS (0x90B)
+#define HAL_LL_TIM1_INTFLAGS_REG_ADDRESS (0x90C)
+#define HAL_LL_TIM1_TEMP_REG_ADDRESS (0x90F)
+#define HAL_LL_TIM1_PERBUF_REG_ADDRESS (0x936)
+#define HAL_LL_TIM1_CCABUF_REG_ADDRESS (0x938)
+#define HAL_LL_TIM1_CCBBUF_REG_ADDRESS (0x93A)
+#define HAL_LL_TIM1_CCCBUF_REG_ADDRESS (0x93C)
+#define HAL_LL_TIM1_CCDBUF_REG_ADDRESS (0x93E)
+#define HAL_LL_TIM2_CTRLA_REG_ADDRESS (0xA00)
+#define HAL_LL_TIM2_CTRLB_REG_ADDRESS (0xA01)
+#define HAL_LL_TIM2_CTRLC_REG_ADDRESS (0xA02)
+#define HAL_LL_TIM2_CTRLD_REG_ADDRESS (0xA03)
+#define HAL_LL_TIM2_CTRLE_REG_ADDRESS (0xA04)
+#define HAL_LL_TIM2_INTCTRLA_REG_ADDRESS (0xA06)
+#define HAL_LL_TIM2_INTCTRLB_REG_ADDRESS (0xA07)
+#define HAL_LL_TIM2_CTRLFCLR_REG_ADDRESS (0xA08)
+#define HAL_LL_TIM2_CTRLFSET_REG_ADDRESS (0xA09)
+#define HAL_LL_TIM2_CTRLGCLR_REG_ADDRESS (0xA0A)
+#define HAL_LL_TIM2_CTRLGSET_REG_ADDRESS (0xA0B)
+#define HAL_LL_TIM2_INTFLAGS_REG_ADDRESS (0xA0C)
+#define HAL_LL_TIM2_TEMP_REG_ADDRESS (0xA0F)
+#define HAL_LL_TIM2_CNT_REG_ADDRESS (0xA20)
+#define HAL_LL_TIM2_PERL_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_PERH_REG_ADDRESS (0xA27)
+#define HAL_LL_TIM2_PER_REG_ADDRESS (0xA26)
+#define HAL_LL_TIM2_CCA_REG_ADDRESS (0xA28)
+#define HAL_LL_TIM2_CCB_REG_ADDRESS (0xA2A)
+#define HAL_LL_TIM2_CCC_REG_ADDRESS (0xA2C)
+#define HAL_LL_TIM2_CCD_REG_ADDRESS (0xA2E)
+#define HAL_LL_TIM2_PERBUF_REG_ADDRESS (0xA36)
+#define HAL_LL_TIM2_CCABUF_REG_ADDRESS (0xA38)
+#define HAL_LL_TIM2_CCBBUF_REG_ADDRESS (0xA3A)
+#define HAL_LL_TIM2_CCCBUF_REG_ADDRESS (0xA3C)
+#define HAL_LL_TIM2_CCDBUF_REG_ADDRESS (0xA3E)
+#define HAL_LL_TIM0_CNT_REG_ADDRESS (0x820)
+#define HAL_LL_TIM0_PERL_REG_ADDRESS (0x826)
+#define HAL_LL_TIM0_PERH_REG_ADDRESS (0x827)
+#define HAL_LL_TIM0_CCA_REG_ADDRESS (0x828)
+#define HAL_LL_TIM0_CCB_REG_ADDRESS (0x82A)
+#define HAL_LL_TIM0_CCC_REG_ADDRESS (0x82C)
+#define HAL_LL_TIM0_CCD_REG_ADDRESS (0x82E)
+#define HAL_LL_TIM1_CNT_REG_ADDRESS (0x920)
+#define HAL_LL_TIM1_PERL_REG_ADDRESS (0x926)
+#define HAL_LL_TIM1_PERH_REG_ADDRESS (0x927)
+#define HAL_LL_TIM1_CCA_REG_ADDRESS (0x928)
+#define HAL_LL_TIM1_CCB_REG_ADDRESS (0x92A)
+#define HAL_LL_TIM1_CCC_REG_ADDRESS (0x92C)
+#define HAL_LL_TIM1_CCD_REG_ADDRESS (0x92E)
+// EOF TIM Register addresses and offsets
+// EOF TIM
+
+// GPIO
+#define __PA0_CN
+#define __PA1_CN
+#define __PA2_CN
+#define __PA3_CN
+#define __PA4_CN
+#define __PA5_CN
+#define __PA6_CN
+#define __PA7_CN
+#define __PB0_CN
+#define __PB1_CN
+#define __PB2_CN
+#define __PB3_CN
+#define __PC0_CN
+#define __PC1_CN
+#define __PC2_CN
+#define __PC3_CN
+#define __PC4_CN
+#define __PC5_CN
+#define __PC6_CN
+#define __PC7_CN
+#define __PD0_CN
+#define __PD1_CN
+#define __PD2_CN
+#define __PD3_CN
+#define __PD4_CN
+#define __PD5_CN
+#define __PD6_CN
+#define __PD7_CN
+#define __PE0_CN
+#define __PE1_CN
+#define __PE2_CN
+#define __PE3_CN
+#define __PR0_CN
+#define __PR1_CN
+
+#define __PORT_A_CN
+#define __PORT_B_CN
+#define __PORT_C_CN
+#define __PORT_D_CN
+#define __PORT_E_CN
+#define __PORT_R_CN
+
+#define PORT_SIZE  (8)
+#define PORT_COUNT (6)
+
+// GPIO Register addresses and offsets
+#define DDRA_REG_ADDRESS (0x600)
+#define PORTA_REG_ADDRESS (0x604)
+#define PINA_REG_ADDRESS (0x608)
+#define DDRB_REG_ADDRESS (0x620)
+#define PORTB_REG_ADDRESS (0x624)
+#define PINB_REG_ADDRESS (0x628)
+#define DDRC_REG_ADDRESS (0x640)
+#define PORTC_REG_ADDRESS (0x644)
+#define PINC_REG_ADDRESS (0x648)
+#define DDRD_REG_ADDRESS (0x660)
+#define PORTD_REG_ADDRESS (0x664)
+#define PIND_REG_ADDRESS (0x668)
+#define DDRE_REG_ADDRESS (0x680)
+#define PORTE_REG_ADDRESS (0x684)
+#define PINE_REG_ADDRESS (0x688)
+#define DDRR_REG_ADDRESS (0x7E0)
+#define PORTR_REG_ADDRESS (0x7E4)
+#define PINR_REG_ADDRESS (0x7E8)
+// REMAP Register addresses
+#define HAL_LL_MODULE_REMAP (true)
+#define PORTA_REMAP_REG_ADDRESS (0x60E)
+#define PORTB_REMAP_REG_ADDRESS (0x62E)
+#define PORTC_REMAP_REG_ADDRESS (0x64E)
+#define PORTD_REMAP_REG_ADDRESS (0x66E)
+#define PORTE_REMAP_REG_ADDRESS (0x68E)
+#define PORTR_REMAP_REG_ADDRESS (0x7EE)
+// EOF GPIO Register addresses and offsets
+// EOF GPIO
+
+// POWER REDUCTION REGISTER
+#define HAL_LL_PRPA_REG_ADDRESS (0x71)
+#define HAL_LL_PRPC_REG_ADDRESS (0x73)
+#define HAL_LL_PRPD_REG_ADDRESS (0x74)
+#define HAL_LL_PRPE_REG_ADDRESS (0x75)
+#define HAL_LL_PRPF_REG_ADDRESS (0x76)
+#define HAL_LL_POWER_REDUCTION (true)
+// EOF POWER REDUCTION REGISTER
+
+// IVT
+#define HAL_LL_USARTC0_RXC_IVT (25)
+#define HAL_LL_USARTC0_DRE_IVT (26)
+#define HAL_LL_USARTC0_TXC_IVT (27)
+#define HAL_LL_USARTD0_RXC_IVT (88)
+#define HAL_LL_USARTD0_DRE_IVT (89)
+#define HAL_LL_USARTD0_TXC_IVT (90)
+// IVT ADDRESSES
+#define HAL_LL_USARTC0_RXC_IVT_ADDRESS (0x32)
+#define HAL_LL_USARTC0_DRE_IVT_ADDRESS (0x34)
+#define HAL_LL_USARTC0_TXC_IVT_ADDRESS (0x36)
+#define HAL_LL_USARTD0_RXC_IVT_ADDRESS (0xB0)
+#define HAL_LL_USARTD0_DRE_IVT_ADDRESS (0xB2)
+#define HAL_LL_USARTD0_TXC_IVT_ADDRESS (0xB4)
+// Programmable multilevel interrupt controller
+#define HAL_LL_PMIC_STATUS_REG_ADDRESS (0xA0)
+#define HAL_LL_PMIC_INTPRI_REG_ADDRESS (0xA1)
+#define HAL_LL_PMIC_CTRL_REG_ADDRESS (0xA2)
+// EOF IVT
+
+#endif // _MCU_DEFINITIONS_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/core/CMakeLists.txt b/targets/avr_8bit/mikroe/core/CMakeLists.txt
new file mode 100644
index 000000000..4e7169ac3
--- /dev/null
+++ b/targets/avr_8bit/mikroe/core/CMakeLists.txt
@@ -0,0 +1,42 @@
+set(hal_ll_core_def_list "")
+string(SUBSTRING ${MCU_NAME} 0 5 MEMAKE_MCU_NAME_FIRST_5)
+string(SUBSTRING ${MCU_NAME} 0 6 MEMAKE_MCU_NAME_FIRST_6)
+
+if (${MCU_NAME} MATCHES "AT")
+    set(hal_ll_core_source "hal_ll_core.c")
+    list(APPEND hal_ll_core_def_list "__avr__")
+else()
+    set(hal_ll_core_def_list "__family_not_supported__")
+endif()
+
+string(LENGTH ${MCU_NAME} MCU_NAME_LENGTH)
+MATH(EXPR BEGIN_INDEX "${MCU_NAME_LENGTH}-3")
+string(SUBSTRING ${MCU_NAME} ${BEGIN_INDEX} 3 MCU_NAME_LAST_3)
+
+mikrosdk_add_library(lib_hal_ll_core MikroSDK.HalLowLevelCore
+    src/${hal_ll_core_source}
+
+    include/hal_ll_core_defines.h
+    include/hal_ll_core_port.h
+    include/hal_ll_core.h
+)
+
+target_compile_definitions(lib_hal_ll_core
+    PUBLIC
+        ${hal_ll_core_def_list}
+)
+
+target_link_libraries(lib_hal_ll_core PUBLIC
+    MikroC.Core
+    MikroSDK.HalLowLevelCommon
+)
+
+target_include_directories(lib_hal_ll_core
+PRIVATE
+    include
+INTERFACE
+    $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/include>
+    $<INSTALL_INTERFACE:include>
+)
+
+mikrosdk_install(MikroSDK.HalLowLevelCore)
diff --git a/targets/avr_8bit/mikroe/core/include/hal_ll_core.h b/targets/avr_8bit/mikroe/core/include/hal_ll_core.h
new file mode 100644
index 000000000..83b056be0
--- /dev/null
+++ b/targets/avr_8bit/mikroe/core/include/hal_ll_core.h
@@ -0,0 +1,100 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_core.h
+ * @brief This file contains all function prototypes for the low level CORE library functions.
+ *        These functions are chip specific.
+ */
+
+#ifndef _HAL_LL_CORE_H_
+#define _HAL_LL_CORE_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "hal_ll_core_defines.h"
+
+/**
+ * @brief  Enables interrupts.
+ *
+ * Enables interrupts on global level.
+ *
+ * @return void None.
+ */
+void hal_ll_core_enable_interrupts(void);
+
+/**
+ * @brief  Disables interrupts.
+ *
+ * Disables interrupts on global level.
+ *
+ * @return void None.
+ */
+void hal_ll_core_disable_interrupts(void);
+
+/**
+ * @brief  Enables selected IRQ.
+ *
+ * Registers interrupt on hardware level and enables
+ * it.
+ *
+ * @param[in] IRQn Chip specific IRQ number.
+ * @return void None.
+ */
+void hal_ll_core_enable_irq(uint8_t IRQn);
+
+/**
+ * @brief  Disables selected IRQ.
+ *
+ * Disables previously registered interrupt
+ * handler..
+ *
+ * @param[in] IRQn Chip specific IRQ number.
+ * @return void None.
+ */
+void hal_ll_core_disable_irq(uint8_t IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_CORE_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/core/include/hal_ll_core_defines.h b/targets/avr_8bit/mikroe/core/include/hal_ll_core_defines.h
new file mode 100644
index 000000000..e0c5bf8eb
--- /dev/null
+++ b/targets/avr_8bit/mikroe/core/include/hal_ll_core_defines.h
@@ -0,0 +1,72 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_core_defines.h
+ * @brief Core specific defines and enums used for dsPIC chips.
+ */
+
+#ifndef _HAL_LL_CORE_DEFINES_H_
+#define _HAL_LL_CORE_DEFINES_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include <stdint.h>
+
+#if defined (__MIKROC_AI_FOR_AVR__)
+#define MIKROC_IV(x) org x
+#else
+#define MIKROC_IV(x)
+#endif
+
+#define __weak __attribute__((weak))
+
+#define hal_ll_core_enable_int_asm asm SEI
+#define hal_ll_core_disable_int_asm asm CLI
+
+// Interrupt vectors (program addresses).
+#define HAL_LL_CORE_IRQ_NOT_SUPPORTED (0x0038)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_CORE_DEFINES_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/core/include/hal_ll_core_port.h b/targets/avr_8bit/mikroe/core/include/hal_ll_core_port.h
new file mode 100644
index 000000000..b60f195cb
--- /dev/null
+++ b/targets/avr_8bit/mikroe/core/include/hal_ll_core_port.h
@@ -0,0 +1,97 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file  hal_ll_core_port.h
+ * @brief This file contains all function prototypes for the low level ported CORE library functions.
+ *        These functions are chip specific.
+ */
+
+#ifndef _HAL_LL_CORE_PORT_H_
+#define _HAL_LL_CORE_PORT_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "stdint.h"
+
+/**
+ * @brief  Enables selected IRQ.
+ *
+ * Registers interrupt on hardware level and enables
+ * it.
+ *
+ * @param[in] IRQn Chip specific IRQ number.
+ * @return void None.
+ */
+void hal_ll_core_port_enable_irq( uint8_t IRQn );
+
+/**
+ * @brief  Disables selected IRQ.
+ *
+ * Disables previously registered interrupt
+ * handler..
+ *
+ * @param[in] IRQn Chip specific IRQ number.
+ * @return void None.
+ */
+void hal_ll_core_port_disable_irq( uint8_t IRQn );
+
+/**
+ * @brief  Sets IRQ priority level.
+ *
+ * Sets specified IRQ priority on
+ * hardware level.
+ *
+ * @param[in] IRQn Chip specific IRQ number.
+ *
+ * One of predefined hal_ll_core_irq_priority_levels.
+ * Take into consideration that this is chip specific.
+ *
+ * @return void None.
+ */
+void hal_ll_core_port_set_priority_irq( uint8_t IRQn, uint8_t IRQn_priority );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HAL_LL_CORE_PORT_H_
+// ------------------------------------------------------------------------- END
diff --git a/targets/avr_8bit/mikroe/core/src/hal_ll_core.c b/targets/avr_8bit/mikroe/core/src/hal_ll_core.c
new file mode 100644
index 000000000..eaa436137
--- /dev/null
+++ b/targets/avr_8bit/mikroe/core/src/hal_ll_core.c
@@ -0,0 +1,132 @@
+/****************************************************************************
+**
+** Copyright (C) 2022 MikroElektronika d.o.o.
+** Contact: https://www.mikroe.com/contact
+**
+** This file is part of the mikroSDK package
+**
+** Commercial License Usage
+**
+** Licensees holding valid commercial NECTO compilers AI licenses may use this
+** file in accordance with the commercial license agreement provided with the
+** Software or, alternatively, in accordance with the terms contained in
+** a written agreement between you and The MikroElektronika Company.
+** For licensing terms and conditions see
+** https://www.mikroe.com/legal/software-license-agreement.
+** For further information use the contact form at
+** https://www.mikroe.com/contact.
+**
+**
+** GNU Lesser General Public License Usage
+**
+** Alternatively, this file may be used for
+** non-commercial projects under the terms of the GNU Lesser
+** General Public License version 3 as published by the Free Software
+** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
+**
+** The above copyright notice and this permission notice shall be
+** included in all copies or substantial portions of the Software.
+**
+** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
+** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+**
+****************************************************************************/
+/*!
+ * @file hal_ll_core.c
+ * @brief CORE HAL LOW LEVEL layer implementation.
+ */
+
+#include "mcu_definitions.h"
+#include "hal_ll_core_defines.h"
+#include "hal_ll_bit_control.h"
+
+void hal_ll_core_enable_interrupts(void) {
+    hal_ll_core_enable_int_asm;
+}
+
+void hal_ll_core_disable_interrupts(void) {
+    hal_ll_core_disable_int_asm;
+}
+
+void hal_ll_core_enable_irq(uint8_t IRQn) {
+    if ( IRQn >= HAL_LL_CORE_IRQ_NOT_SUPPORTED ) {
+        return;
+    #ifdef HAL_LL_USART0_UCSR0B_REG_ADDRESS
+    } else if ( IRQn >= HAL_LL_USART0_TX_IVT_ADDRESS ) {
+        set_reg_bit(HAL_LL_USART0_UCSR0B_REG_ADDRESS, 6);
+    } else if ( IRQn >= HAL_LL_USART0_UDRE_IVT_ADDRESS ) {
+        set_reg_bit(HAL_LL_USART0_UCSR0B_REG_ADDRESS, 5);
+    } else if ( IRQn >= HAL_LL_USART0_RX_IVT_ADDRESS ) {
+        set_reg_bit(HAL_LL_USART0_UCSR0B_REG_ADDRESS, 7);
+    #endif
+    #ifdef HAL_LL_USART1_UCSR1B_REG_ADDRESS
+    } else if ( IRQn >= HAL_LL_USART1_TX_IVT_ADDRESS ) {
+        set_reg_bit(HAL_LL_USART1_UCSR1B_REG_ADDRESS, 6);
+    } else if ( IRQn >= HAL_LL_USART1_UDRE_IVT_ADDRESS ) {
+        set_reg_bit(HAL_LL_USART1_UCSR1B_REG_ADDRESS, 5);
+    } else if ( IRQn >= HAL_LL_USART1_RX_IVT_ADDRESS ) {
+        set_reg_bit(HAL_LL_USART1_UCSR1B_REG_ADDRESS, 7);
+    #endif
+    #ifdef HAL_LL_USART2_UCSR2B_REG_ADDRESS
+    } else if ( IRQn >= HAL_LL_USART2_TX_IVT_ADDRESS ) {
+        set_reg_bit(HAL_LL_USART2_UCSR2B_REG_ADDRESS, 6);
+    } else if ( IRQn >= HAL_LL_USART2_UDRE_IVT_ADDRESS ) {
+        set_reg_bit(HAL_LL_USART2_UCSR2B_REG_ADDRESS, 5);
+    } else if ( IRQn >= HAL_LL_USART2_RX_IVT_ADDRESS ) {
+        set_reg_bit(HAL_LL_USART2_UCSR2B_REG_ADDRESS, 7);
+    #endif
+    #ifdef HAL_LL_USART3_UCSR3B_REG_ADDRESS
+    } else if ( IRQn >= HAL_LL_USART3_TX_IVT_ADDRESS ) {
+        set_reg_bit(HAL_LL_USART3_UCSR3B_REG_ADDRESS, 6);
+    } else if ( IRQn >= HAL_LL_USART3_UDRE_IVT_ADDRESS ) {
+        set_reg_bit(HAL_LL_USART3_UCSR3B_REG_ADDRESS, 5);
+    } else if ( IRQn >= HAL_LL_USART3_RX_IVT_ADDRESS ) {
+        set_reg_bit(HAL_LL_USART3_UCSR3B_REG_ADDRESS, 7);
+    #endif
+    }
+}
+
+void hal_ll_core_disable_irq(uint8_t IRQn) {
+    if ( IRQn >= HAL_LL_CORE_IRQ_NOT_SUPPORTED ) {
+        return;
+    #ifdef HAL_LL_USART0_UCSR0B_REG_ADDRESS
+    } else if ( IRQn >= HAL_LL_USART0_TX_IVT_ADDRESS ) {
+        clear_reg_bit(HAL_LL_USART0_UCSR0B_REG_ADDRESS, 6);
+    } else if ( IRQn >= HAL_LL_USART0_UDRE_IVT_ADDRESS ) {
+        clear_reg_bit(HAL_LL_USART0_UCSR0B_REG_ADDRESS, 5);
+    } else if ( IRQn >= HAL_LL_USART0_RX_IVT_ADDRESS ) {
+        clear_reg_bit(HAL_LL_USART0_UCSR0B_REG_ADDRESS, 7);
+    #endif
+    #ifdef HAL_LL_USART1_UCSR1B_REG_ADDRESS
+    } else if ( IRQn >= HAL_LL_USART1_TX_IVT_ADDRESS ) {
+        clear_reg_bit(HAL_LL_USART1_UCSR1B_REG_ADDRESS, 6);
+    } else if ( IRQn >= HAL_LL_USART1_UDRE_IVT_ADDRESS ) {
+        clear_reg_bit(HAL_LL_USART1_UCSR1B_REG_ADDRESS, 5);
+    } else if ( IRQn >= HAL_LL_USART1_RX_IVT_ADDRESS ) {
+        clear_reg_bit(HAL_LL_USART1_UCSR1B_REG_ADDRESS, 7);
+    #endif
+    #ifdef HAL_LL_USART2_UCSR2B_REG_ADDRESS
+    } else if ( IRQn >= HAL_LL_USART2_TX_IVT_ADDRESS ) {
+        clear_reg_bit(HAL_LL_USART2_UCSR2B_REG_ADDRESS, 6);
+    } else if ( IRQn >= HAL_LL_USART2_UDRE_IVT_ADDRESS ) {
+        clear_reg_bit(HAL_LL_USART2_UCSR2B_REG_ADDRESS, 5);
+    } else if ( IRQn >= HAL_LL_USART2_RX_IVT_ADDRESS ) {
+        clear_reg_bit(HAL_LL_USART2_UCSR2B_REG_ADDRESS, 7);
+    #endif
+    #ifdef HAL_LL_USART3_UCSR3B_REG_ADDRESS
+    } else if ( IRQn >= HAL_LL_USART3_TX_IVT_ADDRESS ) {
+        clear_reg_bit(HAL_LL_USART3_UCSR3B_REG_ADDRESS, 6);
+    } else if ( IRQn >= HAL_LL_USART3_UDRE_IVT_ADDRESS ) {
+        clear_reg_bit(HAL_LL_USART3_UCSR3B_REG_ADDRESS, 5);
+    } else if ( IRQn >= HAL_LL_USART3_RX_IVT_ADDRESS ) {
+        clear_reg_bit(HAL_LL_USART3_UCSR3B_REG_ADDRESS, 7);
+    #endif
+    }
+}
+
+// ------------------------------------------------------------------------- END
diff --git a/targets/pic_8bit/mikroe/CMakeLists.txt b/targets/pic_8bit/mikroe/CMakeLists.txt
index ad75670b0..9562839da 100644
--- a/targets/pic_8bit/mikroe/CMakeLists.txt
+++ b/targets/pic_8bit/mikroe/CMakeLists.txt
@@ -1,6 +1,3 @@
 add_subdirectory(common)
 add_subdirectory(core)
 add_subdirectory(pic18)
-    # common
-    # core
-# }
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F25K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F25K42/mcu_definitions.h
index be28a4a6e..5104b451f 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F25K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F25K42/mcu_definitions.h
@@ -479,6 +479,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F26K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F26K42/mcu_definitions.h
index be28a4a6e..5104b451f 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F26K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F26K42/mcu_definitions.h
@@ -479,6 +479,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F27K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F27K42/mcu_definitions.h
index be28a4a6e..5104b451f 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F27K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F27K42/mcu_definitions.h
@@ -479,6 +479,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F45K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F45K42/mcu_definitions.h
index 1504a89fd..d275cfbd2 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F45K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F45K42/mcu_definitions.h
@@ -518,6 +518,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F46K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F46K42/mcu_definitions.h
index 1504a89fd..d275cfbd2 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F46K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F46K42/mcu_definitions.h
@@ -518,6 +518,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F47K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F47K42/mcu_definitions.h
index 1504a89fd..d275cfbd2 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F47K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F47K42/mcu_definitions.h
@@ -518,6 +518,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F55K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F55K42/mcu_definitions.h
index fc86f1ad3..587d38b10 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F55K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F55K42/mcu_definitions.h
@@ -547,6 +547,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F56K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F56K42/mcu_definitions.h
index fc86f1ad3..587d38b10 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F56K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F56K42/mcu_definitions.h
@@ -547,6 +547,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F57K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F57K42/mcu_definitions.h
index fc86f1ad3..587d38b10 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F57K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F57K42/mcu_definitions.h
@@ -547,6 +547,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F57Q43/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F57Q43/mcu_definitions.h
index abdabdf2b..6247bced7 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F57Q43/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F57Q43/mcu_definitions.h
@@ -663,6 +663,7 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x297U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x28EU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x28FU
 #define HAL_LL_I2C1CLK_ADDRESS 0x29CU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F65J94/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F65J94/mcu_definitions.h
index ba97ac443..2cae97279 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F65J94/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F65J94/mcu_definitions.h
@@ -53,30 +53,30 @@
 #define HAL_LL_RA2_AN2_ANCON1 2
 #define HAL_LL_RA3_AN3_ANCON1_BIT 3
 #define HAL_LL_RA3_AN3_ANCON1 3
-#define HAL_LL_RA4_AN6_ANCON1_BIT 4
-#define HAL_LL_RA4_AN6_ANCON1 6
-#define HAL_LL_RA5_AN4_ANCON1_BIT 5
-#define HAL_LL_RA5_AN4_ANCON1 4
-#define HAL_LL_RC2_AN9_ANCON2_BIT 1
-#define HAL_LL_RC2_AN9_ANCON2 9
-#define HAL_LL_RF2_AN7_ANCON1_BIT 6
-#define HAL_LL_RF2_AN7_ANCON1 7
-#define HAL_LL_RF5_AN10_ANCON2_BIT 1
-#define HAL_LL_RF5_AN10_ANCON2 10
-#define HAL_LL_RF6_AN11_ANCON2_BIT 2
-#define HAL_LL_RF6_AN11_ANCON2 11
-#define HAL_LL_RF7_AN5_ANCON1_BIT 5
-#define HAL_LL_RF7_AN5_ANCON1 5
-#define HAL_LL_RG0_AN8_ANCON2_BIT 0
-#define HAL_LL_RG0_AN8_ANCON2 8
-#define HAL_LL_RG1_AN19_ANCON3_BIT 3
-#define HAL_LL_RG1_AN19_ANCON3 19
-#define HAL_LL_RG2_AN18_ANCON3_BIT 2
-#define HAL_LL_RG2_AN18_ANCON3 18
-#define HAL_LL_RG3_AN17_ANCON3_BIT 1
-#define HAL_LL_RG3_AN17_ANCON3 17
-#define HAL_LL_RG4_AN16_ANCON2_BIT 7
-#define HAL_LL_RG4_AN16_ANCON2 16
+#define HAL_LL_RA4_AN4_ANCON1_BIT 4
+#define HAL_LL_RA4_AN4_ANCON1 4
+#define HAL_LL_RA5_AN5_ANCON1_BIT 5
+#define HAL_LL_RA5_AN5_ANCON1 5
+#define HAL_LL_RF2_AN6_ANCON1_BIT 6
+#define HAL_LL_RF2_AN6_ANCON1 6
+#define HAL_LL_RG0_AN7_ANCON1_BIT 7
+#define HAL_LL_RG0_AN7_ANCON1 7
+#define HAL_LL_RC2_AN8_ANCON2_BIT 0
+#define HAL_LL_RC2_AN8_ANCON2 8
+#define HAL_LL_RF5_AN9_ANCON2_BIT 1
+#define HAL_LL_RF5_AN9_ANCON2 9
+#define HAL_LL_RF6_AN10_ANCON2_BIT 2
+#define HAL_LL_RF6_AN10_ANCON2 10
+#define HAL_LL_RF7_AN11_ANCON2_BIT 3
+#define HAL_LL_RF7_AN11_ANCON2 11
+#define HAL_LL_RG1_AN12_ANCON2_BIT 4
+#define HAL_LL_RG1_AN12_ANCON2 12
+#define HAL_LL_RG2_AN13_ANCON2_BIT 5
+#define HAL_LL_RG2_AN13_ANCON2 13
+#define HAL_LL_RG3_AN14_ANCON2_BIT 6
+#define HAL_LL_RG3_AN14_ANCON2 14
+#define HAL_LL_RG4_AN15_ANCON2_BIT 7
+#define HAL_LL_RG4_AN15_ANCON2 15
 
 
 #define HAL_LL_ADCBUF0_ADDRESS 0xFC2U
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F66J94/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F66J94/mcu_definitions.h
index ba97ac443..2cae97279 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F66J94/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F66J94/mcu_definitions.h
@@ -53,30 +53,30 @@
 #define HAL_LL_RA2_AN2_ANCON1 2
 #define HAL_LL_RA3_AN3_ANCON1_BIT 3
 #define HAL_LL_RA3_AN3_ANCON1 3
-#define HAL_LL_RA4_AN6_ANCON1_BIT 4
-#define HAL_LL_RA4_AN6_ANCON1 6
-#define HAL_LL_RA5_AN4_ANCON1_BIT 5
-#define HAL_LL_RA5_AN4_ANCON1 4
-#define HAL_LL_RC2_AN9_ANCON2_BIT 1
-#define HAL_LL_RC2_AN9_ANCON2 9
-#define HAL_LL_RF2_AN7_ANCON1_BIT 6
-#define HAL_LL_RF2_AN7_ANCON1 7
-#define HAL_LL_RF5_AN10_ANCON2_BIT 1
-#define HAL_LL_RF5_AN10_ANCON2 10
-#define HAL_LL_RF6_AN11_ANCON2_BIT 2
-#define HAL_LL_RF6_AN11_ANCON2 11
-#define HAL_LL_RF7_AN5_ANCON1_BIT 5
-#define HAL_LL_RF7_AN5_ANCON1 5
-#define HAL_LL_RG0_AN8_ANCON2_BIT 0
-#define HAL_LL_RG0_AN8_ANCON2 8
-#define HAL_LL_RG1_AN19_ANCON3_BIT 3
-#define HAL_LL_RG1_AN19_ANCON3 19
-#define HAL_LL_RG2_AN18_ANCON3_BIT 2
-#define HAL_LL_RG2_AN18_ANCON3 18
-#define HAL_LL_RG3_AN17_ANCON3_BIT 1
-#define HAL_LL_RG3_AN17_ANCON3 17
-#define HAL_LL_RG4_AN16_ANCON2_BIT 7
-#define HAL_LL_RG4_AN16_ANCON2 16
+#define HAL_LL_RA4_AN4_ANCON1_BIT 4
+#define HAL_LL_RA4_AN4_ANCON1 4
+#define HAL_LL_RA5_AN5_ANCON1_BIT 5
+#define HAL_LL_RA5_AN5_ANCON1 5
+#define HAL_LL_RF2_AN6_ANCON1_BIT 6
+#define HAL_LL_RF2_AN6_ANCON1 6
+#define HAL_LL_RG0_AN7_ANCON1_BIT 7
+#define HAL_LL_RG0_AN7_ANCON1 7
+#define HAL_LL_RC2_AN8_ANCON2_BIT 0
+#define HAL_LL_RC2_AN8_ANCON2 8
+#define HAL_LL_RF5_AN9_ANCON2_BIT 1
+#define HAL_LL_RF5_AN9_ANCON2 9
+#define HAL_LL_RF6_AN10_ANCON2_BIT 2
+#define HAL_LL_RF6_AN10_ANCON2 10
+#define HAL_LL_RF7_AN11_ANCON2_BIT 3
+#define HAL_LL_RF7_AN11_ANCON2 11
+#define HAL_LL_RG1_AN12_ANCON2_BIT 4
+#define HAL_LL_RG1_AN12_ANCON2 12
+#define HAL_LL_RG2_AN13_ANCON2_BIT 5
+#define HAL_LL_RG2_AN13_ANCON2 13
+#define HAL_LL_RG3_AN14_ANCON2_BIT 6
+#define HAL_LL_RG3_AN14_ANCON2 14
+#define HAL_LL_RG4_AN15_ANCON2_BIT 7
+#define HAL_LL_RG4_AN15_ANCON2 15
 
 
 #define HAL_LL_ADCBUF0_ADDRESS 0xFC2U
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F67J94/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F67J94/mcu_definitions.h
index ba97ac443..2cae97279 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F67J94/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F67J94/mcu_definitions.h
@@ -53,30 +53,30 @@
 #define HAL_LL_RA2_AN2_ANCON1 2
 #define HAL_LL_RA3_AN3_ANCON1_BIT 3
 #define HAL_LL_RA3_AN3_ANCON1 3
-#define HAL_LL_RA4_AN6_ANCON1_BIT 4
-#define HAL_LL_RA4_AN6_ANCON1 6
-#define HAL_LL_RA5_AN4_ANCON1_BIT 5
-#define HAL_LL_RA5_AN4_ANCON1 4
-#define HAL_LL_RC2_AN9_ANCON2_BIT 1
-#define HAL_LL_RC2_AN9_ANCON2 9
-#define HAL_LL_RF2_AN7_ANCON1_BIT 6
-#define HAL_LL_RF2_AN7_ANCON1 7
-#define HAL_LL_RF5_AN10_ANCON2_BIT 1
-#define HAL_LL_RF5_AN10_ANCON2 10
-#define HAL_LL_RF6_AN11_ANCON2_BIT 2
-#define HAL_LL_RF6_AN11_ANCON2 11
-#define HAL_LL_RF7_AN5_ANCON1_BIT 5
-#define HAL_LL_RF7_AN5_ANCON1 5
-#define HAL_LL_RG0_AN8_ANCON2_BIT 0
-#define HAL_LL_RG0_AN8_ANCON2 8
-#define HAL_LL_RG1_AN19_ANCON3_BIT 3
-#define HAL_LL_RG1_AN19_ANCON3 19
-#define HAL_LL_RG2_AN18_ANCON3_BIT 2
-#define HAL_LL_RG2_AN18_ANCON3 18
-#define HAL_LL_RG3_AN17_ANCON3_BIT 1
-#define HAL_LL_RG3_AN17_ANCON3 17
-#define HAL_LL_RG4_AN16_ANCON2_BIT 7
-#define HAL_LL_RG4_AN16_ANCON2 16
+#define HAL_LL_RA4_AN4_ANCON1_BIT 4
+#define HAL_LL_RA4_AN4_ANCON1 4
+#define HAL_LL_RA5_AN5_ANCON1_BIT 5
+#define HAL_LL_RA5_AN5_ANCON1 5
+#define HAL_LL_RF2_AN6_ANCON1_BIT 6
+#define HAL_LL_RF2_AN6_ANCON1 6
+#define HAL_LL_RG0_AN7_ANCON1_BIT 7
+#define HAL_LL_RG0_AN7_ANCON1 7
+#define HAL_LL_RC2_AN8_ANCON2_BIT 0
+#define HAL_LL_RC2_AN8_ANCON2 8
+#define HAL_LL_RF5_AN9_ANCON2_BIT 1
+#define HAL_LL_RF5_AN9_ANCON2 9
+#define HAL_LL_RF6_AN10_ANCON2_BIT 2
+#define HAL_LL_RF6_AN10_ANCON2 10
+#define HAL_LL_RF7_AN11_ANCON2_BIT 3
+#define HAL_LL_RF7_AN11_ANCON2 11
+#define HAL_LL_RG1_AN12_ANCON2_BIT 4
+#define HAL_LL_RG1_AN12_ANCON2 12
+#define HAL_LL_RG2_AN13_ANCON2_BIT 5
+#define HAL_LL_RG2_AN13_ANCON2 13
+#define HAL_LL_RG3_AN14_ANCON2_BIT 6
+#define HAL_LL_RG3_AN14_ANCON2 14
+#define HAL_LL_RG4_AN15_ANCON2_BIT 7
+#define HAL_LL_RG4_AN15_ANCON2 15
 
 
 #define HAL_LL_ADCBUF0_ADDRESS 0xFC2U
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F85J94/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F85J94/mcu_definitions.h
index c3e57c5a4..ccdeb9b6d 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F85J94/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F85J94/mcu_definitions.h
@@ -53,46 +53,46 @@
 #define HAL_LL_RA2_AN2_ANCON1 2
 #define HAL_LL_RA3_AN3_ANCON1_BIT 3
 #define HAL_LL_RA3_AN3_ANCON1 3
-#define HAL_LL_RA4_AN6_ANCON1_BIT 4
-#define HAL_LL_RA4_AN6_ANCON1 6
-#define HAL_LL_RA5_AN4_ANCON1_BIT 5
-#define HAL_LL_RA5_AN4_ANCON1 4
-#define HAL_LL_RC2_AN9_ANCON2_BIT 1
-#define HAL_LL_RC2_AN9_ANCON2 9
-#define HAL_LL_RF2_AN7_ANCON1_BIT 6
-#define HAL_LL_RF2_AN7_ANCON1 7
-#define HAL_LL_RF5_AN10_ANCON2_BIT 1
-#define HAL_LL_RF5_AN10_ANCON2 10
-#define HAL_LL_RF6_AN11_ANCON2_BIT 2
-#define HAL_LL_RF6_AN11_ANCON2 11
-#define HAL_LL_RF7_AN5_ANCON1_BIT 5
-#define HAL_LL_RF7_AN5_ANCON1 5
-#define HAL_LL_RG0_AN8_ANCON2_BIT 0
-#define HAL_LL_RG0_AN8_ANCON2 8
-#define HAL_LL_RG1_AN19_ANCON3_BIT 3
-#define HAL_LL_RG1_AN19_ANCON3 19
-#define HAL_LL_RG2_AN18_ANCON3_BIT 2
-#define HAL_LL_RG2_AN18_ANCON3 18
-#define HAL_LL_RG3_AN17_ANCON3_BIT 1
-#define HAL_LL_RG3_AN17_ANCON3 17
-#define HAL_LL_RG4_AN16_ANCON2_BIT 7
-#define HAL_LL_RG4_AN16_ANCON2 16
-#define HAL_LL_RH0_AN23_ANCON3_BIT 7
-#define HAL_LL_RH0_AN23_ANCON3 23
-#define HAL_LL_RH1_AN22_ANCON3_BIT 6
-#define HAL_LL_RH1_AN22_ANCON3 22
-#define HAL_LL_RH2_AN21_ANCON3_BIT 5
-#define HAL_LL_RH2_AN21_ANCON3 21
-#define HAL_LL_RH3_AN20_ANCON3_BIT 4
-#define HAL_LL_RH3_AN20_ANCON3 20
-#define HAL_LL_RH4_AN12_ANCON2_BIT 4
-#define HAL_LL_RH4_AN12_ANCON2 12
-#define HAL_LL_RH5_AN13_ANCON2_BIT 5
-#define HAL_LL_RH5_AN13_ANCON2 13
-#define HAL_LL_RH6_AN14_ANCON2_BIT 6
-#define HAL_LL_RH6_AN14_ANCON2 14
-#define HAL_LL_RH7_AN15_ANCON2_BIT 7
-#define HAL_LL_RH7_AN15_ANCON2 15
+#define HAL_LL_RA4_AN4_ANCON1_BIT 4
+#define HAL_LL_RA4_AN4_ANCON1 4
+#define HAL_LL_RA5_AN5_ANCON1_BIT 5
+#define HAL_LL_RA5_AN5_ANCON1 5
+#define HAL_LL_RF2_AN6_ANCON1_BIT 6
+#define HAL_LL_RF2_AN6_ANCON1 6
+#define HAL_LL_RG0_AN7_ANCON1_BIT 7
+#define HAL_LL_RG0_AN7_ANCON1 7
+#define HAL_LL_RC2_AN8_ANCON2_BIT 0
+#define HAL_LL_RC2_AN8_ANCON2 8
+#define HAL_LL_RF5_AN9_ANCON2_BIT 1
+#define HAL_LL_RF5_AN9_ANCON2 9
+#define HAL_LL_RF6_AN10_ANCON2_BIT 2
+#define HAL_LL_RF6_AN10_ANCON2 10
+#define HAL_LL_RF7_AN11_ANCON2_BIT 3
+#define HAL_LL_RF7_AN11_ANCON2 11
+#define HAL_LL_RG1_AN12_ANCON2_BIT 4
+#define HAL_LL_RG1_AN12_ANCON2 12
+#define HAL_LL_RG2_AN13_ANCON2_BIT 5
+#define HAL_LL_RG2_AN13_ANCON2 13
+#define HAL_LL_RG3_AN14_ANCON2_BIT 6
+#define HAL_LL_RG3_AN14_ANCON2 14
+#define HAL_LL_RG4_AN15_ANCON2_BIT 7
+#define HAL_LL_RG4_AN15_ANCON2 15
+#define HAL_LL_RH0_AN16_ANCON3_BIT 0
+#define HAL_LL_RH0_AN16_ANCON3 16
+#define HAL_LL_RH1_AN17_ANCON3_BIT 1
+#define HAL_LL_RH1_AN17_ANCON3 17
+#define HAL_LL_RH2_AN18_ANCON3_BIT 2
+#define HAL_LL_RH2_AN18_ANCON3 18
+#define HAL_LL_RH3_AN19_ANCON3_BIT 3
+#define HAL_LL_RH3_AN19_ANCON3 19
+#define HAL_LL_RH4_AN20_ANCON3_BIT 4
+#define HAL_LL_RH4_AN20_ANCON3 20
+#define HAL_LL_RH5_AN21_ANCON3_BIT 5
+#define HAL_LL_RH5_AN21_ANCON3 21
+#define HAL_LL_RH6_AN22_ANCON3_BIT 6
+#define HAL_LL_RH6_AN22_ANCON3 22
+#define HAL_LL_RH7_AN23_ANCON3_BIT 7
+#define HAL_LL_RH7_AN23_ANCON3 23
 
 
 #define HAL_LL_ADCBUF0_ADDRESS 0xFC2U
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F86J94/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F86J94/mcu_definitions.h
index c3e57c5a4..ccdeb9b6d 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F86J94/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F86J94/mcu_definitions.h
@@ -53,46 +53,46 @@
 #define HAL_LL_RA2_AN2_ANCON1 2
 #define HAL_LL_RA3_AN3_ANCON1_BIT 3
 #define HAL_LL_RA3_AN3_ANCON1 3
-#define HAL_LL_RA4_AN6_ANCON1_BIT 4
-#define HAL_LL_RA4_AN6_ANCON1 6
-#define HAL_LL_RA5_AN4_ANCON1_BIT 5
-#define HAL_LL_RA5_AN4_ANCON1 4
-#define HAL_LL_RC2_AN9_ANCON2_BIT 1
-#define HAL_LL_RC2_AN9_ANCON2 9
-#define HAL_LL_RF2_AN7_ANCON1_BIT 6
-#define HAL_LL_RF2_AN7_ANCON1 7
-#define HAL_LL_RF5_AN10_ANCON2_BIT 1
-#define HAL_LL_RF5_AN10_ANCON2 10
-#define HAL_LL_RF6_AN11_ANCON2_BIT 2
-#define HAL_LL_RF6_AN11_ANCON2 11
-#define HAL_LL_RF7_AN5_ANCON1_BIT 5
-#define HAL_LL_RF7_AN5_ANCON1 5
-#define HAL_LL_RG0_AN8_ANCON2_BIT 0
-#define HAL_LL_RG0_AN8_ANCON2 8
-#define HAL_LL_RG1_AN19_ANCON3_BIT 3
-#define HAL_LL_RG1_AN19_ANCON3 19
-#define HAL_LL_RG2_AN18_ANCON3_BIT 2
-#define HAL_LL_RG2_AN18_ANCON3 18
-#define HAL_LL_RG3_AN17_ANCON3_BIT 1
-#define HAL_LL_RG3_AN17_ANCON3 17
-#define HAL_LL_RG4_AN16_ANCON2_BIT 7
-#define HAL_LL_RG4_AN16_ANCON2 16
-#define HAL_LL_RH0_AN23_ANCON3_BIT 7
-#define HAL_LL_RH0_AN23_ANCON3 23
-#define HAL_LL_RH1_AN22_ANCON3_BIT 6
-#define HAL_LL_RH1_AN22_ANCON3 22
-#define HAL_LL_RH2_AN21_ANCON3_BIT 5
-#define HAL_LL_RH2_AN21_ANCON3 21
-#define HAL_LL_RH3_AN20_ANCON3_BIT 4
-#define HAL_LL_RH3_AN20_ANCON3 20
-#define HAL_LL_RH4_AN12_ANCON2_BIT 4
-#define HAL_LL_RH4_AN12_ANCON2 12
-#define HAL_LL_RH5_AN13_ANCON2_BIT 5
-#define HAL_LL_RH5_AN13_ANCON2 13
-#define HAL_LL_RH6_AN14_ANCON2_BIT 6
-#define HAL_LL_RH6_AN14_ANCON2 14
-#define HAL_LL_RH7_AN15_ANCON2_BIT 7
-#define HAL_LL_RH7_AN15_ANCON2 15
+#define HAL_LL_RA4_AN4_ANCON1_BIT 4
+#define HAL_LL_RA4_AN4_ANCON1 4
+#define HAL_LL_RA5_AN5_ANCON1_BIT 5
+#define HAL_LL_RA5_AN5_ANCON1 5
+#define HAL_LL_RF2_AN6_ANCON1_BIT 6
+#define HAL_LL_RF2_AN6_ANCON1 6
+#define HAL_LL_RG0_AN7_ANCON1_BIT 7
+#define HAL_LL_RG0_AN7_ANCON1 7
+#define HAL_LL_RC2_AN8_ANCON2_BIT 0
+#define HAL_LL_RC2_AN8_ANCON2 8
+#define HAL_LL_RF5_AN9_ANCON2_BIT 1
+#define HAL_LL_RF5_AN9_ANCON2 9
+#define HAL_LL_RF6_AN10_ANCON2_BIT 2
+#define HAL_LL_RF6_AN10_ANCON2 10
+#define HAL_LL_RF7_AN11_ANCON2_BIT 3
+#define HAL_LL_RF7_AN11_ANCON2 11
+#define HAL_LL_RG1_AN12_ANCON2_BIT 4
+#define HAL_LL_RG1_AN12_ANCON2 12
+#define HAL_LL_RG2_AN13_ANCON2_BIT 5
+#define HAL_LL_RG2_AN13_ANCON2 13
+#define HAL_LL_RG3_AN14_ANCON2_BIT 6
+#define HAL_LL_RG3_AN14_ANCON2 14
+#define HAL_LL_RG4_AN15_ANCON2_BIT 7
+#define HAL_LL_RG4_AN15_ANCON2 15
+#define HAL_LL_RH0_AN16_ANCON3_BIT 0
+#define HAL_LL_RH0_AN16_ANCON3 16
+#define HAL_LL_RH1_AN17_ANCON3_BIT 1
+#define HAL_LL_RH1_AN17_ANCON3 17
+#define HAL_LL_RH2_AN18_ANCON3_BIT 2
+#define HAL_LL_RH2_AN18_ANCON3 18
+#define HAL_LL_RH3_AN19_ANCON3_BIT 3
+#define HAL_LL_RH3_AN19_ANCON3 19
+#define HAL_LL_RH4_AN20_ANCON3_BIT 4
+#define HAL_LL_RH4_AN20_ANCON3 20
+#define HAL_LL_RH5_AN21_ANCON3_BIT 5
+#define HAL_LL_RH5_AN21_ANCON3 21
+#define HAL_LL_RH6_AN22_ANCON3_BIT 6
+#define HAL_LL_RH6_AN22_ANCON3 22
+#define HAL_LL_RH7_AN23_ANCON3_BIT 7
+#define HAL_LL_RH7_AN23_ANCON3 23
 
 
 #define HAL_LL_ADCBUF0_ADDRESS 0xFC2U
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F87J94/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F87J94/mcu_definitions.h
index c3e57c5a4..ccdeb9b6d 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F87J94/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F87J94/mcu_definitions.h
@@ -53,46 +53,46 @@
 #define HAL_LL_RA2_AN2_ANCON1 2
 #define HAL_LL_RA3_AN3_ANCON1_BIT 3
 #define HAL_LL_RA3_AN3_ANCON1 3
-#define HAL_LL_RA4_AN6_ANCON1_BIT 4
-#define HAL_LL_RA4_AN6_ANCON1 6
-#define HAL_LL_RA5_AN4_ANCON1_BIT 5
-#define HAL_LL_RA5_AN4_ANCON1 4
-#define HAL_LL_RC2_AN9_ANCON2_BIT 1
-#define HAL_LL_RC2_AN9_ANCON2 9
-#define HAL_LL_RF2_AN7_ANCON1_BIT 6
-#define HAL_LL_RF2_AN7_ANCON1 7
-#define HAL_LL_RF5_AN10_ANCON2_BIT 1
-#define HAL_LL_RF5_AN10_ANCON2 10
-#define HAL_LL_RF6_AN11_ANCON2_BIT 2
-#define HAL_LL_RF6_AN11_ANCON2 11
-#define HAL_LL_RF7_AN5_ANCON1_BIT 5
-#define HAL_LL_RF7_AN5_ANCON1 5
-#define HAL_LL_RG0_AN8_ANCON2_BIT 0
-#define HAL_LL_RG0_AN8_ANCON2 8
-#define HAL_LL_RG1_AN19_ANCON3_BIT 3
-#define HAL_LL_RG1_AN19_ANCON3 19
-#define HAL_LL_RG2_AN18_ANCON3_BIT 2
-#define HAL_LL_RG2_AN18_ANCON3 18
-#define HAL_LL_RG3_AN17_ANCON3_BIT 1
-#define HAL_LL_RG3_AN17_ANCON3 17
-#define HAL_LL_RG4_AN16_ANCON2_BIT 7
-#define HAL_LL_RG4_AN16_ANCON2 16
-#define HAL_LL_RH0_AN23_ANCON3_BIT 7
-#define HAL_LL_RH0_AN23_ANCON3 23
-#define HAL_LL_RH1_AN22_ANCON3_BIT 6
-#define HAL_LL_RH1_AN22_ANCON3 22
-#define HAL_LL_RH2_AN21_ANCON3_BIT 5
-#define HAL_LL_RH2_AN21_ANCON3 21
-#define HAL_LL_RH3_AN20_ANCON3_BIT 4
-#define HAL_LL_RH3_AN20_ANCON3 20
-#define HAL_LL_RH4_AN12_ANCON2_BIT 4
-#define HAL_LL_RH4_AN12_ANCON2 12
-#define HAL_LL_RH5_AN13_ANCON2_BIT 5
-#define HAL_LL_RH5_AN13_ANCON2 13
-#define HAL_LL_RH6_AN14_ANCON2_BIT 6
-#define HAL_LL_RH6_AN14_ANCON2 14
-#define HAL_LL_RH7_AN15_ANCON2_BIT 7
-#define HAL_LL_RH7_AN15_ANCON2 15
+#define HAL_LL_RA4_AN4_ANCON1_BIT 4
+#define HAL_LL_RA4_AN4_ANCON1 4
+#define HAL_LL_RA5_AN5_ANCON1_BIT 5
+#define HAL_LL_RA5_AN5_ANCON1 5
+#define HAL_LL_RF2_AN6_ANCON1_BIT 6
+#define HAL_LL_RF2_AN6_ANCON1 6
+#define HAL_LL_RG0_AN7_ANCON1_BIT 7
+#define HAL_LL_RG0_AN7_ANCON1 7
+#define HAL_LL_RC2_AN8_ANCON2_BIT 0
+#define HAL_LL_RC2_AN8_ANCON2 8
+#define HAL_LL_RF5_AN9_ANCON2_BIT 1
+#define HAL_LL_RF5_AN9_ANCON2 9
+#define HAL_LL_RF6_AN10_ANCON2_BIT 2
+#define HAL_LL_RF6_AN10_ANCON2 10
+#define HAL_LL_RF7_AN11_ANCON2_BIT 3
+#define HAL_LL_RF7_AN11_ANCON2 11
+#define HAL_LL_RG1_AN12_ANCON2_BIT 4
+#define HAL_LL_RG1_AN12_ANCON2 12
+#define HAL_LL_RG2_AN13_ANCON2_BIT 5
+#define HAL_LL_RG2_AN13_ANCON2 13
+#define HAL_LL_RG3_AN14_ANCON2_BIT 6
+#define HAL_LL_RG3_AN14_ANCON2 14
+#define HAL_LL_RG4_AN15_ANCON2_BIT 7
+#define HAL_LL_RG4_AN15_ANCON2 15
+#define HAL_LL_RH0_AN16_ANCON3_BIT 0
+#define HAL_LL_RH0_AN16_ANCON3 16
+#define HAL_LL_RH1_AN17_ANCON3_BIT 1
+#define HAL_LL_RH1_AN17_ANCON3 17
+#define HAL_LL_RH2_AN18_ANCON3_BIT 2
+#define HAL_LL_RH2_AN18_ANCON3 18
+#define HAL_LL_RH3_AN19_ANCON3_BIT 3
+#define HAL_LL_RH3_AN19_ANCON3 19
+#define HAL_LL_RH4_AN20_ANCON3_BIT 4
+#define HAL_LL_RH4_AN20_ANCON3 20
+#define HAL_LL_RH5_AN21_ANCON3_BIT 5
+#define HAL_LL_RH5_AN21_ANCON3 21
+#define HAL_LL_RH6_AN22_ANCON3_BIT 6
+#define HAL_LL_RH6_AN22_ANCON3 22
+#define HAL_LL_RH7_AN23_ANCON3_BIT 7
+#define HAL_LL_RH7_AN23_ANCON3 23
 
 
 #define HAL_LL_ADCBUF0_ADDRESS 0xFC2U
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F95J94/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F95J94/mcu_definitions.h
index 47c0aa4b2..0bdebdbb3 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F95J94/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F95J94/mcu_definitions.h
@@ -53,46 +53,46 @@
 #define HAL_LL_RA2_AN2_ANCON1 2
 #define HAL_LL_RA3_AN3_ANCON1_BIT 3
 #define HAL_LL_RA3_AN3_ANCON1 3
-#define HAL_LL_RA4_AN6_ANCON1_BIT 4
-#define HAL_LL_RA4_AN6_ANCON1 6
-#define HAL_LL_RA5_AN4_ANCON1_BIT 5
-#define HAL_LL_RA5_AN4_ANCON1 4
-#define HAL_LL_RC2_AN9_ANCON2_BIT 1
-#define HAL_LL_RC2_AN9_ANCON2 9
-#define HAL_LL_RF2_AN7_ANCON1_BIT 6
-#define HAL_LL_RF2_AN7_ANCON1 7
-#define HAL_LL_RF5_AN10_ANCON2_BIT 1
-#define HAL_LL_RF5_AN10_ANCON2 10
-#define HAL_LL_RF6_AN11_ANCON2_BIT 2
-#define HAL_LL_RF6_AN11_ANCON2 11
-#define HAL_LL_RF7_AN5_ANCON1_BIT 5
-#define HAL_LL_RF7_AN5_ANCON1 5
-#define HAL_LL_RG0_AN8_ANCON2_BIT 0
-#define HAL_LL_RG0_AN8_ANCON2 8
-#define HAL_LL_RG1_AN19_ANCON3_BIT 3
-#define HAL_LL_RG1_AN19_ANCON3 19
-#define HAL_LL_RG2_AN18_ANCON3_BIT 2
-#define HAL_LL_RG2_AN18_ANCON3 18
-#define HAL_LL_RG3_AN17_ANCON3_BIT 1
-#define HAL_LL_RG3_AN17_ANCON3 17
-#define HAL_LL_RG4_AN16_ANCON2_BIT 7
-#define HAL_LL_RG4_AN16_ANCON2 16
-#define HAL_LL_RH0_AN23_ANCON3_BIT 7
-#define HAL_LL_RH0_AN23_ANCON3 23
-#define HAL_LL_RH1_AN22_ANCON3_BIT 6
-#define HAL_LL_RH1_AN22_ANCON3 22
-#define HAL_LL_RH2_AN21_ANCON3_BIT 5
-#define HAL_LL_RH2_AN21_ANCON3 21
-#define HAL_LL_RH3_AN20_ANCON3_BIT 4
-#define HAL_LL_RH3_AN20_ANCON3 20
-#define HAL_LL_RH4_AN12_ANCON2_BIT 4
-#define HAL_LL_RH4_AN12_ANCON2 12
-#define HAL_LL_RH5_AN13_ANCON2_BIT 5
-#define HAL_LL_RH5_AN13_ANCON2 13
-#define HAL_LL_RH6_AN14_ANCON2_BIT 6
-#define HAL_LL_RH6_AN14_ANCON2 14
-#define HAL_LL_RH7_AN15_ANCON2_BIT 7
-#define HAL_LL_RH7_AN15_ANCON2 15
+#define HAL_LL_RA4_AN4_ANCON1_BIT 4
+#define HAL_LL_RA4_AN4_ANCON1 4
+#define HAL_LL_RA5_AN5_ANCON1_BIT 5
+#define HAL_LL_RA5_AN5_ANCON1 5
+#define HAL_LL_RF2_AN6_ANCON1_BIT 6
+#define HAL_LL_RF2_AN6_ANCON1 6
+#define HAL_LL_RG0_AN7_ANCON1_BIT 7
+#define HAL_LL_RG0_AN7_ANCON1 7
+#define HAL_LL_RC2_AN8_ANCON2_BIT 0
+#define HAL_LL_RC2_AN8_ANCON2 8
+#define HAL_LL_RF5_AN9_ANCON2_BIT 1
+#define HAL_LL_RF5_AN9_ANCON2 9
+#define HAL_LL_RF6_AN10_ANCON2_BIT 2
+#define HAL_LL_RF6_AN10_ANCON2 10
+#define HAL_LL_RF7_AN11_ANCON2_BIT 3
+#define HAL_LL_RF7_AN11_ANCON2 11
+#define HAL_LL_RG1_AN12_ANCON2_BIT 4
+#define HAL_LL_RG1_AN12_ANCON2 12
+#define HAL_LL_RG2_AN13_ANCON2_BIT 5
+#define HAL_LL_RG2_AN13_ANCON2 13
+#define HAL_LL_RG3_AN14_ANCON2_BIT 6
+#define HAL_LL_RG3_AN14_ANCON2 14
+#define HAL_LL_RG4_AN15_ANCON2_BIT 7
+#define HAL_LL_RG4_AN15_ANCON2 15
+#define HAL_LL_RH0_AN16_ANCON3_BIT 0
+#define HAL_LL_RH0_AN16_ANCON3 16
+#define HAL_LL_RH1_AN17_ANCON3_BIT 1
+#define HAL_LL_RH1_AN17_ANCON3 17
+#define HAL_LL_RH2_AN18_ANCON3_BIT 2
+#define HAL_LL_RH2_AN18_ANCON3 18
+#define HAL_LL_RH3_AN19_ANCON3_BIT 3
+#define HAL_LL_RH3_AN19_ANCON3 19
+#define HAL_LL_RH4_AN20_ANCON3_BIT 4
+#define HAL_LL_RH4_AN20_ANCON3 20
+#define HAL_LL_RH5_AN21_ANCON3_BIT 5
+#define HAL_LL_RH5_AN21_ANCON3 21
+#define HAL_LL_RH6_AN22_ANCON3_BIT 6
+#define HAL_LL_RH6_AN22_ANCON3 22
+#define HAL_LL_RH7_AN23_ANCON3_BIT 7
+#define HAL_LL_RH7_AN23_ANCON3 23
 
 
 #define HAL_LL_ADCBUF0_ADDRESS 0xFC2U
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F96J94/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F96J94/mcu_definitions.h
index 47c0aa4b2..0bdebdbb3 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F96J94/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F96J94/mcu_definitions.h
@@ -53,46 +53,46 @@
 #define HAL_LL_RA2_AN2_ANCON1 2
 #define HAL_LL_RA3_AN3_ANCON1_BIT 3
 #define HAL_LL_RA3_AN3_ANCON1 3
-#define HAL_LL_RA4_AN6_ANCON1_BIT 4
-#define HAL_LL_RA4_AN6_ANCON1 6
-#define HAL_LL_RA5_AN4_ANCON1_BIT 5
-#define HAL_LL_RA5_AN4_ANCON1 4
-#define HAL_LL_RC2_AN9_ANCON2_BIT 1
-#define HAL_LL_RC2_AN9_ANCON2 9
-#define HAL_LL_RF2_AN7_ANCON1_BIT 6
-#define HAL_LL_RF2_AN7_ANCON1 7
-#define HAL_LL_RF5_AN10_ANCON2_BIT 1
-#define HAL_LL_RF5_AN10_ANCON2 10
-#define HAL_LL_RF6_AN11_ANCON2_BIT 2
-#define HAL_LL_RF6_AN11_ANCON2 11
-#define HAL_LL_RF7_AN5_ANCON1_BIT 5
-#define HAL_LL_RF7_AN5_ANCON1 5
-#define HAL_LL_RG0_AN8_ANCON2_BIT 0
-#define HAL_LL_RG0_AN8_ANCON2 8
-#define HAL_LL_RG1_AN19_ANCON3_BIT 3
-#define HAL_LL_RG1_AN19_ANCON3 19
-#define HAL_LL_RG2_AN18_ANCON3_BIT 2
-#define HAL_LL_RG2_AN18_ANCON3 18
-#define HAL_LL_RG3_AN17_ANCON3_BIT 1
-#define HAL_LL_RG3_AN17_ANCON3 17
-#define HAL_LL_RG4_AN16_ANCON2_BIT 7
-#define HAL_LL_RG4_AN16_ANCON2 16
-#define HAL_LL_RH0_AN23_ANCON3_BIT 7
-#define HAL_LL_RH0_AN23_ANCON3 23
-#define HAL_LL_RH1_AN22_ANCON3_BIT 6
-#define HAL_LL_RH1_AN22_ANCON3 22
-#define HAL_LL_RH2_AN21_ANCON3_BIT 5
-#define HAL_LL_RH2_AN21_ANCON3 21
-#define HAL_LL_RH3_AN20_ANCON3_BIT 4
-#define HAL_LL_RH3_AN20_ANCON3 20
-#define HAL_LL_RH4_AN12_ANCON2_BIT 4
-#define HAL_LL_RH4_AN12_ANCON2 12
-#define HAL_LL_RH5_AN13_ANCON2_BIT 5
-#define HAL_LL_RH5_AN13_ANCON2 13
-#define HAL_LL_RH6_AN14_ANCON2_BIT 6
-#define HAL_LL_RH6_AN14_ANCON2 14
-#define HAL_LL_RH7_AN15_ANCON2_BIT 7
-#define HAL_LL_RH7_AN15_ANCON2 15
+#define HAL_LL_RA4_AN4_ANCON1_BIT 4
+#define HAL_LL_RA4_AN4_ANCON1 4
+#define HAL_LL_RA5_AN5_ANCON1_BIT 5
+#define HAL_LL_RA5_AN5_ANCON1 5
+#define HAL_LL_RF2_AN6_ANCON1_BIT 6
+#define HAL_LL_RF2_AN6_ANCON1 6
+#define HAL_LL_RG0_AN7_ANCON1_BIT 7
+#define HAL_LL_RG0_AN7_ANCON1 7
+#define HAL_LL_RC2_AN8_ANCON2_BIT 0
+#define HAL_LL_RC2_AN8_ANCON2 8
+#define HAL_LL_RF5_AN9_ANCON2_BIT 1
+#define HAL_LL_RF5_AN9_ANCON2 9
+#define HAL_LL_RF6_AN10_ANCON2_BIT 2
+#define HAL_LL_RF6_AN10_ANCON2 10
+#define HAL_LL_RF7_AN11_ANCON2_BIT 3
+#define HAL_LL_RF7_AN11_ANCON2 11
+#define HAL_LL_RG1_AN12_ANCON2_BIT 4
+#define HAL_LL_RG1_AN12_ANCON2 12
+#define HAL_LL_RG2_AN13_ANCON2_BIT 5
+#define HAL_LL_RG2_AN13_ANCON2 13
+#define HAL_LL_RG3_AN14_ANCON2_BIT 6
+#define HAL_LL_RG3_AN14_ANCON2 14
+#define HAL_LL_RG4_AN15_ANCON2_BIT 7
+#define HAL_LL_RG4_AN15_ANCON2 15
+#define HAL_LL_RH0_AN16_ANCON3_BIT 0
+#define HAL_LL_RH0_AN16_ANCON3 16
+#define HAL_LL_RH1_AN17_ANCON3_BIT 1
+#define HAL_LL_RH1_AN17_ANCON3 17
+#define HAL_LL_RH2_AN18_ANCON3_BIT 2
+#define HAL_LL_RH2_AN18_ANCON3 18
+#define HAL_LL_RH3_AN19_ANCON3_BIT 3
+#define HAL_LL_RH3_AN19_ANCON3 19
+#define HAL_LL_RH4_AN20_ANCON3_BIT 4
+#define HAL_LL_RH4_AN20_ANCON3 20
+#define HAL_LL_RH5_AN21_ANCON3_BIT 5
+#define HAL_LL_RH5_AN21_ANCON3 21
+#define HAL_LL_RH6_AN22_ANCON3_BIT 6
+#define HAL_LL_RH6_AN22_ANCON3 22
+#define HAL_LL_RH7_AN23_ANCON3_BIT 7
+#define HAL_LL_RH7_AN23_ANCON3 23
 
 
 #define HAL_LL_ADCBUF0_ADDRESS 0xFC2U
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F97J94/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F97J94/mcu_definitions.h
index 1ff2c1bbd..27a9a8dd8 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F97J94/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18F97J94/mcu_definitions.h
@@ -53,46 +53,46 @@
 #define HAL_LL_RA2_AN2_ANCON1 2
 #define HAL_LL_RA3_AN3_ANCON1_BIT 3
 #define HAL_LL_RA3_AN3_ANCON1 3
-#define HAL_LL_RA4_AN6_ANCON1_BIT 4
-#define HAL_LL_RA4_AN6_ANCON1 6
-#define HAL_LL_RA5_AN4_ANCON1_BIT 5
-#define HAL_LL_RA5_AN4_ANCON1 4
-#define HAL_LL_RC2_AN9_ANCON2_BIT 1
-#define HAL_LL_RC2_AN9_ANCON2 9
-#define HAL_LL_RF2_AN7_ANCON1_BIT 6
-#define HAL_LL_RF2_AN7_ANCON1 7
-#define HAL_LL_RF5_AN10_ANCON2_BIT 1
-#define HAL_LL_RF5_AN10_ANCON2 10
-#define HAL_LL_RF6_AN11_ANCON2_BIT 2
-#define HAL_LL_RF6_AN11_ANCON2 11
-#define HAL_LL_RF7_AN5_ANCON1_BIT 5
-#define HAL_LL_RF7_AN5_ANCON1 5
-#define HAL_LL_RG0_AN8_ANCON2_BIT 0
-#define HAL_LL_RG0_AN8_ANCON2 8
-#define HAL_LL_RG1_AN19_ANCON3_BIT 3
-#define HAL_LL_RG1_AN19_ANCON3 19
-#define HAL_LL_RG2_AN18_ANCON3_BIT 2
-#define HAL_LL_RG2_AN18_ANCON3 18
-#define HAL_LL_RG3_AN17_ANCON3_BIT 1
-#define HAL_LL_RG3_AN17_ANCON3 17
-#define HAL_LL_RG4_AN16_ANCON2_BIT 7
-#define HAL_LL_RG4_AN16_ANCON2 16
-#define HAL_LL_RH0_AN23_ANCON3_BIT 7
-#define HAL_LL_RH0_AN23_ANCON3 23
-#define HAL_LL_RH1_AN22_ANCON3_BIT 6
-#define HAL_LL_RH1_AN22_ANCON3 22
-#define HAL_LL_RH2_AN21_ANCON3_BIT 5
-#define HAL_LL_RH2_AN21_ANCON3 21
-#define HAL_LL_RH3_AN20_ANCON3_BIT 4
-#define HAL_LL_RH3_AN20_ANCON3 20
-#define HAL_LL_RH4_AN12_ANCON2_BIT 4
-#define HAL_LL_RH4_AN12_ANCON2 12
-#define HAL_LL_RH5_AN13_ANCON2_BIT 5
-#define HAL_LL_RH5_AN13_ANCON2 13
-#define HAL_LL_RH6_AN14_ANCON2_BIT 6
-#define HAL_LL_RH6_AN14_ANCON2 14
-#define HAL_LL_RH7_AN15_ANCON2_BIT 7
-#define HAL_LL_RH7_AN15_ANCON2 15
+#define HAL_LL_RA4_AN4_ANCON1_BIT 4
+#define HAL_LL_RA4_AN4_ANCON1 4
+#define HAL_LL_RA5_AN5_ANCON1_BIT 5
+#define HAL_LL_RA5_AN5_ANCON1 5
+#define HAL_LL_RF2_AN6_ANCON1_BIT 6
+#define HAL_LL_RF2_AN6_ANCON1 6
+#define HAL_LL_RG0_AN7_ANCON1_BIT 7
+#define HAL_LL_RG0_AN7_ANCON1 7
+#define HAL_LL_RC2_AN8_ANCON2_BIT 0
+#define HAL_LL_RC2_AN8_ANCON2 8
+#define HAL_LL_RF5_AN9_ANCON2_BIT 1
+#define HAL_LL_RF5_AN9_ANCON2 9
+#define HAL_LL_RF6_AN10_ANCON2_BIT 2
+#define HAL_LL_RF6_AN10_ANCON2 10
+#define HAL_LL_RF7_AN11_ANCON2_BIT 3
+#define HAL_LL_RF7_AN11_ANCON2 11
+#define HAL_LL_RG1_AN12_ANCON2_BIT 4
+#define HAL_LL_RG1_AN12_ANCON2 12
+#define HAL_LL_RG2_AN13_ANCON2_BIT 5
+#define HAL_LL_RG2_AN13_ANCON2 13
+#define HAL_LL_RG3_AN14_ANCON2_BIT 6
+#define HAL_LL_RG3_AN14_ANCON2 14
+#define HAL_LL_RG4_AN15_ANCON2_BIT 7
+#define HAL_LL_RG4_AN15_ANCON2 15
+#define HAL_LL_RH0_AN16_ANCON3_BIT 0
+#define HAL_LL_RH0_AN16_ANCON3 16
+#define HAL_LL_RH1_AN17_ANCON3_BIT 1
+#define HAL_LL_RH1_AN17_ANCON3 17
+#define HAL_LL_RH2_AN18_ANCON3_BIT 2
+#define HAL_LL_RH2_AN18_ANCON3 18
+#define HAL_LL_RH3_AN19_ANCON3_BIT 3
+#define HAL_LL_RH3_AN19_ANCON3 19
+#define HAL_LL_RH4_AN20_ANCON3_BIT 4
+#define HAL_LL_RH4_AN20_ANCON3 20
+#define HAL_LL_RH5_AN21_ANCON3_BIT 5
+#define HAL_LL_RH5_AN21_ANCON3 21
+#define HAL_LL_RH6_AN22_ANCON3_BIT 6
+#define HAL_LL_RH6_AN22_ANCON3 22
+#define HAL_LL_RH7_AN23_ANCON3_BIT 7
+#define HAL_LL_RH7_AN23_ANCON3 23
 
 
 #define HAL_LL_ADCBUF0_ADDRESS 0xFC2U
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF25K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF25K42/mcu_definitions.h
index be28a4a6e..5104b451f 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF25K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF25K42/mcu_definitions.h
@@ -479,6 +479,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF26K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF26K42/mcu_definitions.h
index be28a4a6e..5104b451f 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF26K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF26K42/mcu_definitions.h
@@ -479,6 +479,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF27K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF27K42/mcu_definitions.h
index be28a4a6e..5104b451f 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF27K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF27K42/mcu_definitions.h
@@ -479,6 +479,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF45K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF45K42/mcu_definitions.h
index 1504a89fd..d275cfbd2 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF45K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF45K42/mcu_definitions.h
@@ -518,6 +518,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF46K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF46K42/mcu_definitions.h
index 1504a89fd..d275cfbd2 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF46K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF46K42/mcu_definitions.h
@@ -518,6 +518,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF47K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF47K42/mcu_definitions.h
index 1504a89fd..d275cfbd2 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF47K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF47K42/mcu_definitions.h
@@ -518,6 +518,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF55K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF55K42/mcu_definitions.h
index fc86f1ad3..587d38b10 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF55K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF55K42/mcu_definitions.h
@@ -547,6 +547,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF56K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF56K42/mcu_definitions.h
index fc86f1ad3..587d38b10 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF56K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF56K42/mcu_definitions.h
@@ -547,6 +547,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF57K42/mcu_definitions.h b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF57K42/mcu_definitions.h
index fc86f1ad3..587d38b10 100644
--- a/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF57K42/mcu_definitions.h
+++ b/targets/pic_8bit/mikroe/common/include/mcu_definitions/PIC18LF57K42/mcu_definitions.h
@@ -547,6 +547,8 @@
 // EOF PMD Register addresses
 
 // I2C and SPI Register addresses
+#define HAL_LL_I2C1ERR_ADDRESS 0x3D76U
+#define HAL_LL_I2C2ERR_ADDRESS 0x3D60U
 #define HAL_LL_I2C1ADB0_ADDRESS 0x3D6DU
 #define HAL_LL_I2C1ADB1_ADDRESS 0x3D6EU
 #define HAL_LL_I2C1CLK_ADDRESS 0x3D7BU
diff --git a/targets/pic_8bit/mikroe/pic18/src/i2c/implementation_2/hal_ll_i2c_master.c b/targets/pic_8bit/mikroe/pic18/src/i2c/implementation_2/hal_ll_i2c_master.c
index 5452ff917..d044144e1 100644
--- a/targets/pic_8bit/mikroe/pic18/src/i2c/implementation_2/hal_ll_i2c_master.c
+++ b/targets/pic_8bit/mikroe/pic18/src/i2c/implementation_2/hal_ll_i2c_master.c
@@ -93,6 +93,8 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU
 #define HAL_LL_I2C_MASTER_TXBE_BIT 5
 #define HAL_LL_I2C_MASTER_RXBF_BIT 0
 #define HAL_LL_I2C_MASTER_STOP_FLAG_BIT 2
+#define HAL_LL_I2C_MASTER_NACK_DETECT_BIT 4
+#define HAL_LL_I2C_MASTER_NACK_ENABLE_DETECT_BIT 0
 #define HAL_LL_I2C_MASTER_BFRE_BIT 7
 
 /*!< @brief Default pass count value upon reset */
@@ -105,6 +107,7 @@ typedef struct
     hal_ll_base_addr_t i2c_con0_reg_addr;
     hal_ll_base_addr_t i2c_con1_reg_addr;
     hal_ll_base_addr_t i2c_con2_reg_addr;
+    hal_ll_base_addr_t i2c_err_reg_addr;
     hal_ll_base_addr_t i2c_clk_reg_addr;
     hal_ll_base_addr_t i2c_pie_reg_addr;
     hal_ll_base_addr_t i2c_pir_reg_addr;
@@ -183,16 +186,16 @@ typedef enum
 static const hal_ll_i2c_base_handle_t hal_ll_i2c_hw_regs[ I2C_MODULE_COUNT + 1 ] =
 {
     #ifdef I2C_MODULE
-    { HAL_LL_I2C1CON0_ADDRESS, HAL_LL_I2C1CON1_ADDRESS, HAL_LL_I2C1CON2_ADDRESS, HAL_LL_I2C1CLK_ADDRESS, HAL_LL_I2C1PIE_ADDRESS, HAL_LL_I2C1PIR_ADDRESS, HAL_LL_I2C1STAT0_ADDRESS, HAL_LL_I2C1STAT1_ADDRESS, HAL_LL_I2C1CNT_ADDRESS, HAL_LL_I2C1ADB1_ADDRESS, HAL_LL_I2C1RXB_ADDRESS, HAL_LL_I2C1TXB_ADDRESS },
+    { HAL_LL_I2C1CON0_ADDRESS, HAL_LL_I2C1CON1_ADDRESS, HAL_LL_I2C1CON2_ADDRESS, HAL_LL_I2C1ERR_ADDRESS, HAL_LL_I2C1CLK_ADDRESS, HAL_LL_I2C1PIE_ADDRESS, HAL_LL_I2C1PIR_ADDRESS, HAL_LL_I2C1STAT0_ADDRESS, HAL_LL_I2C1STAT1_ADDRESS, HAL_LL_I2C1CNT_ADDRESS, HAL_LL_I2C1ADB1_ADDRESS, HAL_LL_I2C1RXB_ADDRESS, HAL_LL_I2C1TXB_ADDRESS },
     #endif
     #ifdef I2C_MODULE_1
-    { HAL_LL_I2C1CON0_ADDRESS, HAL_LL_I2C1CON1_ADDRESS, HAL_LL_I2C1CON2_ADDRESS, HAL_LL_I2C1CLK_ADDRESS, HAL_LL_I2C1PIE_ADDRESS, HAL_LL_I2C1PIR_ADDRESS, HAL_LL_I2C1STAT0_ADDRESS, HAL_LL_I2C1STAT1_ADDRESS, HAL_LL_I2C1CNT_ADDRESS, HAL_LL_I2C1ADB1_ADDRESS, HAL_LL_I2C1RXB_ADDRESS, HAL_LL_I2C1TXB_ADDRESS },
+    { HAL_LL_I2C1CON0_ADDRESS, HAL_LL_I2C1CON1_ADDRESS, HAL_LL_I2C1CON2_ADDRESS, HAL_LL_I2C1ERR_ADDRESS, HAL_LL_I2C1CLK_ADDRESS, HAL_LL_I2C1PIE_ADDRESS, HAL_LL_I2C1PIR_ADDRESS, HAL_LL_I2C1STAT0_ADDRESS, HAL_LL_I2C1STAT1_ADDRESS, HAL_LL_I2C1CNT_ADDRESS, HAL_LL_I2C1ADB1_ADDRESS, HAL_LL_I2C1RXB_ADDRESS, HAL_LL_I2C1TXB_ADDRESS },
     #endif
     #ifdef I2C_MODULE_2
-    { HAL_LL_I2C2CON0_ADDRESS, HAL_LL_I2C2CON1_ADDRESS, HAL_LL_I2C2CON2_ADDRESS, HAL_LL_I2C2CLK_ADDRESS, HAL_LL_I2C2PIE_ADDRESS, HAL_LL_I2C2PIR_ADDRESS, HAL_LL_I2C2STAT0_ADDRESS, HAL_LL_I2C2STAT1_ADDRESS, HAL_LL_I2C2CNT_ADDRESS, HAL_LL_I2C2ADB1_ADDRESS, HAL_LL_I2C2RXB_ADDRESS, HAL_LL_I2C2TXB_ADDRESS },
+    { HAL_LL_I2C2CON0_ADDRESS, HAL_LL_I2C2CON1_ADDRESS, HAL_LL_I2C2CON2_ADDRESS, HAL_LL_I2C2ERR_ADDRESS, HAL_LL_I2C2CLK_ADDRESS, HAL_LL_I2C2PIE_ADDRESS, HAL_LL_I2C2PIR_ADDRESS, HAL_LL_I2C2STAT0_ADDRESS, HAL_LL_I2C2STAT1_ADDRESS, HAL_LL_I2C2CNT_ADDRESS, HAL_LL_I2C2ADB1_ADDRESS, HAL_LL_I2C2RXB_ADDRESS, HAL_LL_I2C2TXB_ADDRESS },
     #endif
 
-    { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR }
+    { HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR }
 };
 
 // ------------------------------------------------------------------ VARIABLES
@@ -614,7 +617,7 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m
         while ( !hal_ll_i2c_master_is_idle( map->base ) ) {
             if ( map->timeout ) {
                 if ( !time_counter-- )
-                    return HAL_LL_I2C_MASTER_TIMEOUT_WRITE;
+                    return HAL_LL_I2C_MASTER_TIMEOUT_READ;
                 }
         }
     }
@@ -630,7 +633,7 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m
     while ( !( hal_ll_hw_reg->i2c_pir_reg_addr, HAL_LL_I2C_MASTER_START_RESTART_BITS_MASK ) ) {
         if ( map->timeout ) {
             if ( !time_counter-- )
-                return HAL_LL_I2C_MASTER_TIMEOUT_WRITE;
+                return HAL_LL_I2C_MASTER_TIMEOUT_READ;
             }
     }
 
@@ -647,10 +650,7 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m
         #endif
         hal_ll_i2c_master_restart( map->base );
     } else {
-        status = hal_ll_i2c_master_start( map );
-        if ( status != HAL_LL_I2C_MASTER_SUCCESS ) {
-            return status;
-        }
+        hal_ll_i2c_master_stop( map->base );
     }
 
     for( transfer_counter = 0; transfer_counter < len_read_data; transfer_counter++) {
@@ -658,7 +658,7 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m
         while ( !check_reg_bit( hal_ll_hw_reg->i2c_stat1_reg_addr, HAL_LL_I2C_MASTER_RXBF_BIT ) ) {
             if ( map->timeout ) {
                 if ( !time_counter-- )
-                    return HAL_LL_I2C_MASTER_TIMEOUT_WRITE;
+                    return HAL_LL_I2C_MASTER_TIMEOUT_READ;
             }
         }
         read_data_buf[ transfer_counter ] = read_reg(hal_ll_hw_reg->i2c_rxb_reg_addr);
@@ -668,10 +668,11 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m
 
     time_counter = map->timeout;
     clear_reg_bit( hal_ll_hw_reg->i2c_pir_reg_addr, HAL_LL_I2C_MASTER_STOP_FLAG_BIT );
-    while ( !( check_reg_bit( hal_ll_hw_reg->i2c_pir_reg_addr, HAL_LL_I2C_MASTER_STOP_FLAG_BIT ) ) ) {
+
+    while ( !( check_reg_bit( hal_ll_hw_reg->i2c_err_reg_addr, HAL_LL_I2C_MASTER_NACK_DETECT_BIT ) ) ) {
         if ( map->timeout ) {
             if ( !time_counter-- )
-                return HAL_LL_I2C_MASTER_TIMEOUT_WRITE;
+                return HAL_LL_I2C_MASTER_TIMEOUT_READ;
         }
     }
 
@@ -936,6 +937,9 @@ static hal_ll_err_t hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) {
     const hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct(map->base);
     uint16_t time_counter = map->timeout;
 
+    // Enable NACK detect interrupts.
+    set_reg_bit( hal_ll_hw_reg->i2c_err_reg_addr, HAL_LL_I2C_MASTER_NACK_ENABLE_DETECT_BIT );
+
     set_reg_bit( HAL_LL_OSCEN_ADDRESS, HAL_LL_OSCEN_MFOEN_BIT );
     while ( !check_reg_bit( HAL_LL_OSCSTAT_ADDRESS, HAL_LL_OSCSTAT_MFOR_BIT ) ) {
         if ( map->timeout ) {
diff --git a/targets/riscv/mikroe/gigadevice/src/gpio/implementation_1/hal_ll_gpio_port.c b/targets/riscv/mikroe/gigadevice/src/gpio/implementation_1/hal_ll_gpio_port.c
index fdc9464cc..7ac3d7050 100644
--- a/targets/riscv/mikroe/gigadevice/src/gpio/implementation_1/hal_ll_gpio_port.c
+++ b/targets/riscv/mikroe/gigadevice/src/gpio/implementation_1/hal_ll_gpio_port.c
@@ -50,7 +50,7 @@
 #define GPIO_SWJ_CFG_PIN_MASK                      (0x18UL)
 #define GPIO_AFIO_PCF0_SWJ_CFG_RESET               (0xF8FFFFFFUL)
 #define GPIO_AFIO_PCF0_SWJ_CFG_NJRST_DISABLED      (0x01000000UL)
-#define GPIO_AFIO_PCF0_SWJ_CFG_DISABLED            (0x02000000UL)
+#define GPIO_AFIO_PCF0_SWJ_CFG_DISABLED            (0x04000000UL)
 
 #if defined(GD32VF103)
     #define GPIOA_BASE_ADDR                        (0x40010800UL)
diff --git a/tests/gpio/CMakeLists.txt b/tests/gpio/CMakeLists.txt
index 3060c459f..707e3b7b5 100644
--- a/tests/gpio/CMakeLists.txt
+++ b/tests/gpio/CMakeLists.txt
@@ -7,7 +7,7 @@ string(SUBSTRING ${MCU_NAME} 0 7 MCU_NAME_FIRST_7)
 
 if ( ( ${MCU_NAME_FIRST_7} STREQUAL "PIC32MZ" ) OR ( ${MCU_NAME_FIRST_7} STREQUAL "PIC32MX" ) OR ( ${MCU_NAME_FIRST_5} STREQUAL "STM32" ) OR ( ${MCU_NAME} MATCHES "GD32VF103" ) )
     list(APPEND gpio_def_list "port_count_size=16")
-elseif( ( ${MCU_NAME_FIRST_5} STREQUAL "PIC18" ) OR ( ${MCU_NAME_FIRST_4} STREQUAL "TM4C" ) )
+elseif( ( ${MCU_NAME_FIRST_5} STREQUAL "PIC18" ) OR ( ${MCU_NAME_FIRST_4} STREQUAL "TM4C" ) OR ( ${MCU_NAME_FIRST_2} STREQUAL "AT" ) )
     list(APPEND gpio_def_list "port_count_size=8")
 elseif( ${MCU_NAME_FIRST_2} STREQUAL "MK" )
     list(APPEND gpio_def_list "port_count_size=32")
diff --git a/tests/tft_jig/CMakeLists.txt b/tests/tft_jig/CMakeLists.txt
index e03e2ae6e..49ff48778 100644
--- a/tests/tft_jig/CMakeLists.txt
+++ b/tests/tft_jig/CMakeLists.txt
@@ -9,10 +9,10 @@ add_executable(test_tft_jig
 
 set(tft_list "")
 
-if ( ${_MSDK_BOARD_NAME_} MATCHES "(^BOARD(.+)(FUSION|PRO)(.+)V8$)|(^MIKROMEDIA(.+)$)" )
+if ( ${_MSDK_BOARD_NAME_} MATCHES "(^BOARD(.+)(UNI_DS|FUSION|PRO)(.+)V8$)|(^MIKROMEDIA(.+)$)" )
     list(APPEND tft_list "__SSD1963__")
-elseif( ${_MSDK_BOARD_NAME_} MATCHES "(^BOARD(.+)(FUSION|PRO)(.+)V8$)|(^MIKROMEDIA(.+)$)" )
-    list(APPEND tft_list "__ILI9341__")
+#elseif( ${_MSDK_BOARD_NAME_} MATCHES "(TODO - Add this once ILI9341 is added to SDK)" )
+    #list(APPEND tft_list "__ILI9341__")
 else()
     list(APPEND tft_list "__TFT_NOT_SUPPORTED__")
 endif()