diff --git a/access/access.vhd b/access/access.vhd
deleted file mode 100644
index 1d94298..0000000
--- a/access/access.vhd
+++ /dev/null
@@ -1,69 +0,0 @@
---*******************************
---* TITLE: Access (sender) 	*
---* TYPE: Component		*
---* AUTHOR: Dylan Van Assche 	*
---* DATE: 01/10/2017 		*
---*******************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- Access layer API.
---2)Principle:
--- Provide an API as access layer
---3)Inputs:
--- data, pn_select, rst, clk, clk_en
---4)Outputs:
--- pn_start, tx
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-ENTITY access_layer IS
-	PORT
-	(
-		clk       : IN std_logic;
-		clk_en    : IN std_logic;
-		rst       : IN std_logic;
-		data      : IN std_logic;
-		pn_select : IN std_logic_vector(1 DOWNTO 0);
-		pn_start  : OUT std_logic;
-		tx        : OUT std_logic
-	);
-END access_layer;
-ARCHITECTURE behavior OF access_layer IS
-	SIGNAL pn_1_output  : std_logic;
-	SIGNAL pn_2_output  : std_logic;
-	SIGNAL pn_3_output  : std_logic;
-	SIGNAL pn_1_xor     : std_logic;
-	SIGNAL pn_2_xor     : std_logic;
-	SIGNAL pn_3_xor     : std_logic;
-BEGIN
---EXOR ports
-pn_1_xor <= pn_1_output XOR data;
-pn_2_xor <= pn_2_output XOR data;
-pn_3_xor <= pn_3_output XOR data;
---components
-pngenerator : ENTITY work.pngenerator(behavior)
-PORT MAP
-(
-	clk    => clk,
-	clk_en => clk_en,
-	rst => rst,
-	pn_1 => pn_1_output,
-	pn_2 => pn_2_output,
-	pn_3 => pn_3_output,
-	pn_s => pn_start
-);
-mux : ENTITY work.mux(behavior)
-PORT MAP
-(
-	in_0 => data,
-	in_1 => pn_1_xor,
-	in_2 => pn_2_xor,
-	in_3 => pn_3_xor,
-	in_select => pn_select,              
-	output => tx             
-);
-END behavior;
\ No newline at end of file
diff --git a/access/access_test.vhd b/access/access_test.vhd
deleted file mode 100644
index b21ac82..0000000
--- a/access/access_test.vhd
+++ /dev/null
@@ -1,94 +0,0 @@
---***************************************
---* TITLE: Access TESTBENCH (sender)	*
---* TYPE: Top File 			*
---* AUTHOR: Dylan Van Assche 		*
---* DATE: 12/10/2017 			*
---***************************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- TESTBENCH: Access layer API.
---2)Principle:
--- Provide an API as access layer
---3)Inputs:
--- rst, clk, clk_en
---4)Outputs:
--- output, display_b
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-USE ieee.std_logic_arith.ALL;
-ENTITY access_layer_test IS
-END access_layer_test;
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE structural OF access_layer_test IS
-	--initialize signals & constants
-	CONSTANT period   : TIME := 100 ns;
-	CONSTANT delay    : TIME := 10 ns;
-	SIGNAL end_of_sim : BOOLEAN := false;
-	SIGNAL clk        : std_logic := '0';
-	SIGNAL clk_en     : std_logic := '1';
-	SIGNAL rst        : std_logic := '0';
-	SIGNAL data	  : std_logic;
-	SIGNAL pn_select  : std_logic_vector(1 DOWNTO 0);
-	SIGNAL pn_start   : std_logic;
-	SIGNAL tx         : std_logic;
-BEGIN
---***********
---* MAPPING *
---***********
-uut : ENTITY work.access_layer(behavior)
-	PORT MAP
-	(
-		clk       => clk,
-		clk_en    => clk_en,
-		rst       => rst,
-		data	  => data,
-		pn_select => pn_select,
-		pn_start  => pn_start,
-		tx        => tx
-	);
--- Only for synchronous components
-clock : PROCESS
-BEGIN
-	clk <= '0';
-	WAIT FOR period/2;
-	LOOP
-		clk <= '0';
-		WAIT FOR period/2;
-		clk <= '1';
-		WAIT FOR period/2;
-		EXIT WHEN end_of_sim;
-	END LOOP;
-	WAIT;
-	END PROCESS clock;
--- Testbench
-tb : PROCESS
-	-- Reset procedure to initialize the component
-	PROCEDURE reset IS
-	BEGIN
-		rst <= '1';
-		WAIT FOR period * 2;
-		rst <= '0';
-		WAIT FOR period;
-	END reset;
-BEGIN
-	-- Reset at startup
-	reset;
-	-- Test data
-	FOR i IN 0 TO 3 LOOP
-		pn_select <= CONV_STD_LOGIC_VECTOR(i, 2);
-		data <= '1';
-		WAIT FOR period*10;
-	END LOOP;
-
-	end_of_sim <= true;
-	WAIT;
-END PROCESS;
-END;
\ No newline at end of file
diff --git a/access/mux/mux.vhd b/access/mux/mux.vhd
deleted file mode 100644
index df2e721..0000000
--- a/access/mux/mux.vhd
+++ /dev/null
@@ -1,47 +0,0 @@
---*****************************
---* TITLE: MUX (sender) 	     *
---* TYPE: Component 		        *
---* AUTHOR: Dylan Van Assche 	*
---* DATE: 12/01/2017 		       *
---*****************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- Selecting the right PN code
---2)Principle:
--- Decode a dipswitch to select the right PN code
---3)Inputs:
--- 
---4)Outputs:
--- output
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-ENTITY mux IS
-	PORT
-	(
-		in_0, in_1, in_2, in_3  : IN std_logic;
-		in_select               : IN std_logic_vector(1 DOWNTO 0);
-		output                  : OUT std_logic
-	);
-END mux;
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE behavior OF mux IS
-BEGIN
-decode : PROCESS (in_0, in_1, in_2, in_3, in_select)
-BEGIN
-	CASE in_select IS
-		WHEN "00" => output  <= in_0; -- 'input in_0'
-		WHEN "01" => output  <= in_1; -- 'input in_1'
-		WHEN "10" => output  <= in_2; -- 'input in_2'
-		WHEN "11" => output  <= in_3; -- 'input in_3'
-		WHEN OTHERS => output <= in_0; -- fallback
-	END CASE;
-END PROCESS decode;
-END behavior;
\ No newline at end of file
diff --git a/access/mux/mux_test.vhd b/access/mux/mux_test.vhd
deleted file mode 100644
index d183390..0000000
--- a/access/mux/mux_test.vhd
+++ /dev/null
@@ -1,70 +0,0 @@
---*********************************
---* TITLE: MUX TESTBENCH (sender) *
---* TYPE: Component 		            *
---* AUTHOR: Dylan Van Assche 	    *
---* DATE: 12/01/2017 		           *
---*********************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- Selecting the right PN code
---2)Principle:
--- Decode a dipswitch to select the right PN code
---3)Inputs:
--- 
---4)Outputs:
--- output
---***************************
---* LIBRARIES & ENTITY *
---***************************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-USE ieee.std_logic_arith.ALL;
-ENTITY mux_test IS
-END mux_test;
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE structural OF mux_test IS
-	-- Initialize signals & constants
-	CONSTANT period   : TIME := 100 ns;
-	CONSTANT delay    : TIME := 10 ns;
-	SIGNAL end_of_sim : BOOLEAN := false;
-	SIGNAL in_0       : std_logic;
-	SIGNAL in_1       : std_logic;
-	SIGNAL in_2       : std_logic;
-	SIGNAL in_3       : std_logic;
-	SIGNAL output     : std_logic; 
-	SIGNAL in_select  : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
-BEGIN
---***********
---* MAPPING *
---***********
-uut : ENTITY work.mux(behavior)
-	PORT MAP
-	(
-		in_0      => in_0,
-		in_1      => in_1,
-		in_2      => in_2,
-		in_3      => in_3,
-		in_select => in_select,
-		output    => output
-	);
-			
--- Testbench
-tb : PROCESS
-BEGIN
-  in_0 <= '1';
-  in_1 <= '0';
-  in_2 <= '1';
-  in_3 <= '0';
-	FOR i IN 0 TO 3 LOOP
-		in_select <= CONV_STD_LOGIC_VECTOR(i, 2);
-		WAIT FOR period;
-	END LOOP;
-	end_of_sim <= true;
-	WAIT;
-END PROCESS;
-END;
\ No newline at end of file
diff --git a/access/pngenerator/pngenerator.vhd b/access/pngenerator/pngenerator.vhd
deleted file mode 100644
index 14879b0..0000000
--- a/access/pngenerator/pngenerator.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
---*******************************
---* TITLE: PNGenerator (sender)	*
---* TYPE: Component 		          *
---* AUTHOR: Dylan Van Assche 	  *
---* DATE: 12/10/2017 		         *
---*******************************
---* DESCRIPTION *
---***************
---1)Purpose:
--- Generating a PN code
---2)Principle:
--- Lineair feedback register to generate a PN code (31 bits)
---3)Inputs:
--- rst, clk, clk_en
---4)Outputs:
--- pn_start, pn_1, pn_2, pn_3
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-ENTITY pngenerator IS
-	PORT
-	(
-		clk, clk_en, rst : IN std_logic;
-		pn_s, pn_1, pn_2, pn_3  : OUT std_logic -- pn_0 is without PN code
-	);
-	SIGNAL shdata1          : std_logic_vector(4 DOWNTO 0);
-	SIGNAL shdata1_next     : std_logic_vector(4 DOWNTO 0);
-	SIGNAL shdata2          : std_logic_vector(4 DOWNTO 0);
-	SIGNAL shdata2_next     : std_logic_vector(4 DOWNTO 0);
-	SIGNAL pn_start_next    : std_logic;
-	SIGNAL pn_start         : std_logic;
-	SIGNAL linear_feedback1 : std_logic;
-	SIGNAL linear_feedback2 : std_logic;
-END;
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE behavior OF pngenerator IS
-BEGIN
--- calculate linear feedback for both PN counters (LFSR)
-linear_feedback1 <= (shdata1(0) XOR shdata1(3));
-linear_feedback2 <= ((shdata2(0) XOR shdata2(1)) XOR shdata2(3)) XOR shdata2(4);
--- connect signals to outputs
-pn_1 <= shdata1(0);
-pn_2 <= shdata2(0);
-pn_3 <= shdata1(0) XOR shdata2(0);
-pn_s <= pn_start;
--- 2-Process: synchronous part
-pn_sync : PROCESS (clk)
-BEGIN
-	IF (rising_edge(clk) AND clk_en = '1') THEN
-		IF (rst = '1') THEN -- rst line high, go to initial state
-			shdata1 <= "00010";
-			shdata2 <= "00111";
-			pn_start <= '1';
-		ELSE -- normal operation
-			pn_start <= pn_start_next;
-			shdata1 <= shdata1_next;
-			shdata2 <= shdata2_next;
-		END IF;
-	END IF;
-END PROCESS pn_sync;
--- 2-Process: combinatoric part
-pn_comb : PROCESS (shdata1, shdata2, linear_feedback1, linear_feedback2)
-BEGIN
-	shdata1_next <= linear_feedback1 & shdata1(4 DOWNTO 1);
-	shdata2_next <= linear_feedback2 & shdata2(4 DOWNTO 1);
-	IF (shdata1 = "00100") THEN -- next value is the start value, prepare this already
-			pn_start_next <= '1';
-	ELSE
-			pn_start_next <= '0';
-	END IF;	
-END PROCESS pn_comb;
-END behavior;
diff --git a/access/pngenerator/pngenerator_test.vhd b/access/pngenerator/pngenerator_test.vhd
deleted file mode 100644
index e38f03c..0000000
--- a/access/pngenerator/pngenerator_test.vhd
+++ /dev/null
@@ -1,89 +0,0 @@
---*******************************
---* TITLE: PNGenerator TESTBENCH (sender)	*
---* TYPE: Component 		          *
---* AUTHOR: Dylan Van Assche 	  *
---* DATE: 12/10/2017 		         *
---*******************************
---* DESCRIPTION *
---***************
---1)Purpose:
--- TESTBENCH: Generating a PN code
---2)Principle:
--- Lineair feedback register to generate a PN code (31 bits)
---3)Inputs:
--- rst, clk, clk_en
---4)Outputs:
--- pn_start, pn_1, pn_2, pn_3
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-USE ieee.std_logic_arith.ALL;
-ENTITY pngenerator_test IS
-END pngenerator_test;
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE structural OF pngenerator_test IS
-	--initialize signals & constants
-	CONSTANT period   : TIME := 100 ns;
-	CONSTANT delay    : TIME := 10 ns;
-	SIGNAL end_of_sim : BOOLEAN := false;
-	SIGNAL clk        : std_logic := '0';
-	SIGNAL clk_en     : std_logic := '1';
-	SIGNAL rst        : std_logic := '0';
-	SIGNAL pn_1       : std_logic;
-	SIGNAL pn_2       : std_logic;
-	SIGNAL pn_3       : std_logic;
-	SIGNAL pn_s	  : std_logic;
-BEGIN
---***********
---* MAPPING *
---***********
-uut : ENTITY work.pngenerator(behavior)
-	PORT MAP
-	(
-		clk    => clk,
-		clk_en => clk_en,
-		rst    => rst,
-		pn_1   => pn_1,
-		pn_2   => pn_2,
-		pn_3   => pn_3,
-		pn_s   => pn_s
-	);
--- Only for synchronous components
-clock : PROCESS
-BEGIN
-	clk <= '0';
-	WAIT FOR period/2;
-	LOOP
-		clk <= '0';
-		WAIT FOR period/2;
-		clk <= '1';
-		WAIT FOR period/2;
-		EXIT WHEN end_of_sim;
-	END LOOP;
-	WAIT;
-END PROCESS clock;
--- Testbench
-tb : PROCESS
-	-- Reset procedure to initialize the component
-	PROCEDURE reset IS
-	BEGIN
-		rst <= '1';
-		WAIT FOR period * 2;
-		rst <= '0';
-		WAIT FOR period;
-	END reset;
-BEGIN
-	-- Reset at startup
-	reset;
-	-- Test data
-	WAIT FOR period*33;
-	
-	end_of_sim <= true;
-	WAIT;
-END PROCESS;
-END;
\ No newline at end of file
diff --git a/application/application.vhd b/application/application.vhd
deleted file mode 100644
index 40f9c89..0000000
--- a/application/application.vhd
+++ /dev/null
@@ -1,95 +0,0 @@
---*******************************
---* TITLE: Application (sender) *
---* TYPE: Component		*
---* AUTHOR: Dylan Van Assche 	*
---* DATE: 01/10/2017 		*
---*******************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- Application layer API.
---2)Principle:
--- Provide an API as application layer
---3)Inputs:
--- cha, rst, clk, clk_en
---4)Outputs:
--- output, display_b
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-ENTITY application_layer IS
-	PORT
-	(
-		clk       : IN std_logic;
-		clk_en    : IN std_logic;
-		rst       : IN std_logic;
-		up        : IN std_logic;
-		down      : IN std_logic;
-		output    : OUT std_logic_vector(3 DOWNTO 0);
-		display_b : OUT std_logic_vector(6 DOWNTO 0)
-	);
-END application_layer;
-ARCHITECTURE behavior OF application_layer IS
-	SIGNAL counter_output : std_logic_vector(3 DOWNTO 0);
-	SIGNAL btn_up_deb_s   : std_logic;
-	SIGNAL btn_down_deb_s : std_logic;
-	SIGNAL btn_up_edg_s   : std_logic;
-	SIGNAL btn_down_edg_s : std_logic;
-BEGIN
-output <= counter_output;
-decoder : ENTITY work.decoder(behavior)
-PORT MAP
-(
-	bin    => counter_output,
-	disp_b => display_b
-);
-edge1 : ENTITY work.edgedetector(behavior)
-PORT MAP
-(
-	data   => btn_up_deb_s,
-	puls   => btn_up_edg_s,
-	clk    => clk,
-	clk_en => clk_en,
-	rst    => rst
-);
-edge2 : ENTITY work.edgedetector(behavior)
-PORT MAP
-(
-	data   => btn_down_deb_s,
-	puls   => btn_down_edg_s,
-	clk    => clk,
-	clk_en => clk_en,
-	rst    => rst
-);
-debounce1 : ENTITY work.debouncer(behavior)
-PORT MAP
-(
-	clk    => clk,
-	clk_en => clk_en,
-	rst    => rst,
-	cha    => up,
-	syncha => btn_up_deb_s
-);
-debounce2 : ENTITY work.debouncer(behavior)
-PORT MAP
-(
-	clk    => clk,
-	clk_en => clk_en,
-	rst    => rst,
-	cha    => down,
-	syncha => btn_down_deb_s
-);
-counter : ENTITY work.counter(behavior)
-PORT MAP
-(
-	clk    => clk,
-	clk_en => clk_en,
-	rst    => rst,
-	up     => btn_up_edg_s,
-	down   => btn_down_edg_s,
-	output => counter_output
-);
-END behavior;
diff --git a/application/application_test.vhd b/application/application_test.vhd
deleted file mode 100644
index 38b1a50..0000000
--- a/application/application_test.vhd
+++ /dev/null
@@ -1,102 +0,0 @@
---***********************************************
---* TITLE: Application TESTBENCH (sender)	*
---* TYPE: Top File 				*
---* AUTHOR: Dylan Van Assche			*
---* DATE: 01/10/2017 				*
---***********************************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- TESTBENCH: Application layer API.
---2)Principle:
--- Provide an API as application layer
---3)Inputs:
--- cha, rst, clk, clk_en
---4)Outputs:
--- output, display_b
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-USE ieee.std_logic_arith.ALL;
-ENTITY application_layer_test IS
-END application_layer_test;
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE structural OF application_layer_test IS
-	--initialize signals & constants
-	CONSTANT period   : TIME := 100 ns;
-	CONSTANT delay    : TIME := 10 ns;
-	SIGNAL end_of_sim : BOOLEAN := false;
-	SIGNAL clk        : std_logic := '0';
-	SIGNAL clk_en     : std_logic := '1';
-	SIGNAL rst        : std_logic := '0';
-	SIGNAL up         : std_logic := '0';
-	SIGNAL down       : std_logic := '0';
-	SIGNAL output     : std_logic_vector(3 DOWNTO 0);
-	SIGNAL display_b  : std_logic_vector(6 DOWNTO 0);
-BEGIN
---***********
---* MAPPING *
---***********
-uut : ENTITY work.application_layer(behavior)
-	PORT MAP
-	(
-		clk       => clk,
-		clk_en    => clk_en,
-		rst       => rst,
-		up        => up,
-		down      => down,
-		output    => output,
-		display_b => display_b
-	);
--- Only for synchronous components
-clock : PROCESS
-BEGIN
-	clk <= '0';
-	WAIT FOR period/2;
-	LOOP
-		clk <= '0';
-		WAIT FOR period/2;
-		clk <= '1';
-		WAIT FOR period/2;
-		EXIT WHEN end_of_sim;
-	END LOOP;
-	WAIT;
-	END PROCESS clock;
--- Testbench
-tb : PROCESS
-	-- Reset procedure to initialize the component
-	PROCEDURE reset IS
-	BEGIN
-		rst <= '1';
-		WAIT FOR period * 2;
-		rst <= '0';
-		WAIT FOR period;
-	END reset;
-	-- Test data procedure
-	PROCEDURE test (CONSTANT testdata : IN std_logic_vector(1 DOWNTO 0)) IS
-	BEGIN
-		up   <= testdata(0);
-		down <= testdata(1);
-		WAIT FOR period * 5;
-	END test;
-BEGIN
-	-- Reset at startup
-	reset;
-	-- Test data
-	test("01"); -- up=1, down=0
-	test("00"); -- nothing
-	test("11"); -- nothing
-	test("10"); -- up=0, down=1
-	test("00");
-	clk_en <= '0'; -- disable clock
-	test("10");
-	end_of_sim <= true;
-	WAIT;
-END PROCESS;
-END;
\ No newline at end of file
diff --git a/application/debouncer/debouncer.vhd b/application/debouncer/debouncer.vhd
deleted file mode 100644
index 8dcc02a..0000000
--- a/application/debouncer/debouncer.vhd
+++ /dev/null
@@ -1,63 +0,0 @@
---*******************************
---* TITLE: Debouncer (sender) 	*
---* TYPE: Component 		*
---* AUTHOR: Dylan Van Assche 	*
---* DATE: 28/09/2017 		*
---*******************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- Debouncing the input buttons.
---2)Principle:
--- When detecting 4 clock cycles the same input, data is valid.
---3)Inputs:
--- cha, rst, clk
---4)Outputs:
--- syncha
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-ENTITY debouncer IS
-	PORT
-	(
-		cha, clk, clk_en, rst : IN std_logic;
-		syncha                : OUT std_logic
-	);
-END debouncer;
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE behavior OF debouncer IS
-	SIGNAL reg      : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
-	SIGNAL reg_next : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
-	SIGNAL sh_ldb   : std_logic;
-BEGIN
--- output of the shiftreg asigned to syncha (signal -> output)
-syncha <= reg(0);
--- exor
-sh_ldb <= reg(0) XOR cha;
--- 2-Process: synchronous part
-sync_debouncer : PROCESS (clk)
-BEGIN
-	IF (rising_edge(clk) AND clk_en = '1') THEN
-		IF (rst = '1') THEN -- reset line high, go to initial state
-			reg <= (OTHERS => '0');
-		ELSE -- normal operation
-			reg <= reg_next;
-		END IF;
-	END IF;
-END PROCESS sync_debouncer;
--- 2-Process: combinatoric part
-comb_debouncer : PROCESS (reg, sh_ldb, cha)
-BEGIN
-	IF (sh_ldb = '1') THEN
-		reg_next <= cha & reg(3 DOWNTO 1);
-	ELSE
-		reg_next <= (OTHERS => reg(0));
-	END IF;
-END PROCESS comb_debouncer;
-END behavior;
diff --git a/application/debouncer/debouncer_test.vhd b/application/debouncer/debouncer_test.vhd
deleted file mode 100644
index d81d47d..0000000
--- a/application/debouncer/debouncer_test.vhd
+++ /dev/null
@@ -1,96 +0,0 @@
---***************************************
---* TITLE: Debouncer TESTBENCH (sender) *
---* TYPE: Component 			*
---* AUTHOR: Dylan Van Assche 		*
---* DATE: 01/10/2017 			*
---***************************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- TESTBENCH: Debouncing the input buttons.
---2)Principle:
--- When detecting 4 clock cycles the same input, data is valid.
---3)Inputs:
--- cha, rst, clk
---4)Outputs:
--- syncha
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-USE ieee.std_logic_arith.ALL;
-ENTITY debouncer_test IS
-END debouncer_test;
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE structural OF debouncer_test IS
-	--initialize signals & constants
-	CONSTANT period   : TIME := 100 ns;
-	CONSTANT delay    : TIME := 10 ns;
-	SIGNAL end_of_sim : BOOLEAN := false;
-	SIGNAL clk        : std_logic;
-	SIGNAL clk_en     : std_logic := '1';
-	SIGNAL rst        : std_logic;
-	SIGNAL cha        : std_logic;
-	SIGNAL syncha     : std_logic;
-BEGIN
---***********
---* MAPPING *
---***********
--- Connect ports to signals (PORT => SIGNAL)
-uut : ENTITY work.debouncer(behavior)
-	PORT MAP
-	(
-		clk    => clk,
-		clk_en => clk_en,
-		rst    => rst,
-		cha    => cha,
-		syncha => syncha
-	);
-
--- Only for synchronous components
-clock : PROCESS
-BEGIN
-	clk <= '0';
-	WAIT FOR period/2;
-	LOOP
-	clk <= '0';
-	WAIT FOR period/2;
-	clk <= '1';
-	WAIT FOR period/2;
-	EXIT WHEN end_of_sim;
-	END LOOP;
-	WAIT;
-END PROCESS clock;
--- Testbench
-tb : PROCESS
-	-- Reset procedure to initialize the component
-	PROCEDURE reset IS
-	BEGIN
-		rst <= '1';
-		WAIT FOR period * 2;
-		rst <= '0';
-		WAIT FOR period;
-	END reset;
-	-- Test data procedure
-	PROCEDURE test (CONSTANT testdata : IN std_logic) IS
-	BEGIN
-		cha <= testdata;
-		WAIT FOR period * 4;
-	END test;
-BEGIN
-	-- Reset at startup
-	reset;
-	-- Test data
-	test('0');
-	test('1');
-	test('0');
-	test('1');
-	end_of_sim <= true;
-	WAIT;
-END PROCESS;
-END;
diff --git a/application/edgedetector/edgedetector.vhd b/application/edgedetector/edgedetector.vhd
deleted file mode 100644
index 919fec1..0000000
--- a/application/edgedetector/edgedetector.vhd
+++ /dev/null
@@ -1,69 +0,0 @@
---******************************************************************************
---* TITLE: Edgedetector FSM (sender) *
---* TYPE: Component *
---* AUTHOR: Dylan Van Assche *
---* DATE: 05/10/2017 *
---******************************************************************************
---********************
---* DESCRIPTION *
---********************
---1)Purpose:
--- Check if a signal goes from LOW to HIGH
---2)Principle:
--- Moore FSM
---3)Inputs:
--- data, clk, clk_en, rst
---4)Outputs:
--- puls
---***************************
---* LIBRARIES & ENTITY *
---***************************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-ENTITY edgedetector IS
-	PORT
-	(
-		data, clk, clk_en, rst : IN std_logic;
-		puls                   : OUT std_logic
-	);
-END edgedetector;
---**************************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---**************************************************
-ARCHITECTURE behavior OF edgedetector IS
-	TYPE state IS (s0, s1, s2);
-	SIGNAL present_state, next_state : state;
-BEGIN
--- 2-Process: synchronous part
-sync_moore : PROCESS (clk)
-BEGIN
-	IF (rising_edge(clk) AND clk_en = '1') THEN
-		IF (rst = '1') THEN -- reset line high, go to initial state
-			present_state <= s0;
-		ELSE -- normal operation
-			present_state <= next_state;
-		END IF;
-	END IF;
-END PROCESS sync_moore;
--- 2-Process: combinatoric part
-comb_moore : PROCESS (present_state, data)
-BEGIN
-	CASE present_state IS
-		WHEN s0 => puls <= '0'; -- Initial state
-		IF (data = '1') THEN -- data high, send puls
-			next_state <= s1;
-		ELSE
-			next_state <= s0;
-		END IF;
-		WHEN s1 => puls <= '1'; -- Send puls out (high)
-		next_state      <= s2;
-		WHEN s2 => puls <= '0'; -- After 1 CLK cycle, puls low
-		IF (data = '0') THEN -- data low, go to initial state
-			next_state <= s0;
-		ELSE
-			next_state <= s2;
-		END IF;
-	END CASE;
-END PROCESS comb_moore;
-END behavior;
\ No newline at end of file
diff --git a/application/edgedetector/edgedetector_test.vhd b/application/edgedetector/edgedetector_test.vhd
deleted file mode 100644
index 039bf10..0000000
--- a/application/edgedetector/edgedetector_test.vhd
+++ /dev/null
@@ -1,95 +0,0 @@
---***********************************************
---* TITLE: Edgedetector FSM TESTBENCH (sender) 	*
---* TYPE: Component 				*
---* AUTHOR: Dylan Van Assche 			*
---* DATE: 05/10/2017 				*
---***********************************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- Check if a signal goes from LOW to HIGH
---2)Principle:
--- Moore FSM
---3)Inputs:
--- data, clk, clk_en, rst
---4)Outputs:
--- puls
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-ENTITY edgedetector_test IS
-END edgedetector_test;
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE structural OF edgedetector_test IS
-	--initialize signals & constants
-	CONSTANT period   : TIME := 100 ns;
-	CONSTANT delay    : TIME := 10 ns;
-	SIGNAL end_of_sim : BOOLEAN := false;
-	SIGNAL data       : std_logic;
-	SIGNAL clk        : std_logic;
-	SIGNAL clk_en     : std_logic := '1';
-	SIGNAL rst        : std_logic;
-	SIGNAL puls       : std_logic;
-BEGIN
---***********
---* MAPPING *
---***********
--- Connect ports to signals (PORT => SIGNAL)
-uut : ENTITY work.edgedetector(behavior)
-	PORT MAP
-	(
-		data   => data,
-		puls   => puls,
-		clk    => clk,
-		clk_en => clk_en,
-		rst    => rst
-	);
-
--- Only for synchronous components
-clock : PROCESS
-	BEGIN
-	clk <= '0';
-	WAIT FOR period/2;
-	LOOP
-		clk <= '0';
-		WAIT FOR period/2;
-		clk <= '1';
-		WAIT FOR period/2;
-	EXIT WHEN end_of_sim;
-	END LOOP;
-	WAIT;
-END PROCESS clock;
--- Testbench
-PROCESS
-	-- Reset procedure to initialize the component
-	PROCEDURE reset IS
-	BEGIN
-		rst <= '1';
-		WAIT FOR period * 2;
-		rst <= '0';
-		WAIT FOR period;
-	END reset;
-	-- Test data procedure
-	PROCEDURE test (CONSTANT testdata : IN std_logic) IS
-	BEGIN
-		data <= testdata;
-		WAIT FOR period * 4;
-		END test;
-BEGIN
-	-- Reset at startup
-	reset;
-	-- Test data
-	test('0');
-	test('1');
-	test('0');
-	test('1');
-	end_of_sim <= true;
-	WAIT;
-END PROCESS;
-END structural;
diff --git a/application/segdecoder/segdecoder.vhd b/application/segdecoder/segdecoder.vhd
deleted file mode 100644
index 8591249..0000000
--- a/application/segdecoder/segdecoder.vhd
+++ /dev/null
@@ -1,58 +0,0 @@
---*******************************************************
---* TITLE: Binary-To-7-Segment-Display decoder (sender) *
---* TYPE: Component 					*
---* AUTHOR: Dylan Van Assche 				*
---* DATE: 01/10/2017 					*
---*******************************************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- Convert a 4 bit STD_LOGIC_VECTOR to a 7 segment display output (active low)
---2)Principle:
--- Switch statement converts the binary data to HEX values which are understand by the 7 segment display
---3)Inputs:
--- bin
---4)Outputs:
--- disp_b
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-ENTITY decoder IS
-	PORT
-	(
-		bin    : IN std_logic_vector(3 DOWNTO 0);
-		disp_b : OUT std_logic_vector(6 DOWNTO 0)
-	);
-END decoder;
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE behavior OF decoder IS
-BEGIN
-decode : PROCESS (bin)
-BEGIN
-	CASE bin IS
-		WHEN "0000" => disp_b  <= "0000001"; -- '0'
-		WHEN "0001" => disp_b  <= "1001111"; -- '1'
-		WHEN "0010" => disp_b  <= "0010010"; -- '2'
-		WHEN "0011" => disp_b  <= "0000110"; -- '3'
-		WHEN "0100" => disp_b  <= "1001100"; -- '4'
-		WHEN "0101" => disp_b <= "0100100"; -- '5'
-		WHEN "0110" => disp_b <= "0100000"; -- '6'
-		WHEN "0111" => disp_b <= "0001111"; -- '7'
-		WHEN "1000" => disp_b <= "0000000"; -- '8'
-		WHEN "1001" => disp_b <= "0000100"; -- '9'
-		WHEN "1010" => disp_b <= "0000010"; -- 'A'
-		WHEN "1011" => disp_b <= "1100000"; -- 'B'
-		WHEN "1100" => disp_b <= "0110001"; -- 'C'
-		WHEN "1101" => disp_b <= "1000010"; -- 'D'
-		WHEN "1110" => disp_b <= "0010000"; -- 'E'
-		WHEN "1111" => disp_b <= "0111000"; -- 'F'
-		WHEN OTHERS => disp_b     <= "0000000";
-	END CASE;
-END PROCESS decode;
-END behavior;
diff --git a/application/segdecoder/segdecoder_test.vhd b/application/segdecoder/segdecoder_test.vhd
deleted file mode 100644
index d87ab51..0000000
--- a/application/segdecoder/segdecoder_test.vhd
+++ /dev/null
@@ -1,58 +0,0 @@
---***********************************************************************
---* TITLE: Binary-To-7-Segment-Display decoder TESTBENCH (sender)	*
---* TYPE: Component 							*
---* AUTHOR: Dylan Van Assche						*
---* DATE: 01/10/2017 							*
---***********************************************************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- TESTBENCH: Convert a 4 bit STD_LOGIC_VECTOR to a 7 segment display output (active low)
---2)Principle:
--- Switch statement converts the binary data to HEX values which are understand by the 7 segment display
---3)Inputs:
--- bin
---4)Outputs:
--- disp_b
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-USE ieee.std_logic_arith.ALL;
-ENTITY decoder_test IS
-END decoder_test;
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE structural OF decoder_test IS
-	-- Initialize signals & constants
-	CONSTANT period   : TIME := 100 ns;
-	CONSTANT delay    : TIME := 10 ns;
-	SIGNAL end_of_sim : BOOLEAN := false;
-	SIGNAL bin        : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
-	SIGNAL disp_b     : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
-BEGIN
---***********
---* MAPPING *
---***********
-uut : ENTITY work.decoder(behavior)
-	PORT MAP
-	(
-		bin    => bin,
-		disp_b => disp_b
-	);
-			
--- Testbench
-tb : PROCESS
-BEGIN
-	FOR i IN 0 TO 15 LOOP
-		bin <= CONV_STD_LOGIC_VECTOR(i, 4);
-		WAIT FOR period;
-	END LOOP;
-	end_of_sim <= true;
-	WAIT;
-END PROCESS;
-END;
diff --git a/application/updowncounter/updowncounter.vhd b/application/updowncounter/updowncounter.vhd
deleted file mode 100644
index 7102620..0000000
--- a/application/updowncounter/updowncounter.vhd
+++ /dev/null
@@ -1,61 +0,0 @@
---*******************************
---* TITLE: Counter (sender)	*
---* TYPE: Component 		*
---* AUTHOR: Dylan Van Assche 	*
---* DATE: 01/10/2017 		*
---*******************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- Counting up/down
---2)Principle:
--- When up or down input is high, count
---3)Ingangen:
--- up, down, rst, clk, clk_en
---4)Uitgangen:
--- output
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-ENTITY counter IS
-	PORT
-	(
-		clk, clk_en, rst, up, down : IN std_logic;
-		output                     : OUT std_logic_vector(3 DOWNTO 0)
-	);
-	SIGNAL n_count : std_logic_vector(3 DOWNTO 0);
-	SIGNAL p_count : std_logic_vector(3 DOWNTO 0);
-END;
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE behavior OF counter IS
-BEGIN
-output <= p_count;
--- 2-Process: synchronous part
-count_sync : PROCESS (clk)
-BEGIN
-	IF (rising_edge(clk) AND clk_en = '1') THEN
-		IF (rst = '1') THEN -- rst line high, go to initial state
-			p_count <= (OTHERS => '0');
-		ELSE -- normal operation
-			p_count <= n_count;
-		END IF;
-	END IF;
-END PROCESS count_sync;
--- 2-Process: combinatoric part
-count_comb : PROCESS (p_count, up, down)
-BEGIN
-	IF up = '1' AND down = '0' THEN -- count up
-		n_count <= p_count + 1;
-	ELSIF down = '1' AND up = '0' THEN -- count down
-		n_count <= p_count - 1;
-	ELSE
-		n_count <= p_count; -- halt
-	END IF;
-END PROCESS count_comb;
-END behavior;
\ No newline at end of file
diff --git a/application/updowncounter/updowncounter_test.vhd b/application/updowncounter/updowncounter_test.vhd
deleted file mode 100644
index 6de8dac..0000000
--- a/application/updowncounter/updowncounter_test.vhd
+++ /dev/null
@@ -1,100 +0,0 @@
---***************************************
---* TITLE: Counter TESTBENCH (sender) 	*
---* TYPE: Component 			*
---* AUTHOR: Dylan Van Assche 		*
---* DATE: 01/10/2017 			*
---***************************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- TESTBENCH: Counting up/down
---2)Principle:
--- When up or down input is high, count
---3)Ingangen:
--- up, down, rst, clk, clk_en
---4)Uitgangen:
--- output
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-USE ieee.std_logic_arith.ALL;
-ENTITY counter_test IS
-END counter_test;
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE structural OF counter_test IS
-	--initialize signals & constants
-	CONSTANT period   : TIME := 100 ns;
-	CONSTANT delay    : TIME := 10 ns;
-	SIGNAL end_of_sim : BOOLEAN := false;
-	SIGNAL clk        : std_logic := '0';
-	SIGNAL clk_en     : std_logic := '1';
-	SIGNAL rst        : std_logic := '0';
-	SIGNAL up         : std_logic := '0';
-	SIGNAL down       : std_logic := '0';
-	SIGNAL output     : std_logic_vector(3 DOWNTO 0);
-BEGIN
---***********
---* MAPPING *
---***********
-uut : ENTITY work.counter(behavior)
-	PORT MAP
-	(
-		clk    => clk,
-		clk_en => clk_en,
-		rst    => rst,
-		up     => up,
-		down   => down,
-		output => output
-	);
--- Only for synchronous components
-clock : PROCESS
-BEGIN
-	clk <= '0';
-	WAIT FOR period/2;
-	LOOP
-		clk <= '0';
-		WAIT FOR period/2;
-		clk <= '1';
-		WAIT FOR period/2;
-		EXIT WHEN end_of_sim;
-	END LOOP;
-	WAIT;
-END PROCESS clock;
--- Testbench
-tb : PROCESS
-	-- Reset procedure to initialize the component
-	PROCEDURE reset IS
-	BEGIN
-		rst <= '1';
-		WAIT FOR period * 2;
-		rst <= '0';
-		WAIT FOR period;
-	END reset;
-	-- Test data procedure
-	PROCEDURE test (CONSTANT testdata : IN std_logic_vector(1 DOWNTO 0)) IS
-	BEGIN
-		up   <= testdata(0);
-		down <= testdata(1);
-		WAIT FOR period * 5;
-		END test;
-BEGIN
-	-- Reset at startup
-	reset;
-	-- Test data
-	test("01"); -- up=1, down=0
-	test("00"); -- nothing
-	test("11"); -- nothing
-	test("10"); -- up=0, down=1
-	test("00");
-	clk_en <= '0'; -- disable clock
-	test("10");
-	end_of_sim <= true;
-	WAIT;
-END PROCESS;
-END;
diff --git a/datalink/datalink.vhd b/datalink/datalink.vhd
deleted file mode 100644
index d753b66..0000000
--- a/datalink/datalink.vhd
+++ /dev/null
@@ -1,60 +0,0 @@
---*******************************
---* TITLE: Datalink (sender) 	*
---* TYPE: Component		*
---* AUTHOR: Dylan Van Assche 	*
---* DATE: 25/10/2017 		*
---*******************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- Datalink layer API.
---2)Principle:
--- Provide an API as datalink layer
---3)Inputs:
--- data, pn_start, rst, clk, clk_en
---4)Outputs:
--- output
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-ENTITY datalink_layer IS
-	PORT
-	(
-		clk       : IN std_logic;
-		clk_en    : IN std_logic;
-		rst       : IN std_logic;
-		data      : IN std_logic_vector(3 DOWNTO 0);
-		pn_start  : IN std_logic;
-		output	  : OUT std_logic
-	);
-END datalink_layer;
-ARCHITECTURE behavior OF datalink_layer IS
-	SIGNAL sh_output : std_logic;
-	SIGNAL ld_output : std_logic;
-BEGIN
---components
-sequencecontroller : ENTITY work.sequencecontroller(behavior)
-PORT MAP
-(
-	clk      => clk,
-	clk_en   => clk_en,
-	rst      => rst,
-	pn_start => pn_start,
-	ld       => ld_output,
-	sh       => sh_output
-);
-datareg : ENTITY work.datareg(behavior)
-PORT MAP
-(
-	clk    => clk,
-	clk_en => clk_en,
-	rst    => rst,
-	sh     => sh_output,
-	ld     => ld_output,
-	output => output,
-	data   => data         
-);
-END behavior;
\ No newline at end of file
diff --git a/datalink/datalink_test.vhd b/datalink/datalink_test.vhd
deleted file mode 100644
index d6331a3..0000000
--- a/datalink/datalink_test.vhd
+++ /dev/null
@@ -1,93 +0,0 @@
---***************************************
---* TITLE: Datalink TESTBENCH (sender) 	*
---* TYPE: Top File			*
---* AUTHOR: Dylan Van Assche 		*
---* DATE: 25/10/2017 			*
---***************************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- TESTBENCH: Datalink layer API.
---2)Principle:
--- Provide an API as datalink layer
---3)Inputs:
--- data, pn_start, rst, clk, clk_en
---4)Outputs:
--- output
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-USE ieee.std_logic_arith.ALL;
-ENTITY datalink_layer_test IS
-END datalink_layer_test;
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE structural OF datalink_layer_test IS
-	--initialize signals & constants
-	CONSTANT period   : TIME := 100 ns;
-	CONSTANT delay    : TIME := 10 ns;
-	SIGNAL end_of_sim : BOOLEAN := false;
-	SIGNAL clk        : std_logic := '0';
-	SIGNAL clk_en     : std_logic := '1';
-	SIGNAL rst        : std_logic := '0';
-	SIGNAL data	  : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
-	SIGNAL pn_start   : std_logic := '0';
-	SIGNAL output	  : std_logic := '0';
-BEGIN
---***********
---* MAPPING *
---***********
-uut : ENTITY work.datalink_layer(behavior)
-	PORT MAP
-	(
-		clk       => clk,
-		clk_en    => clk_en,
-		rst       => rst,
-		data	  => data,
-		pn_start  => pn_start,
-		output    => output
-	);
--- Only for synchronous components
-clock : PROCESS
-BEGIN
-	clk <= '0';
-	WAIT FOR period/2;
-	LOOP
-		clk <= '0';
-		WAIT FOR period/2;
-		clk <= '1';
-		WAIT FOR period/2;
-		EXIT WHEN end_of_sim;
-	END LOOP;
-	WAIT;
-	END PROCESS clock;
--- Testbench
-tb : PROCESS
-	-- Reset procedure to initialize the component
-	PROCEDURE reset IS
-	BEGIN
-		rst <= '1';
-		WAIT FOR period * 2;
-		rst <= '0';
-		WAIT FOR period;
-	END reset;
-BEGIN
-	-- Reset at startup
-	reset;
-	-- Test data
-	FOR i IN 0 TO 15 LOOP -- all possible counter values
-		data <= CONV_STD_LOGIC_VECTOR(i, 4); -- counter
-		pn_start <= '1'; -- trigger every 31 periods a PN_START reduced to 5 periods
-		WAIT FOR period*1;
-		pn_start <= '0';
-		WAIT FOR period*5;
-	END LOOP;
-	end_of_sim <= true;
-	WAIT;
-END PROCESS;
-END;
\ No newline at end of file
diff --git a/datalink/datareg/datareg.vhd b/datalink/datareg/datareg.vhd
deleted file mode 100644
index f9a9088..0000000
--- a/datalink/datareg/datareg.vhd
+++ /dev/null
@@ -1,66 +0,0 @@
---***********************************************
---* TITLE: Dataregister (sender)		*
---* TYPE: Component 				*
---* AUTHOR: Dylan Van Assche 			*
---* DATE: 19/10/2017 				*
---***********************************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- Generate serial data output with a preamble and counter data
---2)Principle:
--- When the load signal is received, data is loaded from the counter.
--- When the shift signal is received, data is shifted out (1 place).
---3)Inputs:
--- sh, ld, data, clk, clk_en, rst
---4)Outputs:
--- output
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-
-ENTITY datareg IS
-PORT (
-	sh, ld, clk, clk_en, rst : IN  std_logic; 
-	data                     : IN  std_logic_vector(3 DOWNTO 0);
-	output                   : OUT std_logic
-     );
-END datareg;
-
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE behavior OF datareg IS
-	SIGNAL reg: std_logic_vector(10 DOWNTO 0);
-	SIGNAL reg_next: std_logic_vector(10 DOWNTO 0);
-	CONSTANT preamble: std_logic_vector(6 DOWNTO 0) := "0111110";
-BEGIN
--- connect signal to output
-output <= reg(0);
--- 2-Process: synchronous part
-reg_sync : PROCESS (clk)
-BEGIN
-	IF (rising_edge(clk) AND clk_en = '1') THEN
-		IF (rst = '1') THEN -- rst line high, go to initial state
-			reg <= (OTHERS => '0');
-		ELSE -- normal operation
-			reg <= reg_next;
-		END IF;
-	END IF;
-END PROCESS reg_sync;
--- 2-Process: combinatoric part
-reg_comb : PROCESS(reg, ld, sh)
-BEGIN
-	IF ld = '1' AND sh = '0' THEN -- load data, first preamble to reg(0) then the number of the counter
-		reg_next <= data & preamble;
-	ELSIF ld = '0' AND sh = '1' THEN -- shift data, first preamble to reg(0) then the number of the counter
-		reg_next <= '0' & reg(10 DOWNTO 1); -- Zeros added since load signal will occur as soon as zeros are arrived at the output
-	ELSE -- Input signals wrong!
-		reg_next <= reg;
-	END IF;
-END PROCESS reg_comb;
-END behavior;
\ No newline at end of file
diff --git a/datalink/datareg/datareg_test.vhd b/datalink/datareg/datareg_test.vhd
deleted file mode 100644
index 586dd7a..0000000
--- a/datalink/datareg/datareg_test.vhd
+++ /dev/null
@@ -1,113 +0,0 @@
---***********************************************
---* TITLE: Dataregister TESTBENCH (sender)	*
---* TYPE: Component 				*
---* AUTHOR: Dylan Van Assche 			*
---* DATE: 19/10/2017 				*
---***********************************************
---***************
---* DESCRIPTION *
---***************
---1)Purpose:
--- TESTBENCH: Generate serial data output with a preamble and counter data
---2)Principle:
--- When the load signal is received, data is loaded from the counter.
--- When the shift signal is received, data is shifted out (1 place).
---3)Inputs:
--- sh, ld, data, clk, clk_en, rst
---4)Outputs:
--- output
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-USE ieee.std_logic_arith.ALL;
-ENTITY datareg_test IS
-END datareg_test;
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE structural OF datareg_test IS
-	--initialize signals & constants
-	CONSTANT period   : TIME := 100 ns;
-	CONSTANT delay    : TIME := 10 ns;
-	SIGNAL end_of_sim : BOOLEAN := false;
-	SIGNAL clk        : std_logic := '0';
-	SIGNAL clk_en     : std_logic := '1';
-	SIGNAL rst        : std_logic := '0';
-	SIGNAL sh	  : std_logic := '0';
-	SIGNAL ld         : std_logic := '0';
-	SIGNAL output	  : std_logic := '0';
-	SIGNAL data	  : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); -- counter input
-BEGIN
---***********
---* MAPPING *
---***********
-uut : ENTITY work.datareg(behavior)
-	PORT MAP
-	(
-		clk    => clk,
-		clk_en => clk_en,
-		rst    => rst,
-		sh     => sh,
-		ld     => ld,
-		output => output,
-		data   => data
-	);
--- Only for synchronous components
-clock : PROCESS
-BEGIN
-	clk <= '0';
-	WAIT FOR period/2;
-	LOOP
-		clk <= '0';
-		WAIT FOR period/2;
-		clk <= '1';
-		WAIT FOR period/2;
-		EXIT WHEN end_of_sim;
-	END LOOP;
-	WAIT;
-END PROCESS clock;
--- Testbench
-tb : PROCESS
-	-- Reset procedure to initialize the component
-	PROCEDURE reset IS
-	BEGIN
-		rst <= '1';
-		WAIT FOR period * 2;
-		rst <= '0';
-		WAIT FOR period;
-	END reset;
-	-- Test data procedure
-	PROCEDURE test (CONSTANT testdata : IN std_logic_vector(5 DOWNTO 0)) IS
-	BEGIN
-		data <= testdata(5 DOWNTO 2);
-		ld <= testdata(0);
-		sh <= testdata(1);
-		WAIT FOR period * 1;
-		ld <= '0';
-		sh <= '0';
-		WAIT FOR period * 5; -- normally 31 clock cycles for sequence controller (PN_START)
-	END test;
-BEGIN
-	-- Reset at startup
-	reset;
-	-- Test data
-	FOR counter IN 0 TO 3 LOOP -- 3 cycles with 3 different counter values
-		FOR i IN 0 TO 10 LOOP -- imitate sequencecontroller
-			IF(i = 0) THEN -- load
-				test(CONV_STD_LOGIC_VECTOR(counter, 4) & "01");
-			ELSE -- shift
-				test(CONV_STD_LOGIC_VECTOR(counter, 4) & "10");
-			END IF;
-		END LOOP;
-	END LOOP;
-	clk_en <= '0'; -- disable clock
-	test(CONV_STD_LOGIC_VECTOR(5, 4) & "10");
-	test(CONV_STD_LOGIC_VECTOR(6, 4) & "01");
-	end_of_sim <= true;
-	WAIT;
-END PROCESS;
-END;
-
diff --git a/datalink/sequencecontroller/sequencecontroller.vhd b/datalink/sequencecontroller/sequencecontroller.vhd
deleted file mode 100644
index 9967c32..0000000
--- a/datalink/sequencecontroller/sequencecontroller.vhd
+++ /dev/null
@@ -1,73 +0,0 @@
---***************************************
---* TITLE: Sequencecontroller (sender)	*
---* TYPE: Component 		        *
---* AUTHOR: Dylan Van Assche 		*
---* DATE: 19/10/2017 			*
---***************************************
---* DESCRIPTION *
---***************
---1)Purpose:
--- Controlling the behavior of the dataregister
---2)Principle:
--- When 0, emit load signal. Data is loaded into the register. From 1 to 10 data is shifted by emitting the shift signal.
--- On 10, the counter rests itself and the sequence starts again.
---3)Inputs:
--- clk, clk_en, rst, pn_start
---4)Outputs:
--- ld, sh
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-ENTITY sequencecontroller IS
-	PORT
-	(
-		clk, clk_en, rst, pn_start : IN std_logic;
-		ld, sh                     : OUT std_logic
-	);
-END;
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE behavior OF sequencecontroller IS
-	SIGNAL n_count : std_logic_vector(3 DOWNTO 0);
-	SIGNAL p_count : std_logic_vector(3 DOWNTO 0);
-	SIGNAL ld_next : std_logic;
-	SIGNAL sh_next : std_logic;
-BEGIN
--- 2-Process: synchronous part
-count_sync : PROCESS (clk)
-BEGIN
-	IF (rising_edge(clk) AND clk_en = '1') THEN
-		IF (rst = '1') THEN -- rst line high, go to initial state
-			p_count <= (OTHERS => '0');
-			ld <= '1';
-      			sh <= '0';
-		ELSE -- normal operation
-			p_count <= n_count;
-			ld <= ld_next;
-			sh <= sh_next;
-		END IF;
-	END IF;
-END PROCESS count_sync;
--- 2-Process: combinatoric part
--- 1 LOAD + 10 SHIFTS = counter from 0 to 10
-count_comb : PROCESS (p_count, pn_start)
-BEGIN
-	IF p_count = "1010" AND pn_start = '1' THEN -- When 10, reset (priority)
-		n_count <= "0000";
-		ld_next <= '1';
-    		sh_next <= '0';
-	ELSIF pn_start = '1' THEN -- count up when PN_start is received
-		n_count <= p_count + 1;
-		ld_next <= '0';
-    		sh_next <= '1';
-	ELSE
-		ld_next <= '0';
-    		sh_next <= '0';
-		n_count <= p_count; -- halt
-	END IF;
-END PROCESS count_comb;
-END behavior;
diff --git a/datalink/sequencecontroller/sequencecontroller_test.vhd b/datalink/sequencecontroller/sequencecontroller_test.vhd
deleted file mode 100644
index 2c6a4a7..0000000
--- a/datalink/sequencecontroller/sequencecontroller_test.vhd
+++ /dev/null
@@ -1,100 +0,0 @@
---*******************************************************
---* TITLE: Sequencecontroller TESTBENCH (sender)	*
---* TYPE: Component 					*
---* AUTHOR: Dylan Van Assche 				*
---* DATE: 19/10/2017 					*
---*******************************************************
---* DESCRIPTION *
---***************
---1)Purpose:
--- TESTBENCH: Controlling the behavior of the dataregister
---2)Principle:
--- When 0, emit load signal. Data is loaded into the register. From 1 to 10 data is shifted by emitting the shift signal.
--- On 10, the counter rests itself and the sequence starts again.
---3)Inputs:
--- clk, clk_en, rst, pn_start
---4)Outputs:
--- ld, sh
---**********************
---* LIBRARIES & ENTITY *
---**********************
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.ALL;
-USE ieee.std_logic_arith.ALL;
-ENTITY sequencecontroller_test IS
-END sequencecontroller_test;
---*********************************************
---* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
---*********************************************
-ARCHITECTURE structural OF sequencecontroller_test IS
-	--initialize signals & constants
-	CONSTANT period   : TIME := 100 ns;
-	CONSTANT delay    : TIME := 10 ns;
-	SIGNAL end_of_sim : BOOLEAN := false;
-	SIGNAL clk        : std_logic := '0';
-	SIGNAL clk_en     : std_logic := '1';
-	SIGNAL rst        : std_logic := '0';
-	SIGNAL pn_start   : std_logic := '0';
-	SIGNAL ld         : std_logic :='0';
-	SIGNAL sh         : std_logic :='0';
-BEGIN
---***********
---* MAPPING *
---***********
-uut : ENTITY work.sequencecontroller(behavior)
-	PORT MAP
-	(
-		clk      => clk,
-		clk_en   => clk_en,
-		rst      => rst,
-		pn_start => pn_start,
-		ld       => ld,
-		sh       => sh
-	);
--- Only for synchronous components
-clock : PROCESS
-BEGIN
-	clk <= '0';
-	WAIT FOR period/2;
-	LOOP
-		clk <= '0';
-		WAIT FOR period/2;
-		clk <= '1';
-		WAIT FOR period/2;
-		EXIT WHEN end_of_sim;
-	END LOOP;
-	WAIT;
-END PROCESS clock;
--- Testbench
-tb : PROCESS
-	-- Reset procedure to initialize the component
-	PROCEDURE reset IS
-	BEGIN
-		rst <= '1';
-		WAIT FOR period * 2;
-		rst <= '0';
-		WAIT FOR period;
-	END reset;
-	-- Test data procedure
-	PROCEDURE test IS
-	BEGIN
-		pn_start <= '1';
-		WAIT FOR period * 1;
-		pn_start <= '0';
-		END test;
-BEGIN
-	-- Reset at startup
-	reset;
-	-- Test data
-	FOR i IN 0 TO 11 LOOP -- 12 loops: 1 full cycle + start of the next one
-		test;
-		WAIT FOR period*30; -- 1 period from pn_start + 30 = 31 periods
-	END LOOP;
-	clk_en <= '0'; -- disable clock
-	test;
-	end_of_sim <= true;
-	WAIT;
-END PROCESS;
-END;
-