-
Notifications
You must be signed in to change notification settings - Fork 0
/
12Net_40x30_gen.cpp
428 lines (384 loc) · 17.1 KB
/
12Net_40x30_gen.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
/*
* Copyright 2018 Digital Media Professionals Inc.
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* This source code was generated using DMP-DV700 tools.
*/
#include "12Net_40x30_gen.h"
C12Net_40x30::C12Net_40x30() {
// Empty by design
}
C12Net_40x30::~C12Net_40x30() {
// Empty by design
}
bool C12Net_40x30::Initialize() {
if (!ReserveMemory(16416, 17936)) {
return false;
}
set_num_layers(6);
set_num_output_layers(2);
Layer_0();
Layer_1();
Layer_2();
Layer_3();
Layer_4();
Layer_5();
return true;
}
//Layer_0: Convolution Layer
// ->: conv1
// ->: PReLU1
// ->: pool1
void C12Net_40x30::Layer_0() {
dmp_dv_cmdraw_conv_v0& conf = get_layer(0).conv_conf;
conf.header.size = sizeof(conf);
conf.header.device_type = DMP_DV_DEV_CONV;
conf.header.version = 0;
// Topo: 00000000000000000000000000000001
conf.topo = 0x1; // [31:0] Output Destination of each run, 0 = UBUF, 1 = EXTMEM
// Input Configuration:
conf.w = 30; // Input Width
conf.h = 40; // Input Height
conf.z = 1; // Input Depth
conf.c = 3; // Input Channels
conf.input_buf.mem = io_mem_;
conf.input_buf.offs = 5328;
// Output Configuration:
conf.output_buf.mem = io_mem_;
conf.output_buf.offs = 0;
conf.eltwise_buf.mem = NULL;
conf.eltwise_buf.offs = 0; // Input byte address for elementwise add (0 = UBUF Input Buffer)
conf.output_mode = 0; // 0 = concat, 1 = eltwise add
// Runs Configuration:
// ->1 run(s)
//--------------------------------------------------
//RUN : 0
//--------------------------------------------------
//->: conv1
//->: PReLU1
//->: pool1
conf.run[0].m = 10; // Output Channels
conf.run[0].conv_enable = 1; // 1 = Enabled, 0 = Disabled
conf.run[0].p = 0x3; // Filter Width and Height
conf.run[0].pz = 1; // Filter Depth
conf.run[0].weight_buf.mem = weights_mem_;
conf.run[0].weight_buf.offs = 0;
conf.run[0].weight_fmt = 1; // Weight format (0 = random access blocks, 1 = compact stream, 3 = 8-bit qunatized stream)
conf.run[0].conv_pad = 0x0; // bits [7:0] = left padding, bits [15:8] = right padding, bits [23:16] = top padding, bits [31:24] = bottom padding
conf.run[0].conv_stride = 0x101; // bits [7:0] = X stride, bits [15:8] = Y stride
conf.run[0].conv_dilation = 0x0; // bits [7:0] = X dilation, bits [15:8] = Y dilation
conf.run[0].pool_enable = 1; // 0 = disabled, 1 = max pooling, 2 = average pooling
conf.run[0].pool_size = 0x202; // bits [7:0] = width, bits [15:8] = height
conf.run[0].pool_stride = 0x202; // bits [7:0] = X stride, bits [15:8] = Y stride
conf.run[0].pool_pad = 0x0; // bits [7:0] = left padding, bits [15:8] = right padding, bits [23:16] = top padding, bits [31:24] = bottom padding
conf.run[0].pool_avg_param = 0x0; // Usually set to 1/pool_size^2 in FP16 format when using average pooling (average pooling assumes square size)
conf.run[0].actfunc = 4; // Activation Function: 0 = None, 1 = Tanh, 2 = Leaky ReLU, 3 = Sigmoid, 4 = PReLU, 5 = ELU, 6 = ReLU6
conf.run[0].actfunc_param = 0x0; // Leaky ReLU parameter (NOTE: 0x2E66 is 0.1 in FP16)
conf.run[0].rectifi_en = 0; // Rectification, i.e. max(0, x) (NOTE: Can be applied after non-ReLU activation function)
fpga_layer& layer = get_layer(0);
layer.name = "pool1";
layer.type = LT_CONV;
layer.input_offs = 5328;
layer.output_offs = 0;
layer.output_size = 5320;
layer.input_dim[0] = 30;
layer.input_dim[1] = 40;
layer.input_dim[2] = 3;
layer.input_dim_size = 3;
layer.output_dim[0] = 14;
layer.output_dim[1] = 19;
layer.output_dim[2] = 10;
layer.output_dim_size = 3;
layer.is_output = false;
layer.is_f32_output = false;
layer.is_input_hw_layout = false;
}//end of Layer_0
//Layer_1: Convolution Layer
// ->: conv2
// ->: PReLU2
void C12Net_40x30::Layer_1() {
dmp_dv_cmdraw_conv_v0& conf = get_layer(1).conv_conf;
conf.header.size = sizeof(conf);
conf.header.device_type = DMP_DV_DEV_CONV;
conf.header.version = 0;
// Topo: 00000000000000000000000000000001
conf.topo = 0x1; // [31:0] Output Destination of each run, 0 = UBUF, 1 = EXTMEM
// Input Configuration:
conf.w = 14; // Input Width
conf.h = 19; // Input Height
conf.z = 1; // Input Depth
conf.c = 10; // Input Channels
conf.input_buf.mem = io_mem_;
conf.input_buf.offs = 0;
// Output Configuration:
conf.output_buf.mem = io_mem_;
conf.output_buf.offs = 11408;
conf.eltwise_buf.mem = NULL;
conf.eltwise_buf.offs = 0; // Input byte address for elementwise add (0 = UBUF Input Buffer)
conf.output_mode = 0; // 0 = concat, 1 = eltwise add
// Runs Configuration:
// ->1 run(s)
//--------------------------------------------------
//RUN : 0
//--------------------------------------------------
//->: conv2
//->: PReLU2
conf.run[0].m = 16; // Output Channels
conf.run[0].conv_enable = 1; // 1 = Enabled, 0 = Disabled
conf.run[0].p = 0x3; // Filter Width and Height
conf.run[0].pz = 1; // Filter Depth
conf.run[0].weight_buf.mem = weights_mem_;
conf.run[0].weight_buf.offs = 1504;
conf.run[0].weight_fmt = 1; // Weight format (0 = random access blocks, 1 = compact stream, 3 = 8-bit qunatized stream)
conf.run[0].conv_pad = 0x0; // bits [7:0] = left padding, bits [15:8] = right padding, bits [23:16] = top padding, bits [31:24] = bottom padding
conf.run[0].conv_stride = 0x101; // bits [7:0] = X stride, bits [15:8] = Y stride
conf.run[0].conv_dilation = 0x0; // bits [7:0] = X dilation, bits [15:8] = Y dilation
conf.run[0].pool_enable = 0; // 0 = disabled, 1 = max pooling, 2 = average pooling
conf.run[0].pool_size = 0x0; // bits [7:0] = width, bits [15:8] = height
conf.run[0].pool_stride = 0x101; // bits [7:0] = X stride, bits [15:8] = Y stride
conf.run[0].pool_pad = 0x0; // bits [7:0] = left padding, bits [15:8] = right padding, bits [23:16] = top padding, bits [31:24] = bottom padding
conf.run[0].pool_avg_param = 0x0; // Usually set to 1/pool_size^2 in FP16 format when using average pooling (average pooling assumes square size)
conf.run[0].actfunc = 4; // Activation Function: 0 = None, 1 = Tanh, 2 = Leaky ReLU, 3 = Sigmoid, 4 = PReLU, 5 = ELU, 6 = ReLU6
conf.run[0].actfunc_param = 0x0; // Leaky ReLU parameter (NOTE: 0x2E66 is 0.1 in FP16)
conf.run[0].rectifi_en = 0; // Rectification, i.e. max(0, x) (NOTE: Can be applied after non-ReLU activation function)
fpga_layer& layer = get_layer(1);
layer.name = "conv2";
layer.type = LT_CONV;
layer.input_offs = 0;
layer.output_offs = 11408;
layer.output_size = 6528;
layer.input_dim[0] = 14;
layer.input_dim[1] = 19;
layer.input_dim[2] = 10;
layer.input_dim_size = 3;
layer.output_dim[0] = 12;
layer.output_dim[1] = 17;
layer.output_dim[2] = 16;
layer.output_dim_size = 3;
layer.is_output = false;
layer.is_f32_output = false;
layer.is_input_hw_layout = true;
}//end of Layer_1
//Layer_2: Convolution Layer
// ->: conv3
// ->: PReLU3
void C12Net_40x30::Layer_2() {
dmp_dv_cmdraw_conv_v0& conf = get_layer(2).conv_conf;
conf.header.size = sizeof(conf);
conf.header.device_type = DMP_DV_DEV_CONV;
conf.header.version = 0;
// Topo: 00000000000000000000000000000001
conf.topo = 0x1; // [31:0] Output Destination of each run, 0 = UBUF, 1 = EXTMEM
// Input Configuration:
conf.w = 12; // Input Width
conf.h = 17; // Input Height
conf.z = 1; // Input Depth
conf.c = 16; // Input Channels
conf.input_buf.mem = io_mem_;
conf.input_buf.offs = 11408;
// Output Configuration:
conf.output_buf.mem = io_mem_;
conf.output_buf.offs = 1808;
conf.eltwise_buf.mem = NULL;
conf.eltwise_buf.offs = 0; // Input byte address for elementwise add (0 = UBUF Input Buffer)
conf.output_mode = 0; // 0 = concat, 1 = eltwise add
// Runs Configuration:
// ->1 run(s)
//--------------------------------------------------
//RUN : 0
//--------------------------------------------------
//->: conv3
//->: PReLU3
conf.run[0].m = 32; // Output Channels
conf.run[0].conv_enable = 1; // 1 = Enabled, 0 = Disabled
conf.run[0].p = 0x3; // Filter Width and Height
conf.run[0].pz = 1; // Filter Depth
conf.run[0].weight_buf.mem = weights_mem_;
conf.run[0].weight_buf.offs = 6176;
conf.run[0].weight_fmt = 1; // Weight format (0 = random access blocks, 1 = compact stream, 3 = 8-bit qunatized stream)
conf.run[0].conv_pad = 0x0; // bits [7:0] = left padding, bits [15:8] = right padding, bits [23:16] = top padding, bits [31:24] = bottom padding
conf.run[0].conv_stride = 0x101; // bits [7:0] = X stride, bits [15:8] = Y stride
conf.run[0].conv_dilation = 0x0; // bits [7:0] = X dilation, bits [15:8] = Y dilation
conf.run[0].pool_enable = 0; // 0 = disabled, 1 = max pooling, 2 = average pooling
conf.run[0].pool_size = 0x0; // bits [7:0] = width, bits [15:8] = height
conf.run[0].pool_stride = 0x101; // bits [7:0] = X stride, bits [15:8] = Y stride
conf.run[0].pool_pad = 0x0; // bits [7:0] = left padding, bits [15:8] = right padding, bits [23:16] = top padding, bits [31:24] = bottom padding
conf.run[0].pool_avg_param = 0x0; // Usually set to 1/pool_size^2 in FP16 format when using average pooling (average pooling assumes square size)
conf.run[0].actfunc = 4; // Activation Function: 0 = None, 1 = Tanh, 2 = Leaky ReLU, 3 = Sigmoid, 4 = PReLU, 5 = ELU, 6 = ReLU6
conf.run[0].actfunc_param = 0x0; // Leaky ReLU parameter (NOTE: 0x2E66 is 0.1 in FP16)
conf.run[0].rectifi_en = 0; // Rectification, i.e. max(0, x) (NOTE: Can be applied after non-ReLU activation function)
fpga_layer& layer = get_layer(2);
layer.name = "conv3";
layer.type = LT_CONV;
layer.input_offs = 11408;
layer.output_offs = 1808;
layer.output_size = 9600;
layer.input_dim[0] = 12;
layer.input_dim[1] = 17;
layer.input_dim[2] = 16;
layer.input_dim_size = 3;
layer.output_dim[0] = 10;
layer.output_dim[1] = 15;
layer.output_dim[2] = 32;
layer.output_dim_size = 3;
layer.is_output = false;
layer.is_f32_output = false;
layer.is_input_hw_layout = true;
}//end of Layer_2
//Layer_3: Convolution Layer
// ->: conv4-1
void C12Net_40x30::Layer_3() {
dmp_dv_cmdraw_conv_v0& conf = get_layer(3).conv_conf;
conf.header.size = sizeof(conf);
conf.header.device_type = DMP_DV_DEV_CONV;
conf.header.version = 0;
// Topo: 00000000000000000000000000000001
conf.topo = 0x1; // [31:0] Output Destination of each run, 0 = UBUF, 1 = EXTMEM
// Input Configuration:
conf.w = 10; // Input Width
conf.h = 15; // Input Height
conf.z = 1; // Input Depth
conf.c = 32; // Input Channels
conf.input_buf.mem = io_mem_;
conf.input_buf.offs = 1808;
// Output Configuration:
conf.output_buf.mem = io_mem_;
conf.output_buf.offs = 0;
conf.eltwise_buf.mem = NULL;
conf.eltwise_buf.offs = 0; // Input byte address for elementwise add (0 = UBUF Input Buffer)
conf.output_mode = 0; // 0 = concat, 1 = eltwise add
// Runs Configuration:
// ->1 run(s)
//--------------------------------------------------
//RUN : 0
//--------------------------------------------------
//->: conv4-1
conf.run[0].m = 2; // Output Channels
conf.run[0].conv_enable = 1; // 1 = Enabled, 0 = Disabled
conf.run[0].p = 0x1; // Filter Width and Height
conf.run[0].pz = 1; // Filter Depth
conf.run[0].weight_buf.mem = weights_mem_;
conf.run[0].weight_buf.offs = 15520;
conf.run[0].weight_fmt = 1; // Weight format (0 = random access blocks, 1 = compact stream, 3 = 8-bit qunatized stream)
conf.run[0].conv_pad = 0x0; // bits [7:0] = left padding, bits [15:8] = right padding, bits [23:16] = top padding, bits [31:24] = bottom padding
conf.run[0].conv_stride = 0x101; // bits [7:0] = X stride, bits [15:8] = Y stride
conf.run[0].conv_dilation = 0x0; // bits [7:0] = X dilation, bits [15:8] = Y dilation
conf.run[0].pool_enable = 0; // 0 = disabled, 1 = max pooling, 2 = average pooling
conf.run[0].pool_size = 0x0; // bits [7:0] = width, bits [15:8] = height
conf.run[0].pool_stride = 0x101; // bits [7:0] = X stride, bits [15:8] = Y stride
conf.run[0].pool_pad = 0x0; // bits [7:0] = left padding, bits [15:8] = right padding, bits [23:16] = top padding, bits [31:24] = bottom padding
conf.run[0].pool_avg_param = 0x0; // Usually set to 1/pool_size^2 in FP16 format when using average pooling (average pooling assumes square size)
conf.run[0].actfunc = 0; // Activation Function: 0 = None, 1 = Tanh, 2 = Leaky ReLU, 3 = Sigmoid, 4 = PReLU, 5 = ELU, 6 = ReLU6
conf.run[0].actfunc_param = 0x0; // Leaky ReLU parameter (NOTE: 0x2E66 is 0.1 in FP16)
conf.run[0].rectifi_en = 0; // Rectification, i.e. max(0, x) (NOTE: Can be applied after non-ReLU activation function)
fpga_layer& layer = get_layer(3);
layer.name = "conv4-1";
layer.type = LT_CONV;
layer.input_offs = 1808;
layer.output_offs = 0;
layer.output_size = 600;
layer.input_dim[0] = 10;
layer.input_dim[1] = 15;
layer.input_dim[2] = 32;
layer.input_dim_size = 3;
layer.output_dim[0] = 10;
layer.output_dim[1] = 15;
layer.output_dim[2] = 2;
layer.output_dim_size = 3;
layer.is_output = false;
layer.is_f32_output = false;
layer.is_input_hw_layout = true;
}//end of Layer_3
//Layer_4: SoftMax Layer
// ->: prob1
void C12Net_40x30::Layer_4() {
fpga_layer& layer = get_layer(4);
layer.name = "prob1";
layer.type = LT_SOFTMAX;
layer.input_offs = 0;
layer.output_offs = 1200;
layer.output_size = 600;
layer.input_dim[0] = 10;
layer.input_dim[1] = 15;
layer.input_dim[2] = 2;
layer.input_dim_size = 3;
layer.output_dim[0] = 10;
layer.output_dim[1] = 15;
layer.output_dim[2] = 2;
layer.output_dim_size = 3;
layer.is_output = true;
layer.is_f32_output = false;
layer.is_input_hw_layout = true;
layer.softmax_axis = 2;
output_layers_[0] = &layer;
}//end of Layer_4
//Layer_5: Convolution Layer
// ->: conv4-2
void C12Net_40x30::Layer_5() {
dmp_dv_cmdraw_conv_v0& conf = get_layer(5).conv_conf;
conf.header.size = sizeof(conf);
conf.header.device_type = DMP_DV_DEV_CONV;
conf.header.version = 0;
// Topo: 00000000000000000000000000000001
conf.topo = 0x1; // [31:0] Output Destination of each run, 0 = UBUF, 1 = EXTMEM
// Input Configuration:
conf.w = 10; // Input Width
conf.h = 15; // Input Height
conf.z = 1; // Input Depth
conf.c = 32; // Input Channels
conf.input_buf.mem = io_mem_;
conf.input_buf.offs = 1808;
// Output Configuration:
conf.output_buf.mem = io_mem_;
conf.output_buf.offs = 0;
conf.eltwise_buf.mem = NULL;
conf.eltwise_buf.offs = 0; // Input byte address for elementwise add (0 = UBUF Input Buffer)
conf.output_mode = 0; // 0 = concat, 1 = eltwise add
// Runs Configuration:
// ->1 run(s)
//--------------------------------------------------
//RUN : 0
//--------------------------------------------------
//->: conv4-2
conf.run[0].m = 4; // Output Channels
conf.run[0].conv_enable = 1; // 1 = Enabled, 0 = Disabled
conf.run[0].p = 0x1; // Filter Width and Height
conf.run[0].pz = 1; // Filter Depth
conf.run[0].weight_buf.mem = weights_mem_;
conf.run[0].weight_buf.offs = 15824;
conf.run[0].weight_fmt = 1; // Weight format (0 = random access blocks, 1 = compact stream, 3 = 8-bit qunatized stream)
conf.run[0].conv_pad = 0x0; // bits [7:0] = left padding, bits [15:8] = right padding, bits [23:16] = top padding, bits [31:24] = bottom padding
conf.run[0].conv_stride = 0x101; // bits [7:0] = X stride, bits [15:8] = Y stride
conf.run[0].conv_dilation = 0x0; // bits [7:0] = X dilation, bits [15:8] = Y dilation
conf.run[0].pool_enable = 0; // 0 = disabled, 1 = max pooling, 2 = average pooling
conf.run[0].pool_size = 0x0; // bits [7:0] = width, bits [15:8] = height
conf.run[0].pool_stride = 0x101; // bits [7:0] = X stride, bits [15:8] = Y stride
conf.run[0].pool_pad = 0x0; // bits [7:0] = left padding, bits [15:8] = right padding, bits [23:16] = top padding, bits [31:24] = bottom padding
conf.run[0].pool_avg_param = 0x0; // Usually set to 1/pool_size^2 in FP16 format when using average pooling (average pooling assumes square size)
conf.run[0].actfunc = 0; // Activation Function: 0 = None, 1 = Tanh, 2 = Leaky ReLU, 3 = Sigmoid, 4 = PReLU, 5 = ELU, 6 = ReLU6
conf.run[0].actfunc_param = 0x0; // Leaky ReLU parameter (NOTE: 0x2E66 is 0.1 in FP16)
conf.run[0].rectifi_en = 0; // Rectification, i.e. max(0, x) (NOTE: Can be applied after non-ReLU activation function)
fpga_layer& layer = get_layer(5);
layer.name = "dmp_conv_flat_0";
layer.type = LT_CONV;
layer.input_offs = 1808;
layer.output_offs = 0;
layer.output_size = 1200;
layer.input_dim[0] = 10;
layer.input_dim[1] = 15;
layer.input_dim[2] = 32;
layer.input_dim_size = 3;
layer.output_dim[0] = 600;
layer.output_dim_size = 1;
layer.is_output = true;
layer.is_f32_output = false;
layer.is_input_hw_layout = true;
output_layers_[1] = &layer;
}//end of Layer_5