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scs_and_clock_init.list
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scs_and_clock_init.list
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COMPILATION LISTING OF SEGMENT scs_and_clock_init
Compiled by: Multics PL/I Compiler, Release 32f, of October 9, 1989
Compiled at: Bull HN, Phoenix AZ, System-M
Compiled on: 11/11/89 0949.8 mst Sat
Options: optimize map
1 /****^ ***********************************************************
2* * *
3* * Copyright, (C) Honeywell Bull Inc., 1987 *
4* * *
5* * Copyright, (C) Honeywell Information Systems Inc., 1982 *
6* * *
7* * Copyright (c) 1972 by Massachusetts Institute of *
8* * Technology and Honeywell Information Systems, Inc. *
9* * *
10* *********************************************************** */
11
12
13
14
15 /****^ HISTORY COMMENTS:
16* 1) change(86-05-13,GJohnson), approve(86-05-13,MCR7387),
17* audit(86-05-13,Martinson), install(86-05-14,MR12.0-1056):
18* Correct error message documentation.
19* 2) change(87-10-19,Farley), approve(88-02-26,MCR7795),
20* audit(88-03-03,Fawcett), install(88-03-15,MR12.2-1035):
21* Changed early setting of sys_info$time_zone and constant to a default
22* setting from the MST in sys_boot_info$default_time_zone and constant.
23* END HISTORY COMMENTS */
24
25
26 /* format: style2 */
27
28 scs_and_clock_init:
29 procedure ();
30
31 /* * SCS_AND_CLOCK_INIT
32* *
33* * Initialize preliminary scs variables and the Calendar Clock Software.
34* *
35* * Modified 11/73, RE Mullen, converted to v2pl1
36* * Modified 02/02/76, Noel I. Morris, for reasons unknown.
37* * Modified 11/28/80 W. Olin Sibert, to check operation of clock (code moved
38* * from init_pvt), and crash if no CLOK card.
39* * Modified 01/07/81, WOS, to move some initializations from scs.cds to here.
40* Modified 9/03/80 by J. A. Bush for the DPS8/70M CPU
41* Modified January 1981 by C. Hornig to init proc. start int. cell.
42* Modified January 1982 by J. A. Bush to set RSW2 compare masks for cpu type
43* and DPS8M interlace info bits
44* Modified April 1982 by J. Bongiovanni to read all switches (0 through 4)
45* Cleaned up in '82 for bootload Multics.
46* Modified September 1983, Keith Loepere to make early scas paged.
47* Modified August 1984, JAFalksen to initialize time_defaults
48* Modified January 1985, Keith Loepere, to move date/time powerup into paged
49* initialization.
50* */
51
52 /* Variables */
53
54 dcl base fixed bin (17); /* base address of controller */
55 dcl early_call bit (1) aligned; /* Whether this is the first time */
56 dcl enabled bit (1) aligned; /* processor port enabled bit */
57 dcl idx fixed bin (3); /* iteration variable */
58 dcl interlace fixed bin (3); /* memory interlace type */
59 dcl lang_index fixed bin; /* for looking up time zone */
60 dcl malfunction char (40) varying; /* A complaint about the clock */
61 dcl max_scu fixed bin; /* max number of SCUs - 1 -- depends on sys type */
62 dcl new_scas_sdw fixed bin (71);
63 dcl old_scas_sdw fixed bin (71);
64 dcl port fixed bin (3); /* bootload processor port */
65 dcl size fixed bin (17); /* size of controller */
66 dcl scs_size fixed bin;
67 dcl 1 sdwi aligned like sdw_info;
68 dcl time_later fixed bin (71); /* For checking the clock */
69 dcl time_now fixed bin (71); /* For checking the clock */
70 dcl zone_index fixed bin; /* for looking up time zone */
71
72 /* Based */
73
74 dcl based_scs (scs_size) bit (36) aligned based;
75 /* Overlay for clearing */
76
77 /* Entries */
78
79 dcl absadr entry (ptr, fixed bin (35)) returns (fixed bin (26));
80 dcl config_$find entry (char (4) aligned, ptr);
81 dcl date_time_$set_time_defaults
82 entry;
83 dcl mask_instruction$ldaq entry returns (bit (36) aligned);
84 dcl mask_instruction$staq entry returns (bit (36) aligned);
85 dcl pmut$rsw entry (fixed bin, bit (36) aligned);
86 dcl pmut$swap_sdw entry (pointer, pointer);
87 dcl prds_init entry (ptr, fixed bin (3), ptr);
88 dcl ptw_util_$make_core entry (ptr, fixed bin (26));
89 dcl rsw_util$port_info entry (fixed bin (3), bit (1) aligned, fixed bin (17), fixed bin (17),
90 fixed bin (3));
91 dcl scr_util$read_cfg entry (fixed bin (3));
92 dcl sdw_util_$construct entry (pointer, pointer);
93 dcl syserr entry options (variable);
94
95 /* External */
96
97 dcl dseg$ (0:1023) fixed bin (71) external static;
98 dcl prds$ fixed bin external static;
99 dcl prds$simulated_mask fixed bin (71) external static;
100 dcl scas$ fixed bin external static;
101 dcl scs$end_of_scs fixed bin external static;
102 dcl scs$start_of_scs fixed bin external static;
103 dcl sys_boot_info$default_time_zone
104 char (4) unaligned external static;
105 dcl sys_boot_info$default_time_zone_delta
106 fixed bin (71) external static;
107 dcl sys_info$clock_ bit (36) aligned external static;
108 dcl sys_info$time_correction_constant
109 fixed bin (71) external static;
110 dcl sys_info$time_zone char (4) aligned external static;
111
112 /* Constants */
113
114 dcl WHOAMI char (32) internal static init ("scs_and_clock_init");
115
116 /* Misc */
117
118 dcl (addr, baseno, binary, bit, clock, length, null, unspec, wordno)
119 builtin;
120
121
122 /* This entrypoint does no less than the normal entrypoint -- in fact, a bit */
123 /* more. It fills in the port on the CPU config card. */
124
125 scs_and_clock_init$early:
126 entry ();
127
128 early_call = "1"b;
129 goto INIT_COMMON;
130
131
132 scs_and_clock_init$normal:
133 entry ();
134
135 early_call = "0"b;
136 goto INIT_COMMON;
137
138 INIT_COMMON: /* First, initialize data in the SCS. This used to be done by scs.cds
139* when the segment was created, but now that it gets created more than once,
140* this data must be set each time.
141* */
142 scs_size = wordno (addr (scs$end_of_scs)) - wordno (addr (scs$start_of_scs)) + 1;
143 unspec (addr (scs$start_of_scs) -> based_scs) = ""b;
144 /* Clear it out */
145
146 scs$idle_aptep (*) = null ();
147
148 do port = 0 to 7;
149 scs$port_addressing_word (port) = bit (binary (port, 3));
150 end;
151
152
153 /* Next, figure out some things about our CPU, necessarily the bootload CPU */
154 /* Read switches 1 and 2 into the scs safestore area, to be later used by scas_init */
155
156 call pmut$rsw (0, scs$processor_switch_data (0));
157 call pmut$rsw (1, scs$processor_switch_data (1));
158 call pmut$rsw (2, scs$processor_switch_data (2));
159
160 /* Get our processor tag (necessarily the bootload CPU) from switches. */
161
162 rswp = addr (scs$processor_switch_data (2)); /* Set pointer to info. */
163 scs$bos_processor_tag = dps_rsw_2.cpu_num; /* Remember our CPU tag. */
164 if dps8_rsw_2.cpu_type > 0
165 then /* if DPS8 CPU... */
166 max_scu = 3; /* can be only 4 scus */
167 else do; /* DPS or L68 CPU */
168 max_scu = 7; /* 8 possible SCUs */
169
170 /* read switches 3 and 4 if DPS or L68 CPU */
171
172 call pmut$rsw (3, scs$processor_switch_data (3));
173 call pmut$rsw (4, scs$processor_switch_data (4));
174 end;
175
176 if early_call
177 then do; /* Make a CPU card */
178 cpu_cardp = null ();
179 call config_$find (CPU_CARD_WORD, cpu_cardp);
180 /* Guaranteed to be there */
181
182 cpu_card.tag = scs$bos_processor_tag + 1;
183 end;
184
185 call prds_init (addr (prds$), scs$bos_processor_tag, null ());
186 /* Fill in variables in the prds, too. */
187 rswp = addr (scs$processor_switch_mask (2)); /* Get pointer to mask for checking processor switches. */
188 dps_rsw_2.fault_base = "1111111"b; /* Compare the fault base switches. */
189 dps_rsw_2.cpu_num = 7; /* Compare the processor number. */
190 dps_rsw_2.cpu_type = 3; /* Compare cpu types */
191 dps8_rsw_2.interlace_info (*) = "1"b; /* and dps8 interlace bits */
192
193
194 /* Initialize controller mask instructions and pointers. */
195
196 do port = 0 to 7; /* Set up dummy read and set mask instructions. */
197 scs$read_mask (port) = mask_instruction$ldaq ();
198 scs$set_mask (port) = mask_instruction$staq ();
199 scs$mask_ptr (port) = addr (prds$simulated_mask);
200 /* Set pointer to dummy mask. */
201 end; /* Set up processor start interrupt for cell 0 */
202
203 scs$processor_start_int_no = 0;
204 scs$processor_start_pattern = "400000000000"b3;
205 scs$processor_start_mask = "400000000000000000000000"b3;
206
207 scs$number_of_masks = 3;
208
209
210 /* Find the low-order system controller. */
211
212 do port = 0 to max_scu; /* Search for low-order controller. */
213 call rsw_util$port_info (port, enabled, base, size, interlace);
214 /* Get info for this processor port. */
215 if enabled & (base = 0)
216 then do; /* If this is low-order port ... */
217 scs$interrupt_controller = port; /* Save the port number. */
218 sys_info$clock_ = bit (scs$interrupt_controller);
219 /* Set indirect word for reading clock. */
220 goto FOUND_LOW_SCU; /* Now we can use the clock builtin with impunity, */
221 end; /* since sys_info contains appropriate defaults for */
222 end; /* time_correction_constant (zero, that is) */
223
224 call syserr (CRASH, "^a: No SCU port is assigned address zero.", WHOAMI);
225
226 FOUND_LOW_SCU:
227 if early_call
228 then do; /* Fix up the MEM card */
229
230 /* We must make the SCAS pseudo-operative in order to be able to call scr_util
231* to find out about ports. To this end, we make its SDW temporarily describe
232* the first (max_scu + 1) pages of memory, by simply constructing an SDW for
233* it. */
234
235 unspec (sdwi) = ""b;
236 sdwi.flags.paged = "1"b;
237 sdwi.size = 1024 * (max_scu + 1);
238 sdwi.read = "1"b;
239 sdwi.write = "1"b;
240 sdwi.address = absadr (addr (scs$scas_page_table), (0));
241 do idx = 0 to max_scu;
242 call ptw_util_$make_core (addr (scs$scas_page_table (idx)), idx * 1024);
243 end;
244 call sdw_util_$construct (addr (new_scas_sdw), addr (sdwi));
245
246 old_scas_sdw = dseg$ (binary (baseno (addr (scas$)), 18));
247 call pmut$swap_sdw (addr (scas$), addr (new_scas_sdw));
248
249 mem_cardp = null ();
250 call config_$find (MEM_CARD_WORD, mem_cardp);
251 /* Guaranteed to be there */
252 mem_card.tag = 1 + port;
253
254 call scr_util$read_cfg (port); /* Initialize its info */
255 cpu_card.port = scs$controller_data (port).mask_assignment (1);
256
257 unspec (scs$controller_data (port)) = ""b;
258 /* Clear it out to avoid confusing */
259 unspec (scs$cfg_data (port)) = ""b; /* scas_init later on */
260
261 call pmut$swap_sdw (addr (scas$), addr (old_scas_sdw));
262 /* Restore the old SDW */
263 end;
264
265 if sys_info$collection_1_phase = SERVICE_INITIALIZATION
266 then do;
267 time_now = clock (); /* Prepare to see whether the clock is working */
268 do idx = 1 to 10 while (7 ^= 3); /* Waste a few microseconds */
269 end;
270
271 time_later = clock ();
272
273 malfunction = ""; /* Figure out what to say about it */
274 if time_later < time_now
275 then malfunction = "is running backwards!";
276 else if time_later = time_now
277 then malfunction = "is stopped.";
278 else if time_later < (time_now + 10)
279 then /* Must take at least ten microseconds */
280 malfunction = "is running too slowly.";
281 else if time_later > (time_now + 1000)
282 then /* And not more than 1000 */
283 malfunction = "is running too fast.";
284
285 if length (malfunction) > 0
286 then call syserr (CRASH, "^a: SCU clock on port ^o ^a.", WHOAMI, scs$interrupt_controller,
287 malfunction);
288 end;
289
290 /* Set up the clock with default data. The correct time zone gets set later. */
291
292 sys_info$time_zone = sys_boot_info$default_time_zone;
293 sys_info$time_correction_constant = sys_boot_info$default_time_zone_delta;
294
295 return; /* init_clocks will later set all the clocks */
296
297 date_time:
298 entry;
299
300 /* set up the date time software. */
301
302
303 /* Now set up the rest of the info for clock reading */
304
305 clok_cardp = null ();
306 call config_$find (CLOK_CARD_WORD, clok_cardp); /* Look for CLOK config card. */
307 if clok_cardp = null ()
308 then if sys_info$collection_1_phase = SERVICE_INITIALIZATION
309 then call syserr (CRASH, "^a: No CLOK card.", WHOAMI);
310 else do;
311 sys_info$time_zone = sys_boot_info$default_time_zone;
312 sys_info$time_correction_constant = sys_boot_info$default_time_zone_delta;
313 end;
314 else do;
315 sys_info$time_zone = clok_card.zone; /* use values from config card */
316 do lang_index = 1 to ti_zone.number_lang;
317 do zone_index = 1 to ti_zone.number_zone;
318 if ti_zone.short (lang_index, zone_index) = clok_card.zone
319 then go to found_zone;
320 end;
321 end;
322 call syserr (CRASH, "^a: The zone on the CLOK card is not in time_info_.", WHOAMI);
323 found_zone:
324 sys_info$time_correction_constant = ti_zone.delta (lang_index, zone_index);
325 end;
326
327 call date_time_$set_time_defaults; /* power up! */
328 return;
329
330 /* format: off */
331 /* BEGIN include file collection_1_phases.incl.pl1 */
1 2
1 3 /* Symbolic names for the various collection1 phases.
1 4*Keith Loepere, October 1983. */
1 5
1 6 /* format: style4,indattr,ifthenstmt,ifthen,idind33,^indcomtxt */
1 7
1 8 dcl sys_info$collection_1_phase fixed bin external static;
1 9
1 10 dcl EARLY_INITIALIZATION fixed bin init (1) static options (constant); /* phase to find the config deck */
1 11 dcl BOOT_INITIALIZATION fixed bin init (2) static options (constant); /* phase to setup up crash handler, bce */
1 12 dcl SERVICE_INITIALIZATION fixed bin init (3) static options (constant); /* phase to set up for service */
1 13
1 14 /* These first 3 (EARLY, BOOT and SERVICE) must be 1, 2, 3 in that order so
1 15*programs can simply tell apart the booting phases from all others (crash or
1 16*recovery type phases). */
1 17
1 18 dcl CRASH_INITIALIZATION fixed bin init (4) static options (constant); /* phase to set up bce after crash/shut down */
1 19 dcl RE_EARLY_INITIALIZATION fixed bin init (5) static options (constant); /* retry boot initialization given safe config to a new early level */
1 20 dcl BCE_CRASH_INITIALIZATION fixed bin init (6) static options (constant); /* retry boot initialization to give a new boot level given a crash of bce */
1 21 dcl SHUT_INITIALIZATION fixed bin init (7) static options (constant); /* same as boot but don't load new disk mpcs */
1 22
1 23 dcl COLLECTION_1_PHASE_NAMES (7) char (16) unal static options (constant) init
1 24 ("early", "boot", "service", "crash", "re_early", "bce_crash", "shut");
1 25
1 26 /* END include file collection_1_phases.incl.pl1 */
331
332 /* BEGIN INCLUDE FILE ... config_clok_card.incl.pl1 ... 11/27/80 W. Olin Sibert */
2 2
2 3 dcl clok_cardp pointer; /* pointer to CLOK card */
2 4
2 5 dcl 1 clok_card aligned based (clok_cardp), /* CLOK card declaration */
2 6 2 word char (4), /* "clok" */
2 7 2 delta fixed bin, /* Signed offset from GMT */
2 8 2 zone char (4), /* Name of time zone, such as "hfe" */
2 9 2 boot_delta fixed bin, /* Number of hours allowed between bootloads */
2 10
2 11 2 pad (11) bit (36) aligned, /* Pad to 15 fields */
2 12
2 13 2 type_word aligned,
2 14 3 field_type (14) bit (2) unaligned, /* type of each field; see config_deck.incl.pl1 */
2 15 3 pad1 bit (4) unaligned,
2 16 3 n_fields fixed bin (4) unsigned unaligned; /* number of fields used on card */
2 17
2 18 dcl CLOK_CARD_WORD char (4) aligned internal static options (constant) init ("clok");
2 19
2 20 /* END INCLUDE FILE ... config_clok_card.incl.pl1 */
332
333 /* BEGIN INCLUDE FILE ... config_cpu_card.incl.pl1 ... 11/27/80 W. Olin Sibert */
3 2 /* format: style4 */
3 3
3 4 dcl cpu_cardp pointer; /* pointer to CPU card */
3 5
3 6 dcl 1 cpu_card aligned based (cpu_cardp), /* CPU card declaration */
3 7 2 word char (4), /* "cpu" */
3 8 2 tag fixed bin (3), /* CPU tag from switches, plus one */
3 9 2 port fixed bin (3), /* Controller port for CPU */
3 10 2 state char (4), /* "on", "off", "shut", or "test" */
3 11 2 type char (4), /* "l68", "dps", "dps8" */
3 12
3 13 2 model fixed bin, /* 60., 80., or 70. */
3 14 2 cache_size fixed bin, /* either 0. 2. 8. 16. or 32. */
3 15 2 expander_port fixed bin (3), /* If present, indicates expander sub-port */
3 16
3 17 2 pad (7) bit (36) aligned, /* Pad to 15 fields */
3 18
3 19 2 type_word aligned,
3 20 3 field_type (14) bit (2) unaligned, /* type of each field; see config_deck.incl.pl1 */
3 21 3 pad1 bit (4) unaligned,
3 22 3 n_fields fixed bin (4) unsigned unaligned; /* number of fields used on card */
3 23
3 24 dcl CPU_CARD_WORD char (4) aligned internal static options (constant) init ("cpu");
3 25
3 26 /* END INCLUDE FILE ... config_cpu_card.incl.pl1 */
333
334 /* BEGIN INCLUDE FILE ... config_mem_card.incl.pl1 ... 11/27/80 W. Olin Sibert */
4 2
4 3 dcl mem_cardp pointer; /* pointer to MEM card */
4 4
4 5 dcl 1 mem_card aligned based (mem_cardp), /* MEM card declaration */
4 6 2 word char (4), /* "mem" */
4 7 2 tag fixed bin (3), /* One more than module port to which controller is attached */
4 8 2 size fixed bin (18), /* Number of pages in memory controller */
4 9 2 state char (4), /* State: "on" or "off" */
4 10
4 11 2 pad (11) bit (36) aligned, /* Pad to 15 fields */
4 12
4 13 2 type_word aligned,
4 14 3 field_type (14) bit (2) unaligned, /* type of each field; see config_deck.incl.pl1 */
4 15 3 pad1 bit (4) unaligned,
4 16 3 n_fields fixed bin (4) unsigned unaligned; /* number of fields used on card */
4 17
4 18 dcl MEM_CARD_WORD char (4) aligned internal static options (constant) init ("mem");
4 19
4 20 /* END INCLUDE FILE ... config_mem_card.incl.pl1 */
334
335 /* ***********************************************************
5 2* * *
5 3* * Copyright, (C) Honeywell Information Systems Inc., 1982 *
5 4* * *
5 5* *********************************************************** */
5 6 /* Begin include file ...... rsw.incl.pl1
5 7* Modified 3/26/77 by Noel I. Morris
5 8* Modified 9/03/80 by J. A. Bush for the DPS8/70M CPU
5 9* Modified 3/24/82 by J. A. Bush to allow the L68 CPU to address 4MW/port */
5 10
5 11 dcl rswp ptr;
5 12
5 13 dcl 1 dps_rsw_2 aligned based (rswp), /* rsw 2 template for DPS and L68 CPUs */
5 14 (2 pad1 bit (4),
5 15 2 cpu_type fixed bin (2) unsigned, /* 0 = L68 or DPS, 1 = DPS8 */
5 16 2 fault_base bit (7), /* high order bits of fault vector */
5 17 2 pad2 bit (6),
5 18 2 dps_option bit (1), /* "1"b => DPS CPU, "0"b => L68 CPU */
5 19 2 pad3 bit (7),
5 20 2 cache2 bit (1), /* "1"b => 2k cache installed, "0"b => no cache */
5 21 2 ext_gcos bit (1), /* "1"b => ext gcos option installed */
5 22 2 id bit (4), /* CPU ID - "1110"b => L68 */
5 23 2 cpu_num fixed bin (3) unsigned) unaligned; /* processor number */
5 24
5 25 dcl 1 dps8_rsw_2 aligned based (rswp), /* rsw 2 template for DPS8 CPUs */
5 26 (2 interlace_info (0:3) bit (1), /* if interlace enabled; "0"b => 4-word, "1"b => 2-word */
5 27 2 cpu_type fixed bin (2) unsigned, /* 0 = L68 or DPS, 1 = DPS8 */
5 28 2 fault_base bit (7), /* high order bits of fault vector */
5 29 2 id_prom bit (1), /* "1"b => id_prom present */
5 30 2 pad1 bit (5),
5 31 2 dps_option bit (1), /* always "1"b for DPS8 CPU */
5 32 2 cache8 bit (1), /* "1"b => 8k cache installed, "0"b => no cache */
5 33 2 pad2 bit (2),
5 34 2 multics_cpu bit (1), /* always "1"b for Multics cpu */
5 35 2 pad3 bit (5),
5 36 2 cpu_speed bit (4), /* cpu speed options */
5 37 2 cpu_num fixed bin (3) unsigned) unaligned; /* processor number */
5 38
5 39 dcl 1 rsw_1_3 aligned based (rswp), /* rsw 3 only valid on DPS and L68 CPUs */
5 40 (2 port_info (0:3), /* controller port information */
5 41 3 port_assignment bit (3), /* port address assignment */
5 42 3 port_enable bit (1), /* "1"b => port enabled */
5 43 3 initialize_enable bit (1), /* "1"b => system initialize enabled */
5 44 3 interlace_enable bit (1), /* "1"b => port is interlaced with neighbor */
5 45 3 mem_size fixed bin (3) unsigned) unaligned; /* encoded memory size on port */
5 46
5 47 dcl 1 rsw_4 aligned based (rswp), /* rsw 4 only valid on DPS and L68 CPUs */
5 48 (2 pad1 bit (13),
5 49 2 port_info (0:7), /* additional controller port information */
5 50 3 four bit (1), /* "0"b => 4-word interlace - "1"b => 2-word interlace */
5 51 3 half bit (1), /* "1"b => only half of memory on controller in use */
5 52 2 pad2 bit (7)) unaligned;
5 53
5 54 dcl dps_mem_size_table (0:7) fixed bin (24) static options (constant) init /* DPS and L68 memory sizes */
5 55 (32768, 65536, 4194304, 131072, 524288, 1048576, 2097152, 262144);
5 56
5 57 /* Note that the third array element above, is changed incompatibly in MR10.0.
5 58* In previous releases, this array element was used to decode a port size of
5 59* 98304 (96K). With MR10.0 it is now possible to address 4MW per CPU port, by
5 60* installing FCO # PHAF183 and using a group 10 patch plug, on L68 and DPS CPUs.
5 61**/
5 62
5 63 dcl dps8_mem_size_table (0:7) fixed bin (24) static options (constant) init /* DPS8 memory sizes */
5 64 (32768, 65536, 131072, 262144, 524288, 1048576, 2097152, 4194304);
5 65
5 66 dcl rsw_valid (0:1) fixed bin static options (constant) init (5, 3); /* # of rsw valid per cpu type */
5 67
5 68 /* End of include file ...... rsw.incl.pl1 */
335
336 /* BEGIN INCLUDE FILE scs.incl.pl1 ... March 1983 */
6 2 /* format: style4 */
6 3
6 4 /* Information about system controllers */
6 5
6 6 dcl 1 scs$controller_data (0:7) aligned ext, /* per-controller info */
6 7 2 size fixed bin (17) unaligned, /* size (in 1024 word blocks) of this controller */
6 8 2 base fixed bin (17) unaligned, /* abs address (0 mod 1024) for base of this controller */
6 9 2 eima_data (4) unaligned, /* EIMA information for this controller */
6 10 3 mask_available bit (1) unaligned, /* ON if corresponding mask exists */
6 11 3 mask_assigned bit (1) unaligned, /* ON if mask assigned to a port */
6 12 3 mbz bit (3) unaligned,
6 13 3 mask_assignment fixed bin (3) unaligned, /* port to which mask is assigned */
6 14 2 info aligned,
6 15 3 online bit (1) unaligned, /* ON if controller is online */
6 16 3 offline bit (1) unaligned, /* ON if controller is offline but can be added */
6 17 3 store_a_online bit (1) unaligned, /* ON if store A is online */
6 18 3 store_a1_online bit (1) unaligned, /* ON if store A1 is online */
6 19 3 store_b_online bit (1) unaligned, /* ON if store B is online */
6 20 3 store_b1_online bit (1) unaligned, /* ON if store B1 is online */
6 21 3 store_b_is_lower bit (1) unaligned, /* ON if store B is lower */
6 22 3 ext_interlaced bit (1) unaligned, /* ON if this SCU is interlaced with other SCU */
6 23 3 int_interlaced bit (1) unaligned, /* ON if this SCU is internally interlaced */
6 24 3 four_word bit (1) unaligned, /* ON if external interlace is 4-word */
6 25 3 cyclic_priority (7) bit (1) unaligned, /* Cyclic priority for adjacent ports */
6 26 3 type bit (4) unaligned, /* Model number for this controller */
6 27 3 abs_wired bit (1) unaligned, /* ON if controller can have abs_wired pages */
6 28 3 program bit (1) unaligned, /* PROGRAM/MANUAL switch setting */
6 29 3 mbz bit (13) unaligned,
6 30 2 lower_store_size fixed bin (17) unaligned, /* size (in 1024 word blocks) of lower store */
6 31 2 upper_store_size fixed bin (17) unaligned; /* size (in 1024 word blocks) of upper store */
6 32
6 33 /* Information about CPUs */
6 34
6 35 dcl 1 scs$processor_data (0:7) aligned ext, /* information about CPUs in the system */
6 36 (
6 37 2 online bit (1), /* "1"b if CPU is online */
6 38 2 offline bit (1), /* "1"b if CPU is offline but can be added */
6 39 2 release_mask bit (1), /* "1"b is this CPU is to give up its mask */
6 40 2 accept_mask bit (1), /* "1"b if this CPU is to grap mask in idle loop */
6 41 2 delete_cpu bit (1), /* "1"b if this CPU is to delete itself */
6 42 2 interrupt_cpu bit (1), /* "1"b if this CPU takes hardware interrupts */
6 43 2 halted_cpu bit (1), /* "1"b if this CPU has stopped itself (going to BOS) */
6 44 2 cpu_type fixed bin (2) unsigned, /* 0 => DPS or L68, 1 => DPS8 */
6 45 2 mbz1 bit (6),
6 46 2 cache_size fixed bin (3) unsigned, /* 0 = No cache; 1 = L68 2K cache;
6 47* 2 = DPS8 8K cache; 3 = DPS8 VS&SC 8K cache;
6 48* 4 = DPS8 VS&SC 16K cache; 5 = DPS8 VS&SC 32K cache
6 49* 7 = ignore cache size (set by ISOLTS reconfig) */
6 50 2 mbz2 bit (12),
6 51 2 expanded_port bit (1), /* "1"b = on expanded port */
6 52 2 expander_port fixed bin (2) unsigned, /* The actual expander port */
6 53 2 controller_port fixed bin (3) unsigned
6 54 ) unaligned; /* Port on controller */
6 55
6 56 dcl 1 scs$port_data (0:7) aligned external static, /* Info about what is connected to each SCU port */
6 57 2 assigned fixed bin (4) unsigned unaligned, /* Type of device on this port */
6 58 2 expander_port bit (1) unaligned, /* "1"b => this port has a port expander */
6 59 2 expanded_cpu (0:3) bit (1) unaligned, /* "1"b => this expander port has a CPU attached */
6 60 2 iom_number fixed bin (3) unsigned unaligned, /* IOM number of IOM attached to this port */
6 61 2 cpu_number (0:3) fixed bin (3) unsigned unaligned, /* CPU number of CPU(s) attached to this port */
6 62 /* cpu_number (0) is only one if expander_port is "0"b */
6 63 2 pad bit (12) unaligned;
6 64
6 65 dcl 1 scs$cow (0:7) aligned external, /* Actual connect words */
6 66 2 pad bit (36) aligned, /* Expander COW's must be odd-word */
6 67 2 cow,
6 68 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */
6 69 3 mbz1 bit (13) unaligned,
6 70 3 expander_command bit (3) unaligned, /* Expander command. */
6 71 3 mbz2 bit (2) unaligned,
6 72 3 expanded_port bit (1) unaligned, /* "1"b = on expanded port */
6 73 3 expander_port fixed bin (3) unsigned unaligned, /* Port on expander for cioc */
6 74 3 mbz3 bit (3) unaligned,
6 75 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */
6 76
6 77 dcl 1 scs$cow_ptrs (0:7) external aligned, /* Pointers to COW's */
6 78 2 rel_cow_ptr bit (18) unal, /* Relative pointer to COW */
6 79 2 pad bit (12) unal,
6 80 2 tag bit (6) unal; /* Better be zero. */
6 81
6 82 dcl 1 scs$reconfig_general_cow aligned external, /* Used during reconfig ops. */
6 83 2 pad bit (36) aligned,
6 84 2 cow, /* Connect operand word, in odd location. */
6 85 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */
6 86 3 mbz1 bit (13) unaligned,
6 87 3 expander_command bit (3) unaligned, /* Expander command. */
6 88 3 mbz2 bit (9) unaligned,
6 89 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */
6 90
6 91 /* MASKS and PATTERNS */
6 92
6 93 dcl scs$sys_level bit (72) aligned ext; /* mask used while handling I/O interrupts */
6 94 dcl scs$open_level bit (72) aligned ext; /* mask used during normal operation */
6 95 dcl scs$processor_start_mask bit (72) aligned ext; /* mask used when starting up a CPU */
6 96 dcl scs$cpu_test_mask bit (72) aligned ext; /* mask used for ISOLTS CPU testing */
6 97 dcl scs$number_of_masks fixed bin ext; /* number of masks (starting at sys_level) */
6 98 dcl scs$processor_start_pattern bit (36) aligned ext; /* SMIC pattern used to send processor start interrupt */
6 99 dcl scs$cpu_test_pattern bit (36) aligned ext; /* SMIC pattern used for ISOLTS processor testing */
6 100
6 101 /* CAM and CACHE clear info */
6 102
6 103 dcl scs$cam_pair fixed bin (71) ext; /* instructions XEDd when CAMing and clearing CACHE */
6 104 dcl scs$cam_wait bit (8) aligned ext; /* Used when evicting pages from main memory */
6 105
6 106 /* MASKING INSTRUCTIONS & POINTERS */
6 107
6 108 dcl scs$set_mask (0:7) bit (36) aligned ext; /* instructions to set mask (STAQ or SMCM) */
6 109 dcl scs$read_mask (0:7) bit (36) aligned ext; /* instructions to read mask (LDAQ or RMCM) */
6 110 dcl scs$mask_ptr (0:7) ptr unaligned ext; /* pointers for real or simulated masks */
6 111
6 112 /* MISCELLANEOUS */
6 113
6 114 dcl 1 scs$processor_test_data aligned ext, /* info used for cpu testing */
6 115 (
6 116 2 active bit (1), /* = "1"b if cpu currently under test */
6 117 2 scu_state bit (2), /* state of scu being used for testing (see definition below) */
6 118 2 pad1 bit (4),
6 119 2 req_mem fixed bin (10), /* dedicated memory required to test this cpu */
6 120 2 cpu_tag fixed bin (5), /* tag of cpu under test */
6 121 2 scu_tag fixed bin (5), /* tag of scu being used for cpu testing */
6 122 2 mask_cpu fixed bin (5)
6 123 ) unaligned; /* tag of active cpu that has mask asigned to above scu */
6 124
6 125 /* scu_state = "00"b => SCU defined by scs$processor_test_data.scu_tag not yet effected */
6 126 /* scu_state = "01"b => all core removed from SCU, port mask not yet changed */
6 127 /* scu_state = "10"b => all core removed from SCU, port mask changed */
6 128 /* scu_state = "11"b => only 64k at base of SCU being used for testing, original port mask restored */
6 129
6 130 dcl scs$idle_aptep (0:7) ptr unaligned ext; /* pointer to idle process APTE for each processor */
6 131
6 132 dcl scs$connect_lock bit (36) aligned ext; /* lock for sending connects */
6 133 dcl scs$reconfig_lock bit (36) aligned ext; /* Lock used during reconfiguration */
6 134 dcl scs$trouble_flags bit (8) aligned ext; /* checkoff flags for sys_trouble stopping */
6 135 dcl scs$bos_restart_flags bit (8) aligned ext; /* checkoff flags for restarting after sys_trouble */
6 136 dcl scs$nprocessors fixed bin ext; /* number of runnung processors */
6 137 dcl scs$bos_processor_tag fixed bin (3) ext; /* CPU tag of processor running BOS */
6 138 dcl scs$faults_initialized bit (1) aligned ext; /* ON after faults have been enabled */
6 139 dcl scs$sys_trouble_pending bit (1) aligned ext; /* sys_trouble event is pending in the system */
6 140 dcl scs$fast_cam_pending (0:7) bit (36) aligned ext; /* checkoff cells for cam connect */
6 141 dcl scs$interrupt_controller fixed bin (3) ext; /* port number of low order controller */
6 142 dcl scs$processor_start_int_no fixed bin (5) ext; /* interrupt cell for starting a processor */
6 143 dcl scs$processor bit (8) aligned ext; /* bits ON for online CPUs */
6 144 dcl scs$processor_start_wait bit (8) aligned ext; /* checkoff flags for waiting for new processor */
6 145
6 146 dcl scs$trouble_dbrs (0:7) fixed bin (71); /* DBR values at system crash time */
6 147
6 148 dcl scs$port_addressing_word (0:7) bit (3) aligned ext; /* active module port number for each controller */
6 149
6 150 dcl scs$cfg_data (0:7) fixed bin (71) aligned ext; /* RSCR-CFG data from each controller */
6 151
6 152 dcl scs$cfg_data_save fixed bin (71) aligned ext; /* RSCR-CFG save area for ISOLTS CPU testing */
6 153
6 154 dcl scs$expanded_ports bit (1) unaligned dim (0:7) external;
6 155 /* Which ports have expanders */
6 156
6 157 dcl scs$processor_switch_data (0:4) bit (36) aligned ext; /* raw data from RSW 0 thru 4 */
6 158 dcl scs$processor_switch_template (0:4) bit (36) aligned ext; /* expected data from RSW 0 thru 4 */
6 159 dcl scs$processor_switch_compare (0:4) bit (36) aligned ext; /* discrepancies from expected data */
6 160 dcl scs$processor_switch_mask (0:4) bit (36) aligned ext; /* masks for comparing switch data */
6 161
6 162 dcl scs$processor_data_switch_value bit (36) aligned ext; /* Correct value for CPU data switches */
6 163
6 164 dcl scs$controller_config_size (0:7) fixed bin (14) aligned ext;
6 165 /* Controller size on config card */
6 166
6 167 dcl scs$reconfig_locker_id char (32) aligned ext; /* process group ID of process doing reconfiguration */
6 168
6 169 dcl scs$scas_page_table (0:31) bit (36) aligned external static;
6 170 /* PTWs for SCAS pages */
6 171
6 172 dcl scs$cycle_priority_template bit (7) aligned ext; /* template for setting anti-hog switches */
6 173 dcl scs$set_cycle_switches bit (1) aligned ext; /* flag to set ant-hog switches */
6 174
6 175
6 176 dcl (
6 177 IOM_PORT init (1),
6 178 CPU_PORT init (2),
6 179 BULK_PORT init (3)
6 180 ) fixed bin int static options (constant); /* values for scs$port_data.assigned */
6 181
6 182
6 183 /* END INCLUDE FILE scs.incl.pl1 */
336
337 /* BEGIN INCLUDE FILE ... sdw_info.incl.pl1 ... 12/16/80, for ADP conversion */
7 2 /* Note: This include file has an ALM counterpart made with cif. Keep it up to date */
7 3
7 4 dcl sdw_info_ptr pointer;
7 5
7 6 dcl 1 sdw_info aligned based (sdw_info_ptr), /* Structure describing SDW contents */
7 7 2 address fixed bin (26), /* Address of seg base or of page table */
7 8 2 size fixed bin (19), /* Max length of segment (NOT offset of last word) */
7 9
7 10 2 access unaligned, /* REWP */
7 11 3 read bit (1) unaligned,
7 12 3 execute bit (1) unaligned,
7 13 3 write bit (1) unaligned,
7 14 3 privileged bit (1) unaligned,
7 15
7 16 2 pad1 bit (32) unaligned,
7 17
7 18 2 rings unaligned, /* Ring brackets */
7 19 3 r1 bit (3) unaligned,
7 20 3 r2 bit (3) unaligned,
7 21 3 r3 bit (3) unaligned,
7 22
7 23 2 pad2 bit (27) unaligned,
7 24
7 25 2 flags aligned,
7 26 3 paged bit (1) unaligned, /* "1"b => Segment is paged */
7 27 3 faulted bit (1) unaligned, /* "1"b => SDW has fault set */
7 28 3 cache bit (1) unaligned, /* "1"b => Segment is encacheable */
7 29 3 pad3 bit (33) unaligned,
7 30
7 31 2 gate_entry_bound fixed bin (14); /* Number of entrypoints in gate, or zero */
7 32
7 33 /* END INCLUDE FILE ... sdw_info.incl.pl1 */
337
338 /* BEGIN INCLUDE FILE syserr_constants.incl.pl1 ... 11/11/80 W. Olin Sibert */
8 2 /* 85-02-12, EJ Sharpe - Added sorting class constants, removed AIM_MESSAGE, added new action code names. */
8 3 /* 85-04-24, G. Palter - Renamed SYSERR_UNUSED_10 to SYSERR_RING1_ERROR to reflect its actual use. */
8 4
8 5 /* This include file has an ALM version. Keep 'em in sync! */
8 6
8 7 dcl (
8 8
8 9 /* The following constants define the message action codes. This indicates
8 10*how a message is to be handled. */
8 11
8 12 SYSERR_CRASH_SYSTEM init (1),
8 13 CRASH init (1), /* Crash the system, and bleat plaintively. */
8 14
8 15 SYSERR_TERMINATE_PROCESS init (2),
8 16 TERMINATE_PROCESS init (2), /* Terminate the process, print the message, and beep. */
8 17
8 18 SYSERR_PRINT_WITH_ALARM init (3),
8 19 BEEP init (3), /* Beep and print the message on the console. */
8 20
8 21 SYSERR_PRINT_ON_CONSOLE init (0),
8 22 ANNOUNCE init (0), /* Just print the message on the console. */
8 23
8 24 SYSERR_LOG_OR_PRINT init (4),
8 25 LOG init (4), /* Log the message, or print it if it can't be logged */
8 26
8 27 SYSERR_LOG_OR_DISCARD init (5),
8 28 JUST_LOG init (5), /* Just try to log the message, and discard it if it can't be */
8 29
8 30
8 31 /* The following constants are added to the normal severities to indicate
8 32*different sorting classes of messages. */
8 33
8 34 SYSERR_SYSTEM_ERROR init (00), /* indicates a standard level system error */
8 35 SYSERR_RING1_ERROR init (10), /* indicates an error detected in ring 1 (mseg_, RCP) */
8 36 SYSERR_COVERT_CHANNEL init (20), /* indicates covert channel audit trail message */
8 37 SYSERR_UNSUCCESSFUL_ACCESS init (30), /* indicates access denial audit trail message */
8 38 SYSERR_SUCCESSFUL_ACCESS init (40) /* indicates access grant audit trail message */
8 39 ) fixed bin internal static options (constant);
8 40
8 41 /* END INCLUDE FILE syserr_constants.incl.pl1 */
338
339 /* START OF: time_names_.incl.pl1 * * * * * * * * * * * * * * * * */
9 2
9 3 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
9 4 /* */
9 5 /* Name: time_names_.incl.pl1 */
9 6 /* */
9 7 /* This include file defines the structure of values in the time_table_. The table */
9 8 /* includes a list of time zones known to the system, as well as lists of month names */
9 9 /* and names of days of the week. All names are expressed in several different languages */
9 10 /* to facilitate transliteration of dates into these languages. The table includes */
9 11 /* the list of languages in which dates may be expressed. */
9 12 /* */
9 13 /* Status */
9 14 /* */
9 15 /* 0) Created 06/07/78: J. Falksen */
9 16 /* 1) Modified 07/04/78: G. Dixon */
9 17 /* */
9 18 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
9 19
9 20
9 21 dcl time_info_$version char (8) ext static; /* Version number of all structures in the */
9 22 /* time_info_. Currently = 1. */
9 23 dcl Vtime_info_2 char (8) int static options(constant) init("tinfo002");
9 24
9 25 dcl time_info_$gmt_zone_index fixed bin (17) ext static;
9 26 dcl time_info_$default_language_index fixed bin (17) ext static;
9 27
9 28 dcl time_info_$date_time_keywords fixed bin ext static; /* Table of named date/time format strings */
9 29 dcl 1 ti_keyword based (addr (time_info_$date_time_keywords)),
9 30 2 number_kwd fixed bin, /* number of keywords present */
9 31 2 pad fixed bin,
9 32 2 e (0 refer (ti_keyword.number_kwd)),
9 33 3 name char (32),
9 34 3 str char (128)var;
9 35 dcl (site_date init (1),
9 36 site_date_time init (2),
9 37 site_time init (3)
9 38 ) fixed bin int static options (constant);
9 39
9 40 dcl time_info_$language_names fixed bin ext static; /* Table of language names, in various languages */
9 41
9 42 dcl 1 ti_language based (addr (time_info_$language_names)),
9 43 2 number_lang fixed bin, /* number of language names present */
9 44 2 pad fixed bin,
9 45 2 name (0 refer (ti_language.number_lang), 0 refer (ti_language.number_lang))
9 46 char(32) varying; /* Name of the language. */
9 47 /* All language names are expressed in all languages. name(i,j) gives the */
9 48 /* jth language name in language i. name(i,i) gives a language name in its */
9 49 /* own language. */
9 50 dcl time_info_$month_names fixed bin ext static; /* Table of month names in various languages. */
9 51
9 52 dcl 1 ti_month based (addr (time_info_$month_names)),
9 53 2 number_lang fixed bin, /* number of languages in the table. */
9 54 2 pad fixed bin,
9 55 2 e (0 refer (ti_month.number_lang), 12),
9 56 3 short char(8) var, /* short form of a month name, i.e., Nov */
9 57 3 long char(32) var; /* long form of a month name, i.e. November */
9 58 dcl time_info_$day_names fixed bin ext static; /* Table of day names in various languages. */
9 59
9 60 dcl 1 ti_day based (addr (time_info_$day_names)),
9 61 2 number_lang fixed bin, /* number of languages in the table. */
9 62 2 pad fixed bin,
9 63 2 e (0 refer (ti_day.number_lang), 7),
9 64 3 short char(8) var, /* short for of a day name, i.e. Sat */
9 65 3 long char(32) var; /* long form of a day name, i.e. Saturday */
9 66 dcl time_info_$offset_names fixed bin ext static; /* Table of offset names in various languages. */
9 67
9 68 dcl 1 ti_offset based (addr (time_info_$offset_names)),
9 69 2 number_lang fixed bin, /* number of languages in the table. */
9 70 2 number_offset fixed bin,
9 71 2 e (0 refer (ti_offset.number_lang), 0 refer (ti_offset.number_offset)),
9 72 3 short char(32) var, /* short form of an offset name, i.e. min */
9 73 3 plural char(32) var, /* plural form of an offset name, i.e. minutes */
9 74 3 singular char(32) var, /* singular for of an offset name, i.e. minute */
9 75 3 this char(32) var; /* "this" which goes with singular */
9 76 dcl time_info_$word_names fixed bin ext static; /* Table of word names in various languages. */
9 77
9 78 dcl 1 ti_word based (addr (time_info_$word_names)),
9 79 2 number_lang fixed bin, /* number of languages in the table. */
9 80 2 number_word fixed bin,
9 81 2 short (0 refer (ti_word.number_lang), 0 refer (ti_word.number_word))
9 82 char (8) var,
9 83 2 word (0 refer (ti_word.number_lang), 0 refer (ti_word.number_word))
9 84 char(32) var; /* a "word", i.e. Midnight */
9 85
9 86 dcl time_info_$zone_names fixed bin ext static; /* Table of known time zones. */
9 87
9 88 dcl 1 ti_zone based (addr (time_info_$zone_names)),
9 89 2 number_lang fixed bin, /* number of languages in which zone names */
9 90 /* are defined. */
9 91 2 number_zone fixed bin, /* number of zone names in the table. */
9 92 2 e (0 refer (ti_zone.number_lang), 0 refer (ti_zone.number_zone)),
9 93 3 short char(4) var, /* short form of the zone name. */
9 94 3 long char(64) var, /* long form of the zone name */
9 95 3 pad fixed bin,
9 96 3 delta fixed bin(71); /* offset, in microseconds, of this time zone */
9 97 /* from GMT (Greenwich mean time). This value */
9 98 /* should be subtracted from a clock value */
9 99 /* (which is expressed in GMT by definition). */
9 100 /* to obtain a date/time expressed in the */
9 101 /* named time zone. */
9 102 /* NOTE: zones are listed in order of descending */
9 103 /* delta, from +11 to -12. print_time_zones */
9 104 /* requires this. */
9 105
9 106
9 107 dcl (tiw_FiscalIndicator init (11)
9 108 ) fixed bin int static options (constant);
9 109
9 110 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
9 111 /* NOTE TO MAINTAINER: Before changing this file, see the comments in */
9 112 /* time_info_cds.incl.pl1 */
9 113 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
9 114
9 115 /* END OF: time_names_.incl.pl1 * * * * * * * * * * * * * * * * */
339
340 /* format: on */
341
342 /* BEGIN MESSAGE DOCUMENTATION
343*
344*Message:
345*scs_and_clock_init: No SCU port is assigned address zero.
346*
347*S: $crash
348*
349*T: $init
350*
351*M: None of the system controllers in the config deck appear
352*to have a base address of zero.
353*
354*A: Check the config deck and bootload processor port assignment
355*and address switches.
356*
357*
358*Message:
359*scs_and_clock_init: SCU clock on port NUMBER MALFUNCTION.
360*
361*S: $crash
362*
363*T: $init
364*
365*M: The calendar clock in the bootload SCU seems to be
366*malfunctioning, as specified by MALFUNCTION.
367*
368*A: Fix the SCU, or configure another SCU as low order.
369*
370*Message:
371*scs_and_clock_init: No CLOK card.
372*
373*S: $crash
374*
375*T: $init
376*
377*M: No CLOK card was found in the config deck. One is required.
378*
379*A: Add a CLOK card to the config deck.
380*
381*Message:
382*scs_and_clock_init: The zone on the CLOK card is not in time_info_.
383*
384*S: $crash
385*
386*T: $init
387*
388*M: The zone named on the CLOK card is not found in time_info_, the
389*system's time information database. The system cannot run
390*unless a known zone is specified.
391*
392*A: Update the CLOK card so that it contains a proper zone name. If
393*the zone you need is not known to the system, time_info_.cds
394*will have to be updated, a new system tape generated, and then
395*booting from that tape. time_info_ contains at least 1 name for
396*each hour around the world. You may select a named zone near
397*the one you need, just to get the system up to be able to change
398*time_info_.
399*
400*END MESSAGE DOCUMENTATION */
401
402 end scs_and_clock_init;
SOURCE FILES USED IN THIS COMPILATION.
LINE NUMBER DATE MODIFIED NAME PATHNAME
0 11/11/89 0816.1 scs_and_clock_init.pl1 >spec>install>1112>scs_and_clock_init.pl1
331 1 07/11/84 0937.3 collection_1_phases.incl.pl1 >ldd>include>collection_1_phases.incl.pl1
332 2 05/08/81 1853.6 config_clok_card.incl.pl1 >ldd>include>config_clok_card.incl.pl1
333 3 10/14/83 0957.2 config_cpu_card.incl.pl1 >ldd>include>config_cpu_card.incl.pl1
334 4 05/08/81 1853.6 config_mem_card.incl.pl1 >ldd>include>config_mem_card.incl.pl1
335 5 06/10/82 1045.2 rsw.incl.pl1 >ldd>include>rsw.incl.pl1
336 6 10/12/83 0943.5 scs.incl.pl1 >ldd>include>scs.incl.pl1
337 7 03/27/82 0430.3 sdw_info.incl.pl1 >ldd>include>sdw_info.incl.pl1
338 8 05/17/85 0615.7 syserr_constants.incl.pl1 >ldd>include>syserr_constants.incl.pl1
339 9 09/06/84 0850.2 time_names.incl.pl1 >ldd>include>time_names.incl.pl1
NAMES DECLARED IN THIS COMPILATION.
IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES
(* indicates a set context)
NAMES DECLARED BY DECLARE STATEMENT.
CLOK_CARD_WORD 000002 constant char(4) initial dcl 2-18 set ref 306*
CPU_CARD_WORD 000001 constant char(4) initial dcl 3-24 set ref 179*
CRASH 000015 constant fixed bin(17,0) initial dcl 8-7 set ref 224* 285* 307* 322*
MEM_CARD_WORD 000000 constant char(4) initial dcl 4-18 set ref 250*
SERVICE_INITIALIZATION constant fixed bin(17,0) initial dcl 1-12 ref 265 307
WHOAMI 000010 internal static char(32) initial packed unaligned dcl 114 set ref 224* 285*
307* 322*
absadr 000020 constant entry external dcl 79 ref 240
access 2 000131 automatic structure level 2 packed packed unaligned dcl 67
addr builtin function dcl 118 ref 138 138 143 162 185 185 187 199 240 240
242 242 244 244 244 244 246 247 247 247 247 261
261 261 261 316 317 318 323
address 000131 automatic fixed bin(26,0) level 2 dcl 67 set ref 240*
base 000100 automatic fixed bin(17,0) dcl 54 set ref 213* 215
based_scs based bit(36) array dcl 74 set ref 143*
baseno builtin function dcl 118 ref 246
binary builtin function dcl 118 ref 149 246
bit builtin function dcl 118 ref 149 218
clock builtin function dcl 118 ref 267 271
clok_card based structure level 1 dcl 2-5
clok_cardp 000146 automatic pointer dcl 2-3 set ref 305* 306* 307 315 318