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rsw_util.list
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COMPILATION LISTING OF SEGMENT rsw_util
Compiled by: Multics PL/I Compiler, Release 32f, of October 9, 1989
Compiled at: Bull HN, Phoenix AZ, System-M
Compiled on: 11/11/89 1027.1 mst Sat
Options: optimize map
1 /****^ ***********************************************************
2* * *
3* * Copyright, (C) Honeywell Bull Inc., 1987 *
4* * *
5* * Copyright, (C) Honeywell Information Systems Inc., 1982 *
6* * *
7* *********************************************************** */
8 /* RSW_UTIL - Procedures to Read and Interpret the Processor Switches.
9* coded 4/12/76 by Noel I. Morris
10* Modfified 9/04/80 by J. A. Bush for the DPS8/70M CPU
11**/
12
13
14 /* ******************************************************
15* * *
16* * *
17* * Copyright (c) 1972 by Massachusetts Institute of *
18* * Technology and Honeywell Information Systems, Inc. *
19* * *
20* * *
21* ****************************************************** */
22
23
24
25
26 rsw_util: proc;
27
28 dcl tag fixed bin (3), /* system controller tag */
29 enabled bit (1) aligned, /* "1"b if processor port enabled */
30 base fixed bin (17), /* base address of memory in controller */
31 size fixed bin (17), /* size of memory in controller */
32 interlace fixed bin (3); /* memory interlace type */
33
34 dcl rsw_1_3_data bit (36) aligned,
35 rsw_2_data bit (36) aligned,
36 rsw_4_data bit (36) aligned,
37 (rsw2p, rsw4p) ptr,
38 rsw fixed bin (3);
39
40 dcl privileged_mode_ut$rsw entry (fixed bin (3), bit (36) aligned);
41
42 dcl (addr, bin, divide) builtin;
43
44 dcl pip ptr; /* pointer to port info */
45
46 dcl 1 pi like rsw_1_3.port_info based (pip) unal; /* port info */
47
1 1 /* ***********************************************************
1 2* * *
1 3* * Copyright, (C) Honeywell Information Systems Inc., 1982 *
1 4* * *
1 5* *********************************************************** */
1 6 /* Begin include file ...... rsw.incl.pl1
1 7* Modified 3/26/77 by Noel I. Morris
1 8* Modified 9/03/80 by J. A. Bush for the DPS8/70M CPU
1 9* Modified 3/24/82 by J. A. Bush to allow the L68 CPU to address 4MW/port */
1 10
1 11 dcl rswp ptr;
1 12
1 13 dcl 1 dps_rsw_2 aligned based (rswp), /* rsw 2 template for DPS and L68 CPUs */
1 14 (2 pad1 bit (4),
1 15 2 cpu_type fixed bin (2) unsigned, /* 0 = L68 or DPS, 1 = DPS8 */
1 16 2 fault_base bit (7), /* high order bits of fault vector */
1 17 2 pad2 bit (6),
1 18 2 dps_option bit (1), /* "1"b => DPS CPU, "0"b => L68 CPU */
1 19 2 pad3 bit (7),
1 20 2 cache2 bit (1), /* "1"b => 2k cache installed, "0"b => no cache */
1 21 2 ext_gcos bit (1), /* "1"b => ext gcos option installed */
1 22 2 id bit (4), /* CPU ID - "1110"b => L68 */
1 23 2 cpu_num fixed bin (3) unsigned) unaligned; /* processor number */
1 24
1 25 dcl 1 dps8_rsw_2 aligned based (rswp), /* rsw 2 template for DPS8 CPUs */
1 26 (2 interlace_info (0:3) bit (1), /* if interlace enabled; "0"b => 4-word, "1"b => 2-word */
1 27 2 cpu_type fixed bin (2) unsigned, /* 0 = L68 or DPS, 1 = DPS8 */
1 28 2 fault_base bit (7), /* high order bits of fault vector */
1 29 2 id_prom bit (1), /* "1"b => id_prom present */
1 30 2 pad1 bit (5),
1 31 2 dps_option bit (1), /* always "1"b for DPS8 CPU */
1 32 2 cache8 bit (1), /* "1"b => 8k cache installed, "0"b => no cache */
1 33 2 pad2 bit (2),
1 34 2 multics_cpu bit (1), /* always "1"b for Multics cpu */
1 35 2 pad3 bit (5),
1 36 2 cpu_speed bit (4), /* cpu speed options */
1 37 2 cpu_num fixed bin (3) unsigned) unaligned; /* processor number */
1 38
1 39 dcl 1 rsw_1_3 aligned based (rswp), /* rsw 3 only valid on DPS and L68 CPUs */
1 40 (2 port_info (0:3), /* controller port information */
1 41 3 port_assignment bit (3), /* port address assignment */
1 42 3 port_enable bit (1), /* "1"b => port enabled */
1 43 3 initialize_enable bit (1), /* "1"b => system initialize enabled */
1 44 3 interlace_enable bit (1), /* "1"b => port is interlaced with neighbor */
1 45 3 mem_size fixed bin (3) unsigned) unaligned; /* encoded memory size on port */
1 46
1 47 dcl 1 rsw_4 aligned based (rswp), /* rsw 4 only valid on DPS and L68 CPUs */
1 48 (2 pad1 bit (13),
1 49 2 port_info (0:7), /* additional controller port information */
1 50 3 four bit (1), /* "0"b => 4-word interlace - "1"b => 2-word interlace */
1 51 3 half bit (1), /* "1"b => only half of memory on controller in use */
1 52 2 pad2 bit (7)) unaligned;
1 53
1 54 dcl dps_mem_size_table (0:7) fixed bin (24) static options (constant) init /* DPS and L68 memory sizes */
1 55 (32768, 65536, 4194304, 131072, 524288, 1048576, 2097152, 262144);
1 56
1 57 /* Note that the third array element above, is changed incompatibly in MR10.0.
1 58* In previous releases, this array element was used to decode a port size of
1 59* 98304 (96K). With MR10.0 it is now possible to address 4MW per CPU port, by
1 60* installing FCO # PHAF183 and using a group 10 patch plug, on L68 and DPS CPUs.
1 61**/
1 62
1 63 dcl dps8_mem_size_table (0:7) fixed bin (24) static options (constant) init /* DPS8 memory sizes */
1 64 (32768, 65536, 131072, 262144, 524288, 1048576, 2097152, 4194304);
1 65
1 66 dcl rsw_valid (0:1) fixed bin static options (constant) init (5, 3); /* # of rsw valid per cpu type */
1 67
1 68 /* End of include file ...... rsw.incl.pl1 */
48
49
2 1 /* BEGIN INCLUDE FILE scs.incl.pl1 ... March 1983 */
2 2 /* format: style4 */
2 3
2 4 /* Information about system controllers */
2 5
2 6 dcl 1 scs$controller_data (0:7) aligned ext, /* per-controller info */
2 7 2 size fixed bin (17) unaligned, /* size (in 1024 word blocks) of this controller */
2 8 2 base fixed bin (17) unaligned, /* abs address (0 mod 1024) for base of this controller */
2 9 2 eima_data (4) unaligned, /* EIMA information for this controller */
2 10 3 mask_available bit (1) unaligned, /* ON if corresponding mask exists */
2 11 3 mask_assigned bit (1) unaligned, /* ON if mask assigned to a port */
2 12 3 mbz bit (3) unaligned,
2 13 3 mask_assignment fixed bin (3) unaligned, /* port to which mask is assigned */
2 14 2 info aligned,
2 15 3 online bit (1) unaligned, /* ON if controller is online */
2 16 3 offline bit (1) unaligned, /* ON if controller is offline but can be added */
2 17 3 store_a_online bit (1) unaligned, /* ON if store A is online */
2 18 3 store_a1_online bit (1) unaligned, /* ON if store A1 is online */
2 19 3 store_b_online bit (1) unaligned, /* ON if store B is online */
2 20 3 store_b1_online bit (1) unaligned, /* ON if store B1 is online */
2 21 3 store_b_is_lower bit (1) unaligned, /* ON if store B is lower */
2 22 3 ext_interlaced bit (1) unaligned, /* ON if this SCU is interlaced with other SCU */
2 23 3 int_interlaced bit (1) unaligned, /* ON if this SCU is internally interlaced */
2 24 3 four_word bit (1) unaligned, /* ON if external interlace is 4-word */
2 25 3 cyclic_priority (7) bit (1) unaligned, /* Cyclic priority for adjacent ports */
2 26 3 type bit (4) unaligned, /* Model number for this controller */
2 27 3 abs_wired bit (1) unaligned, /* ON if controller can have abs_wired pages */
2 28 3 program bit (1) unaligned, /* PROGRAM/MANUAL switch setting */
2 29 3 mbz bit (13) unaligned,
2 30 2 lower_store_size fixed bin (17) unaligned, /* size (in 1024 word blocks) of lower store */
2 31 2 upper_store_size fixed bin (17) unaligned; /* size (in 1024 word blocks) of upper store */
2 32
2 33 /* Information about CPUs */
2 34
2 35 dcl 1 scs$processor_data (0:7) aligned ext, /* information about CPUs in the system */
2 36 (
2 37 2 online bit (1), /* "1"b if CPU is online */
2 38 2 offline bit (1), /* "1"b if CPU is offline but can be added */
2 39 2 release_mask bit (1), /* "1"b is this CPU is to give up its mask */
2 40 2 accept_mask bit (1), /* "1"b if this CPU is to grap mask in idle loop */
2 41 2 delete_cpu bit (1), /* "1"b if this CPU is to delete itself */
2 42 2 interrupt_cpu bit (1), /* "1"b if this CPU takes hardware interrupts */
2 43 2 halted_cpu bit (1), /* "1"b if this CPU has stopped itself (going to BOS) */
2 44 2 cpu_type fixed bin (2) unsigned, /* 0 => DPS or L68, 1 => DPS8 */
2 45 2 mbz1 bit (6),
2 46 2 cache_size fixed bin (3) unsigned, /* 0 = No cache; 1 = L68 2K cache;
2 47* 2 = DPS8 8K cache; 3 = DPS8 VS&SC 8K cache;
2 48* 4 = DPS8 VS&SC 16K cache; 5 = DPS8 VS&SC 32K cache
2 49* 7 = ignore cache size (set by ISOLTS reconfig) */
2 50 2 mbz2 bit (12),
2 51 2 expanded_port bit (1), /* "1"b = on expanded port */
2 52 2 expander_port fixed bin (2) unsigned, /* The actual expander port */
2 53 2 controller_port fixed bin (3) unsigned
2 54 ) unaligned; /* Port on controller */
2 55
2 56 dcl 1 scs$port_data (0:7) aligned external static, /* Info about what is connected to each SCU port */
2 57 2 assigned fixed bin (4) unsigned unaligned, /* Type of device on this port */
2 58 2 expander_port bit (1) unaligned, /* "1"b => this port has a port expander */
2 59 2 expanded_cpu (0:3) bit (1) unaligned, /* "1"b => this expander port has a CPU attached */
2 60 2 iom_number fixed bin (3) unsigned unaligned, /* IOM number of IOM attached to this port */
2 61 2 cpu_number (0:3) fixed bin (3) unsigned unaligned, /* CPU number of CPU(s) attached to this port */
2 62 /* cpu_number (0) is only one if expander_port is "0"b */
2 63 2 pad bit (12) unaligned;
2 64
2 65 dcl 1 scs$cow (0:7) aligned external, /* Actual connect words */
2 66 2 pad bit (36) aligned, /* Expander COW's must be odd-word */
2 67 2 cow,
2 68 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */
2 69 3 mbz1 bit (13) unaligned,
2 70 3 expander_command bit (3) unaligned, /* Expander command. */
2 71 3 mbz2 bit (2) unaligned,
2 72 3 expanded_port bit (1) unaligned, /* "1"b = on expanded port */
2 73 3 expander_port fixed bin (3) unsigned unaligned, /* Port on expander for cioc */
2 74 3 mbz3 bit (3) unaligned,
2 75 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */
2 76
2 77 dcl 1 scs$cow_ptrs (0:7) external aligned, /* Pointers to COW's */
2 78 2 rel_cow_ptr bit (18) unal, /* Relative pointer to COW */
2 79 2 pad bit (12) unal,
2 80 2 tag bit (6) unal; /* Better be zero. */
2 81
2 82 dcl 1 scs$reconfig_general_cow aligned external, /* Used during reconfig ops. */
2 83 2 pad bit (36) aligned,
2 84 2 cow, /* Connect operand word, in odd location. */
2 85 3 sub_mask bit (8) unaligned, /* Expander sub-port mask */
2 86 3 mbz1 bit (13) unaligned,
2 87 3 expander_command bit (3) unaligned, /* Expander command. */
2 88 3 mbz2 bit (9) unaligned,
2 89 3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */
2 90
2 91 /* MASKS and PATTERNS */
2 92
2 93 dcl scs$sys_level bit (72) aligned ext; /* mask used while handling I/O interrupts */
2 94 dcl scs$open_level bit (72) aligned ext; /* mask used during normal operation */
2 95 dcl scs$processor_start_mask bit (72) aligned ext; /* mask used when starting up a CPU */
2 96 dcl scs$cpu_test_mask bit (72) aligned ext; /* mask used for ISOLTS CPU testing */
2 97 dcl scs$number_of_masks fixed bin ext; /* number of masks (starting at sys_level) */
2 98 dcl scs$processor_start_pattern bit (36) aligned ext; /* SMIC pattern used to send processor start interrupt */
2 99 dcl scs$cpu_test_pattern bit (36) aligned ext; /* SMIC pattern used for ISOLTS processor testing */
2 100
2 101 /* CAM and CACHE clear info */
2 102
2 103 dcl scs$cam_pair fixed bin (71) ext; /* instructions XEDd when CAMing and clearing CACHE */
2 104 dcl scs$cam_wait bit (8) aligned ext; /* Used when evicting pages from main memory */
2 105
2 106 /* MASKING INSTRUCTIONS & POINTERS */
2 107
2 108 dcl scs$set_mask (0:7) bit (36) aligned ext; /* instructions to set mask (STAQ or SMCM) */
2 109 dcl scs$read_mask (0:7) bit (36) aligned ext; /* instructions to read mask (LDAQ or RMCM) */
2 110 dcl scs$mask_ptr (0:7) ptr unaligned ext; /* pointers for real or simulated masks */
2 111
2 112 /* MISCELLANEOUS */
2 113
2 114 dcl 1 scs$processor_test_data aligned ext, /* info used for cpu testing */
2 115 (
2 116 2 active bit (1), /* = "1"b if cpu currently under test */
2 117 2 scu_state bit (2), /* state of scu being used for testing (see definition below) */
2 118 2 pad1 bit (4),
2 119 2 req_mem fixed bin (10), /* dedicated memory required to test this cpu */
2 120 2 cpu_tag fixed bin (5), /* tag of cpu under test */
2 121 2 scu_tag fixed bin (5), /* tag of scu being used for cpu testing */
2 122 2 mask_cpu fixed bin (5)
2 123 ) unaligned; /* tag of active cpu that has mask asigned to above scu */
2 124
2 125 /* scu_state = "00"b => SCU defined by scs$processor_test_data.scu_tag not yet effected */
2 126 /* scu_state = "01"b => all core removed from SCU, port mask not yet changed */
2 127 /* scu_state = "10"b => all core removed from SCU, port mask changed */
2 128 /* scu_state = "11"b => only 64k at base of SCU being used for testing, original port mask restored */
2 129
2 130 dcl scs$idle_aptep (0:7) ptr unaligned ext; /* pointer to idle process APTE for each processor */
2 131
2 132 dcl scs$connect_lock bit (36) aligned ext; /* lock for sending connects */
2 133 dcl scs$reconfig_lock bit (36) aligned ext; /* Lock used during reconfiguration */
2 134 dcl scs$trouble_flags bit (8) aligned ext; /* checkoff flags for sys_trouble stopping */
2 135 dcl scs$bos_restart_flags bit (8) aligned ext; /* checkoff flags for restarting after sys_trouble */
2 136 dcl scs$nprocessors fixed bin ext; /* number of runnung processors */
2 137 dcl scs$bos_processor_tag fixed bin (3) ext; /* CPU tag of processor running BOS */
2 138 dcl scs$faults_initialized bit (1) aligned ext; /* ON after faults have been enabled */
2 139 dcl scs$sys_trouble_pending bit (1) aligned ext; /* sys_trouble event is pending in the system */
2 140 dcl scs$fast_cam_pending (0:7) bit (36) aligned ext; /* checkoff cells for cam connect */
2 141 dcl scs$interrupt_controller fixed bin (3) ext; /* port number of low order controller */
2 142 dcl scs$processor_start_int_no fixed bin (5) ext; /* interrupt cell for starting a processor */
2 143 dcl scs$processor bit (8) aligned ext; /* bits ON for online CPUs */
2 144 dcl scs$processor_start_wait bit (8) aligned ext; /* checkoff flags for waiting for new processor */
2 145
2 146 dcl scs$trouble_dbrs (0:7) fixed bin (71); /* DBR values at system crash time */
2 147
2 148 dcl scs$port_addressing_word (0:7) bit (3) aligned ext; /* active module port number for each controller */
2 149
2 150 dcl scs$cfg_data (0:7) fixed bin (71) aligned ext; /* RSCR-CFG data from each controller */
2 151
2 152 dcl scs$cfg_data_save fixed bin (71) aligned ext; /* RSCR-CFG save area for ISOLTS CPU testing */
2 153
2 154 dcl scs$expanded_ports bit (1) unaligned dim (0:7) external;
2 155 /* Which ports have expanders */
2 156
2 157 dcl scs$processor_switch_data (0:4) bit (36) aligned ext; /* raw data from RSW 0 thru 4 */
2 158 dcl scs$processor_switch_template (0:4) bit (36) aligned ext; /* expected data from RSW 0 thru 4 */
2 159 dcl scs$processor_switch_compare (0:4) bit (36) aligned ext; /* discrepancies from expected data */
2 160 dcl scs$processor_switch_mask (0:4) bit (36) aligned ext; /* masks for comparing switch data */
2 161
2 162 dcl scs$processor_data_switch_value bit (36) aligned ext; /* Correct value for CPU data switches */
2 163
2 164 dcl scs$controller_config_size (0:7) fixed bin (14) aligned ext;
2 165 /* Controller size on config card */
2 166
2 167 dcl scs$reconfig_locker_id char (32) aligned ext; /* process group ID of process doing reconfiguration */
2 168
2 169 dcl scs$scas_page_table (0:31) bit (36) aligned external static;
2 170 /* PTWs for SCAS pages */
2 171
2 172 dcl scs$cycle_priority_template bit (7) aligned ext; /* template for setting anti-hog switches */
2 173 dcl scs$set_cycle_switches bit (1) aligned ext; /* flag to set ant-hog switches */
2 174
2 175
2 176 dcl (
2 177 IOM_PORT init (1),
2 178 CPU_PORT init (2),
2 179 BULK_PORT init (3)
2 180 ) fixed bin int static options (constant); /* values for scs$port_data.assigned */
2 181
2 182
2 183 /* END INCLUDE FILE scs.incl.pl1 */
50
51
52
53
54 port_info: entry (tag, enabled, base, size, interlace); /* entry to return info about a port */
55
56
57 rsw2p = addr (rsw_2_data); /* Set pointer. */
58 rswp = addr (rsw_1_3_data); /* Set pointer. */
59 call privileged_mode_ut$rsw (2, rsw_2_data); /* get the cpu type. */
60 if rsw2p -> dps8_rsw_2.cpu_type = 1 then do; /* if DPS8 cpu... */
61 if tag > 3 then do; /* can't have for than 4 scus on dps8 so... */
62 enabled = "0"b; /* tell caller this port disabled */
63 return;
64 end;
65 pip = addr (rsw_1_3.port_info (tag)); /* there can only be 4 SCUs... */
66 call privileged_mode_ut$rsw (1, rsw_1_3_data); /* Read port info. */
67 size = divide (dps8_mem_size_table (pi.mem_size), 1024, 17, 0);
68 base = bin (pi.port_assignment, 3) * size; /* Compute base address of memory. */
69 if pi.interlace_enable then /* If interlace is enabled ... */
70 if rsw2p -> dps8_rsw_2.interlace_info (tag) then /* If two-word interlace... */
71 interlace = 2;
72 else interlace = 4; /* If four-word interlace ... */
73 else interlace = 0; /* If no interlace ... */
74 end;
75 else do; /* must be a DPS or L68 cpu */
76 rsw4p = addr (rsw_4_data); /* Set pointer to data. */
77 if tag < 4 then do; /* Decide on RSW 1 or RSW 3 data. */
78 rsw = 1;
79 pip = addr (rsw_1_3.port_info (tag));
80 end;
81 else do;
82 rsw = 3;
83 pip = addr (rsw_1_3.port_info (tag - 4));
84 end;
85 call privileged_mode_ut$rsw (rsw, rsw_1_3_data); /* Read port info. */
86 call privileged_mode_ut$rsw (4, rsw_4_data); /* Read half/full and interlace type data. */
87 size = divide (dps_mem_size_table (pi.mem_size), 1024, 17, 0);
88 base = bin (pi.port_assignment, 3) * size; /* Compute base address of memory. */
89 if rsw4p -> rsw_4.half (tag) then
90 size = divide (size, 2, 17, 0); /* Halve the size if so indicated. */
91 if pi.interlace_enable then /* If interlace is enabled ... */
92 if rsw4p -> rsw_4.four (tag) then /* If two-word interlace ... */
93 interlace = 2;
94 else interlace = 4; /* If four-word interlace ... */
95 else interlace = 0; /* If no interlace ... */
96 end;
97 enabled = pi.port_enable; /* Return port enabled bit. */
98
99 return;
100
101
102 set_rsw_mask: entry (tag, enabled); /* entry to set mask for checking CPU switches */
103
104
105 if tag < 4 then do; /* Set appropriate RSW data. */
106 rswp = addr (scs$processor_switch_mask (1));
107 pip = addr (rsw_1_3.port_info (tag));
108 end;
109 else do;
110 rswp = addr (scs$processor_switch_mask (3));
111 pip = addr (rsw_1_3.port_info (tag - 4));
112 end;
113
114 pi.port_enable = enabled; /* Set or clear enabled bit. */
115
116 return;
117
118
119
120 init_rsw_mask: entry (tag, enabled); /* entry to set initial mask for switch checking */
121
122
123 if tag < 4 then do; /* Set appropriate RSW data. */
124 rswp = addr (scs$processor_switch_mask (1));
125 pip = addr (rsw_1_3.port_info (tag));
126 end;
127 else do;
128 rswp = addr (scs$processor_switch_mask (3));
129 pip = addr (rsw_1_3.port_info (tag - 4));
130 end;
131
132 pi.port_assignment = "111"b; /* Compare port assignment switches. */
133 pi.interlace_enable = "1"b; /* Compare interlace enable switches. */
134 pi.mem_size = 7; /* Compare mem size switches. */
135 pi.port_enable = enabled; /* Compare enable switch only if enabled. */
136
137 rswp = addr (scs$processor_switch_mask (4));
138 rsw_4.four (tag) = "1"b; /* Compare four-word interlace switches. */
139 rsw_4.half (tag) = "1"b; /* Compare half/full switches. */
140
141 if tag < 4 then do; /* Set appropriate RSW data. */
142 rswp = addr (scs$processor_switch_template (1));
143 pip = addr (rsw_1_3.port_info (tag));
144 end;
145 else do;
146 rswp = addr (scs$processor_switch_template (3));
147 pip = addr (rsw_1_3.port_info (tag - 4));
148 end;
149
150 pi.port_enable = "1"b; /* If compared, this bit must be ON. */
151
152 return;
153
154
155
156 end rsw_util;
SOURCE FILES USED IN THIS COMPILATION.
LINE NUMBER DATE MODIFIED NAME PATHNAME
0 11/11/89 0825.5 rsw_util.pl1 >special_ldd>install>MR12.3-1114>rsw_util.pl1
48 1 06/10/82 1045.2 rsw.incl.pl1 >ldd>include>rsw.incl.pl1
50 2 10/12/83 0943.5 scs.incl.pl1 >ldd>include>scs.incl.pl1
NAMES DECLARED IN THIS COMPILATION.
IDENTIFIER OFFSET LOC STORAGE CLASS DATA TYPE ATTRIBUTES AND REFERENCES
(* indicates a set context)
NAMES DECLARED BY DECLARE STATEMENT.
addr builtin function dcl 42 ref 57 58 65 76 79 83 106 107 110 111 124 125
128 129 137 142 143 146 147
base parameter fixed bin(17,0) dcl 28 set ref 54 68* 88*
bin builtin function dcl 42 ref 68 88
cpu_type 0(04) based fixed bin(2,0) level 2 packed packed unsigned unaligned dcl 1-25
ref 60
divide builtin function dcl 42 ref 67 87 89
dps8_mem_size_table 000000 constant fixed bin(24,0) initial array dcl 1-63 ref 67
dps8_rsw_2 based structure level 1 dcl 1-25
dps_mem_size_table 000010 constant fixed bin(24,0) initial array dcl 1-54 ref 87
enabled parameter bit(1) dcl 28 set ref 54 62* 97* 102 114 120 135
four 0(13) based bit(1) array level 3 packed packed unaligned dcl 1-47 set
ref 91 138*
half 0(14) based bit(1) array level 3 packed packed unaligned dcl 1-47 set
ref 89 139*
interlace parameter fixed bin(3,0) dcl 28 set ref 54 69* 72* 73* 91* 94* 95*
interlace_enable 0(05) based bit(1) level 2 packed packed unaligned dcl 46 set ref 69 91
133*
interlace_info based bit(1) array level 2 packed packed unaligned dcl 1-25 ref
69
mem_size 0(06) based fixed bin(3,0) level 2 packed packed unsigned unaligned dcl 46 set
ref 67 87 134*
pi based structure level 1 packed packed unaligned dcl 46
pip 000112 automatic pointer dcl 44 set ref 65* 67 68 69 79* 83* 87 88 91 97 107*
111* 114 125* 129* 132 133 134 135 143* 147* 150
port_assignment based bit(3) level 2 packed packed unaligned dcl 46 set ref 68 88
132*
port_enable 0(03) based bit(1) level 2 packed packed unaligned dcl 46 set ref 97
114* 135* 150*
port_info 0(13) based structure array level 2 in structure "rsw_4" packed packed
unaligned dcl 1-47 in procedure "rsw_util"
port_info based structure array level 2 in structure "rsw_1_3" packed packed
unaligned dcl 1-39 in procedure "rsw_util" set ref
65 79 83 107 111 125 129 143 147
privileged_mode_ut$rsw 000010 constant entry external dcl 40 ref 59 66 85 86
rsw 000110 automatic fixed bin(3,0) dcl 34 set ref 78* 82* 85*
rsw2p 000104 automatic pointer dcl 34 set ref 57* 60 69
rsw4p 000106 automatic pointer dcl 34 set ref 76* 89 91
rsw_1_3 based structure level 1 dcl 1-39
rsw_1_3_data 000100 automatic bit(36) dcl 34 set ref 58 66* 85*
rsw_2_data 000101 automatic bit(36) dcl 34 set ref 57 59*
rsw_4 based structure level 1 dcl 1-47
rsw_4_data 000102 automatic bit(36) dcl 34 set ref 76 86*
rswp 000114 automatic pointer dcl 1-11 set ref 58* 65 79 83 106* 107 110* 111 124*
125 128* 129 137* 138 139 142* 143 146* 147
scs$processor_switch_mask 000014 external static bit(36) array dcl 2-160 set ref 106 110 124 128 137
scs$processor_switch_template 000012 external static bit(36) array dcl 2-158 set ref 142 146
size parameter fixed bin(17,0) dcl 28 set ref 54 67* 68 87* 88 89* 89
tag parameter fixed bin(3,0) dcl 28 ref 54 61 65 69 77 79 83 89 91 102 105 107
111 120 123 125 129 138 139 141 143 147
NAMES DECLARED BY DECLARE STATEMENT AND NEVER REFERENCED.
BULK_PORT internal static fixed bin(17,0) initial dcl 2-176
CPU_PORT internal static fixed bin(17,0) initial dcl 2-176
IOM_PORT internal static fixed bin(17,0) initial dcl 2-176
dps_rsw_2 based structure level 1 dcl 1-13
rsw_valid internal static fixed bin(17,0) initial array dcl 1-66
scs$bos_processor_tag external static fixed bin(3,0) dcl 2-137
scs$bos_restart_flags external static bit(8) dcl 2-135
scs$cam_pair external static fixed bin(71,0) dcl 2-103
scs$cam_wait external static bit(8) dcl 2-104
scs$cfg_data external static fixed bin(71,0) array dcl 2-150
scs$cfg_data_save external static fixed bin(71,0) dcl 2-152
scs$connect_lock external static bit(36) dcl 2-132
scs$controller_config_size external static fixed bin(14,0) array dcl 2-164
scs$controller_data external static structure array level 1 dcl 2-6
scs$cow external static structure array level 1 dcl 2-65
scs$cow_ptrs external static structure array level 1 dcl 2-77
scs$cpu_test_mask external static bit(72) dcl 2-96
scs$cpu_test_pattern external static bit(36) dcl 2-99
scs$cycle_priority_template external static bit(7) dcl 2-172
scs$expanded_ports external static bit(1) array packed unaligned dcl 2-154
scs$fast_cam_pending external static bit(36) array dcl 2-140
scs$faults_initialized external static bit(1) dcl 2-138
scs$idle_aptep external static pointer array packed unaligned dcl 2-130
scs$interrupt_controller external static fixed bin(3,0) dcl 2-141
scs$mask_ptr external static pointer array packed unaligned dcl 2-110
scs$nprocessors external static fixed bin(17,0) dcl 2-136
scs$number_of_masks external static fixed bin(17,0) dcl 2-97
scs$open_level external static bit(72) dcl 2-94
scs$port_addressing_word external static bit(3) array dcl 2-148
scs$port_data external static structure array level 1 dcl 2-56
scs$processor external static bit(8) dcl 2-143
scs$processor_data external static structure array level 1 dcl 2-35
scs$processor_data_switch_value external static bit(36) dcl 2-162
scs$processor_start_int_no external static fixed bin(5,0) dcl 2-142
scs$processor_start_mask external static bit(72) dcl 2-95
scs$processor_start_pattern external static bit(36) dcl 2-98
scs$processor_start_wait external static bit(8) dcl 2-144
scs$processor_switch_compare external static bit(36) array dcl 2-159
scs$processor_switch_data external static bit(36) array dcl 2-157
scs$processor_test_data external static structure level 1 dcl 2-114
scs$read_mask external static bit(36) array dcl 2-109
scs$reconfig_general_cow external static structure level 1 dcl 2-82
scs$reconfig_lock external static bit(36) dcl 2-133
scs$reconfig_locker_id external static char(32) dcl 2-167
scs$scas_page_table external static bit(36) array dcl 2-169
scs$set_cycle_switches external static bit(1) dcl 2-173
scs$set_mask external static bit(36) array dcl 2-108
scs$sys_level external static bit(72) dcl 2-93
scs$sys_trouble_pending external static bit(1) dcl 2-139
scs$trouble_dbrs automatic fixed bin(71,0) array dcl 2-146
scs$trouble_flags external static bit(8) dcl 2-134
NAMES DECLARED BY EXPLICIT CONTEXT.
init_rsw_mask 000360 constant entry external dcl 120
port_info 000037 constant entry external dcl 54
rsw_util 000024 constant entry external dcl 26
set_rsw_mask 000317 constant entry external dcl 102
THERE WERE NO NAMES DECLARED BY CONTEXT OR IMPLICATION.
STORAGE REQUIREMENTS FOR THIS PROGRAM.
Object Text Link Symbol Defs Static
Start 0 0 576 614 471 606
Length 1024 471 16 174 105 0
BLOCK NAME STACK SIZE TYPE WHY NONQUICK/WHO SHARES STACK FRAME
rsw_util 86 external procedure is an external procedure.
STORAGE FOR AUTOMATIC VARIABLES.
STACK FRAME LOC IDENTIFIER BLOCK NAME
rsw_util 000100 rsw_1_3_data rsw_util
000101 rsw_2_data rsw_util
000102 rsw_4_data rsw_util
000104 rsw2p rsw_util
000106 rsw4p rsw_util
000110 rsw rsw_util
000112 pip rsw_util
000114 rswp rsw_util
THE FOLLOWING EXTERNAL OPERATORS ARE USED BY THIS PROGRAM.
call_ext_out return_mac ext_entry
THE FOLLOWING EXTERNAL ENTRIES ARE CALLED BY THIS PROGRAM.
privileged_mode_ut$rsw
THE FOLLOWING EXTERNAL VARIABLES ARE USED BY THIS PROGRAM.
scs$processor_switch_mask scs$processor_switch_template
LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC LINE LOC
26 000023 54 000031 57 000044 58 000046 59 000050 60 000062 61 000067
62 000073 63 000074 65 000075 66 000101 67 000114 68 000126 69 000135
72 000152 73 000155 74 000156 76 000157 77 000161 78 000165 79 000167
80 000174 82 000175 83 000177 85 000205 86 000216 87 000231 88 000243
89 000252 91 000265 94 000301 95 000304 97 000305 99 000312 102 000313
105 000324 106 000330 107 000334 108 000340 110 000341 111 000345 114 000351
116 000355 120 000356 123 000365 124 000371 125 000375 126 000401 128 000402
129 000406 132 000412 133 000415 134 000420 135 000423 137 000427 138 000432
139 000437 141 000442 142 000445 143 000450 144 000454 146 000455 147 000460
150 000464 152 000467
-----------------------------------------------------------
Historical Background
This edition of the Multics software materials and documentation is provided and donated
to Massachusetts Institute of Technology by Group BULL including BULL HN Information Systems Inc.
as a contribution to computer science knowledge.
This donation is made also to give evidence of the common contributions of Massachusetts Institute of Technology,
Bell Laboratories, General Electric, Honeywell Information Systems Inc., Honeywell BULL Inc., Groupe BULL
and BULL HN Information Systems Inc. to the development of this operating system.
Multics development was initiated by Massachusetts Institute of Technology Project MAC (1963-1970),
renamed the MIT Laboratory for Computer Science and Artificial Intelligence in the mid 1970s, under the leadership
of Professor Fernando Jose Corbato. Users consider that Multics provided the best software architecture
for managing computer hardware properly and for executing programs. Many subsequent operating systems
incorporated Multics principles.
Multics was distributed in 1975 to 2000 by Group Bull in Europe , and in the U.S. by Bull HN Information Systems Inc.,
as successor in interest by change in name only to Honeywell Bull Inc. and Honeywell Information Systems Inc. .
-----------------------------------------------------------
Permission to use, copy, modify, and distribute these programs and their documentation for any purpose and without
fee is hereby granted,provided that the below copyright notice and historical background appear in all copies
and that both the copyright notice and historical background and this permission notice appear in supporting
documentation, and that the names of MIT, HIS, BULL or BULL HN not be used in advertising or publicity pertaining
to distribution of the programs without specific prior written permission.
Copyright 1972 by Massachusetts Institute of Technology and Honeywell Information Systems Inc.
Copyright 2006 by BULL HN Information Systems Inc.
Copyright 2006 by Bull SAS
All Rights Reserved