From 2834a6bac74ec72e81f83ce162a96254ffa24b0d Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Tue, 21 May 2024 10:45:48 -0500 Subject: [PATCH 01/31] Revert "board: rockchip: Add early ADC button detect for RGxx3" This reverts commit 41a60d0e5cef54a59596a58940fa7c9cf071034b. On some of the supported devices the adc detect code always returns that the button has been pushed, and as a result the device will not boot normally. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 64 ---------------------- 1 file changed, 64 deletions(-) diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c index 099eea60c39..5c57b902d14 100644 --- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c +++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c @@ -6,14 +6,12 @@ #include #include #include -#include #include #include #include #include #include #include -#include #include #include #include @@ -21,8 +19,6 @@ #include #include -#define BOOT_BROM_DOWNLOAD 0xef08a53c - #define GPIO0_BASE 0xfdd60000 #define GPIO4_BASE 0xfe770000 #define GPIO_SWPORT_DR_L 0x0000 @@ -36,14 +32,6 @@ #define GPIO_WRITEMASK(bits) ((bits) << 16) -#define SARADC_BASE 0xfe720000 -#define SARADC_DATA 0x0000 -#define SARADC_STAS 0x0004 -#define SARADC_ADC_STATUS BIT(0) -#define SARADC_CTRL 0x0008 -#define SARADC_INPUT_SRC_MSK 0x7 -#define SARADC_POWER_CTRL BIT(3) - #define DTB_DIR "rockchip/" struct rg3xx_model { @@ -169,64 +157,12 @@ static const struct rg353_panel rg353_panel_details[] = { }, }; -/* - * The device has internal eMMC, and while some devices have an exposed - * clk pin you can ground to force a bypass not all devices do. As a - * result it may be possible for some devices to become a perma-brick - * if a corrupted TPL or SPL stage with a valid header is flashed to - * the internal eMMC. Add functionality to read ADC channel 0 (the func - * button) as early as possible in the boot process to provide some - * protection against this. If we ever get an open TPL stage, we should - * consider moving this function there. - */ -void read_func_button(void) -{ - int ret; - u32 reg; - - /* Turn off SARADC to reset it. */ - writel(0, (SARADC_BASE + SARADC_CTRL)); - - /* Enable channel 0 and power on SARADC. */ - writel(((0 & SARADC_INPUT_SRC_MSK) | SARADC_POWER_CTRL), - (SARADC_BASE + SARADC_CTRL)); - - /* - * Wait for data to be ready. Use timeout of 20000us from - * rockchip_saradc driver. - */ - ret = readl_poll_timeout((SARADC_BASE + SARADC_STAS), reg, - !(reg & SARADC_ADC_STATUS), 20000); - if (ret) { - printf("ADC Timeout"); - return; - } - - /* Read the data from the SARADC. */ - reg = readl((SARADC_BASE + SARADC_DATA)); - - /* Turn the SARADC back off so it's ready to be used again. */ - writel(0, (SARADC_BASE + SARADC_CTRL)); - - /* - * If the value is less than 30 the button is being pressed. - * Reset the device back into Rockchip download mode. - */ - if (reg <= 30) { - printf("download key pressed, entering download mode..."); - writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); - do_reset(NULL, 0, 0, NULL); - } -}; - /* * Start LED very early so user knows device is on. Set color * to red. */ void spl_board_init(void) { - read_func_button(); - /* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */ writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \ (GPIO_C7 | GPIO_C6 | GPIO_C5), From 7e55ff1f0ddfc24eb1efc1cf1ea4f0e8e564c33a Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Tue, 21 May 2024 10:45:49 -0500 Subject: [PATCH 02/31] board: rockchip: rgxx3: Use sdmmc0 as first device Some of the rgxx3 devices do not have a way to recover from a poor flash of a bootloader to eMMC. Set the device to always attempt to boot from sdmmc0 first which ensures that we can override the boot from emmc if we have a card present with a valid fit signature. The expectation is that this will protect from the very unlikely chance we have a valid FIT signature on the eMMC but the U-Boot stage fails for some other reason. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi index 793ed4ae8ae..c7e849816a6 100644 --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi @@ -4,7 +4,7 @@ / { chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc1, &sdmmc0; + u-boot,spl-boot-order = &sdmmc0, &sdhci; }; }; From 7d35a0cf70275e3ae438fce1329edbdc1202ad9d Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 5 Jun 2024 11:33:21 +0200 Subject: [PATCH 03/31] regulator: rk8xx: fix incorrect device used for _ldo_[sg]et_suspend_value _ldo_get_suspend_value and _ldo_set_suspend_value get passed the parent of the regulator (so the pmic) as first argument, therefore this udevice should be used for pmic_* callbacks instead of using the parent of the pmic. To avoid further confusion, let's rename the argument to pmic instead of dev, highlighting which kind of device we expect as argument. Fixes: f047e4ab9762 ("regulator: rk8xx: add indirection level for some ldo callbacks") Reported-by: Simon Glass Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Reviewed-by: Simon Glass Tested-by: Simon Glass # chromebook-bob --- drivers/power/regulator/rk8xx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c index 1bd4605d43a..cce3502f89c 100644 --- a/drivers/power/regulator/rk8xx.c +++ b/drivers/power/regulator/rk8xx.c @@ -1216,7 +1216,7 @@ static int pldo_set_value(struct udevice *dev, int uvolt) return _ldo_set_value(dev, info, uvolt); } -static int _ldo_set_suspend_value(struct udevice *dev, const struct rk8xx_reg_info *info, int uvolt) +static int _ldo_set_suspend_value(struct udevice *pmic, const struct rk8xx_reg_info *info, int uvolt) { int mask = info->vsel_mask; int val; @@ -1232,7 +1232,7 @@ static int _ldo_set_suspend_value(struct udevice *dev, const struct rk8xx_reg_in debug("%s: volt=%d, reg=0x%x, mask=0x%x, val=0x%x\n", __func__, uvolt, info->vsel_sleep_reg, mask, val); - return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val); + return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val); } static int ldo_set_suspend_value(struct udevice *dev, int uvolt) @@ -1259,7 +1259,7 @@ static int pldo_set_suspend_value(struct udevice *dev, int uvolt) return _ldo_set_suspend_value(dev->parent, info, uvolt); } -static int _ldo_get_suspend_value(struct udevice *dev, const struct rk8xx_reg_info *info) +static int _ldo_get_suspend_value(struct udevice *pmic, const struct rk8xx_reg_info *info) { int mask = info->vsel_mask; int val, ret; @@ -1267,7 +1267,7 @@ static int _ldo_get_suspend_value(struct udevice *dev, const struct rk8xx_reg_in if (info->vsel_sleep_reg == NA) return -ENOSYS; - ret = pmic_reg_read(dev->parent, info->vsel_sleep_reg); + ret = pmic_reg_read(pmic, info->vsel_sleep_reg); if (ret < 0) return ret; From 9b7e7d6c1779983bbaaabb03399f0998a8fb088e Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 5 Jun 2024 11:33:22 +0200 Subject: [PATCH 04/31] regulator: rk8xx: pass pmic udevice instead of regulator to all internal functions For the sake of consistency, make all internal (starting with _) functions expect a pmic udevice instead of a regulator udevice. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Reviewed-by: Simon Glass Tested-by: Simon Glass # chromebook-bob --- drivers/power/regulator/rk8xx.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c index cce3502f89c..bd5a37e718f 100644 --- a/drivers/power/regulator/rk8xx.c +++ b/drivers/power/regulator/rk8xx.c @@ -1134,14 +1134,14 @@ static int buck_get_enable(struct udevice *dev) return _buck_get_enable(dev->parent, buck); } -static int _ldo_get_value(struct udevice *dev, const struct rk8xx_reg_info *info) +static int _ldo_get_value(struct udevice *pmic, const struct rk8xx_reg_info *info) { int mask = info->vsel_mask; int ret, val; if (info->vsel_reg == NA) return -ENOSYS; - ret = pmic_reg_read(dev->parent, info->vsel_reg); + ret = pmic_reg_read(pmic, info->vsel_reg); if (ret < 0) return ret; val = ret & mask; @@ -1154,7 +1154,7 @@ static int ldo_get_value(struct udevice *dev) int ldo = dev->driver_data - 1; const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0); - return _ldo_get_value(dev, info); + return _ldo_get_value(dev->parent, info); } static int nldo_get_value(struct udevice *dev) @@ -1162,7 +1162,7 @@ static int nldo_get_value(struct udevice *dev) int nldo = dev->driver_data - 1; const struct rk8xx_reg_info *info = get_nldo_reg(dev->parent, nldo, 0); - return _ldo_get_value(dev, info); + return _ldo_get_value(dev->parent, info); } static int pldo_get_value(struct udevice *dev) @@ -1170,10 +1170,10 @@ static int pldo_get_value(struct udevice *dev) int pldo = dev->driver_data - 1; const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, pldo, 0); - return _ldo_get_value(dev, info); + return _ldo_get_value(dev->parent, info); } -static int _ldo_set_value(struct udevice *dev, const struct rk8xx_reg_info *info, int uvolt) +static int _ldo_set_value(struct udevice *pmic, const struct rk8xx_reg_info *info, int uvolt) { int mask = info->vsel_mask; int val; @@ -1189,7 +1189,7 @@ static int _ldo_set_value(struct udevice *dev, const struct rk8xx_reg_info *info debug("%s: volt=%d, reg=0x%x, mask=0x%x, val=0x%x\n", __func__, uvolt, info->vsel_reg, mask, val); - return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val); + return pmic_clrsetbits(pmic, info->vsel_reg, mask, val); } static int ldo_set_value(struct udevice *dev, int uvolt) @@ -1197,7 +1197,7 @@ static int ldo_set_value(struct udevice *dev, int uvolt) int ldo = dev->driver_data - 1; const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt); - return _ldo_set_value(dev, info, uvolt); + return _ldo_set_value(dev->parent, info, uvolt); } static int nldo_set_value(struct udevice *dev, int uvolt) @@ -1205,7 +1205,7 @@ static int nldo_set_value(struct udevice *dev, int uvolt) int nldo = dev->driver_data - 1; const struct rk8xx_reg_info *info = get_nldo_reg(dev->parent, nldo, uvolt); - return _ldo_set_value(dev, info, uvolt); + return _ldo_set_value(dev->parent, info, uvolt); } static int pldo_set_value(struct udevice *dev, int uvolt) @@ -1213,7 +1213,7 @@ static int pldo_set_value(struct udevice *dev, int uvolt) int pldo = dev->driver_data - 1; const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, pldo, uvolt); - return _ldo_set_value(dev, info, uvolt); + return _ldo_set_value(dev->parent, info, uvolt); } static int _ldo_set_suspend_value(struct udevice *pmic, const struct rk8xx_reg_info *info, int uvolt) From f3adcec410ade6de77427c6b80bd9a8c75308bad Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 5 Jun 2024 11:33:23 +0200 Subject: [PATCH 05/31] regulator: rk8xx: clarify operator precedence My linter complains that the order isn't clear enough so let's put parentheses around the ternary condition to make it happy. Signed-off-by: Quentin Schulz Reviewed-by: Mattijs Korpershoek Reviewed-by: Kever Yang Reviewed-by: Simon Glass Tested-by: Simon Glass # chromebook-bob --- drivers/power/regulator/rk8xx.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c index bd5a37e718f..3125835bc07 100644 --- a/drivers/power/regulator/rk8xx.c +++ b/drivers/power/regulator/rk8xx.c @@ -520,7 +520,7 @@ static int _buck_get_enable(struct udevice *pmic, int buck) if (ret < 0) return ret; - return ret & mask ? true : false; + return (ret & mask) ? true : false; } static int _buck_set_suspend_enable(struct udevice *pmic, int buck, bool enable) @@ -585,7 +585,7 @@ static int _buck_get_suspend_enable(struct udevice *pmic, int buck) val = pmic_reg_read(pmic, RK816_REG_DCDC_SLP_EN); if (val < 0) return val; - ret = val & mask ? 1 : 0; + ret = (val & mask) ? 1 : 0; break; case RK806_ID: { @@ -608,7 +608,7 @@ static int _buck_get_suspend_enable(struct udevice *pmic, int buck) val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF1); if (val < 0) return val; - ret = val & mask ? 0 : 1; + ret = (val & mask) ? 0 : 1; break; case RK809_ID: case RK817_ID: @@ -620,7 +620,7 @@ static int _buck_get_suspend_enable(struct udevice *pmic, int buck) val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0)); if (val < 0) return val; - ret = val & mask ? 1 : 0; + ret = (val & mask) ? 1 : 0; break; default: ret = -EINVAL; @@ -723,7 +723,7 @@ static int _ldo_get_enable(struct udevice *pmic, int ldo) if (ret < 0) return ret; - return ret & mask ? true : false; + return (ret & mask) ? true : false; } static int _nldo_get_enable(struct udevice *pmic, int nldo) @@ -980,7 +980,7 @@ static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo) val = pmic_reg_read(pmic, RK816_REG_LDO_SLP_EN); if (val < 0) return val; - ret = val & mask ? 1 : 0; + ret = (val & mask) ? 1 : 0; break; case RK808_ID: case RK818_ID: @@ -988,7 +988,7 @@ static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo) val = pmic_reg_read(pmic, REG_SLEEP_SET_OFF2); if (val < 0) return val; - ret = val & mask ? 0 : 1; + ret = (val & mask) ? 0 : 1; break; case RK809_ID: case RK817_ID: @@ -997,13 +997,13 @@ static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo) val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(0)); if (val < 0) return val; - ret = val & mask ? 1 : 0; + ret = (val & mask) ? 1 : 0; } else { mask = 1 << ldo; val = pmic_reg_read(pmic, RK817_POWER_SLP_EN(1)); if (val < 0) return val; - ret = val & mask ? 1 : 0; + ret = (val & mask) ? 1 : 0; } break; } @@ -1438,7 +1438,7 @@ static int switch_get_enable(struct udevice *dev) if (ret < 0) return ret; - return ret & mask ? true : false; + return (ret & mask) ? true : false; } static int switch_set_suspend_value(struct udevice *dev, int uvolt) @@ -1493,21 +1493,21 @@ static int switch_get_suspend_enable(struct udevice *dev) val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1); if (val < 0) return val; - ret = val & mask ? 0 : 1; + ret = (val & mask) ? 0 : 1; break; case RK809_ID: mask = 1 << (sw + 6); val = pmic_reg_read(dev->parent, RK817_POWER_SLP_EN(0)); if (val < 0) return val; - ret = val & mask ? 1 : 0; + ret = (val & mask) ? 1 : 0; break; case RK818_ID: mask = 1 << 6; val = pmic_reg_read(dev->parent, REG_SLEEP_SET_OFF1); if (val < 0) return val; - ret = val & mask ? 0 : 1; + ret = (val & mask) ? 0 : 1; break; } From 5693c20b95dfc7c2ac8dcae506ea89fe53cb820e Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 12 May 2024 12:16:14 +0000 Subject: [PATCH 06/31] pinctrl: rockchip: rk3188: Fix support for IOMUX_GPIO_ONLY flag GPIO0_A0-A7 on RK3188 is IOMUX_GPIO_ONLY, however, trying to set gpio mux return an -ENOTSUPP error code. Fix this by validating using the mux function type and not the iomux flag. Based on Linux commit c4a532dee6b6 ("pinctrl: rockchip: handle first half of rk3188-bank0 correctly"). Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rockchip-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 8ef089994f4..a3cdadb86b1 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -172,7 +172,7 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank, } if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { - if (mux != IOMUX_GPIO_ONLY) { + if (mux != RK_FUNC_GPIO) { debug("pin %d only supports a gpio mux\n", pin); return -ENOTSUPP; } From b4be11858e5160aad57374e97402f105cf5bed85 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 12 May 2024 12:16:15 +0000 Subject: [PATCH 07/31] pinctrl: rockchip: rv1126: Fix support for IOMUX_L_SOURCE_PMU flag GPIO0_C0-C4 iomux is set using PMUGRF_GPIO0C_IOMUX_L reg on RV1126. This is indicated using the IOMUX_L_SOURCE_PMU flag. Fix reading current mux by fully adopting the IOMUX_L_SOURCE_PMU related code in Linux kernel. Based on Linux commit fd4ea48688c6 ("pinctrl: rockchip: Add RV1126 pinctrl support"). Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rockchip-core.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index a3cdadb86b1..ca93b52ecc7 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -132,8 +132,12 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) return RK_FUNC_GPIO; - regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) - ? priv->regmap_pmu : priv->regmap_base; + if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + regmap = priv->regmap_pmu; + else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) + regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; + else + regmap = priv->regmap_base; /* get basic quadrupel of mux registers and the correct reg inside */ mux_type = bank->iomux[iomux_num].type; @@ -532,12 +536,14 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d /* preset iomux offset value, set new start value */ if (iom->offset >= 0) { - if (iom->type & IOMUX_SOURCE_PMU) + if ((iom->type & IOMUX_SOURCE_PMU) || + (iom->type & IOMUX_L_SOURCE_PMU)) pmu_offs = iom->offset; else grf_offs = iom->offset; } else { /* set current iomux offset */ - iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? + iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || + (iom->type & IOMUX_L_SOURCE_PMU)) ? pmu_offs : grf_offs; } From 785b7b0ba359109ae1db0f1639c7272da18c5c67 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 12 May 2024 12:16:16 +0000 Subject: [PATCH 08/31] pinctrl: rockchip: rk3588: Fix support for rockchip_get_mux() GPIO IOMUX control is located at PMU2_IOC or BUS_IOC offset on RK3588. Based on Linux commit fdc33eba11c5 ("pinctrl/rockchip: add rk3588 support"). Compared to the Linux commit, this include a fix so that the iomux of GPIO0_B4-D7 is reported correctly. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- .../pinctrl/rockchip/pinctrl-rockchip-core.c | 24 ++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index ca93b52ecc7..8245b854e63 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -14,10 +14,10 @@ #include #include "pinctrl-rockchip.h" +#include #define MAX_ROCKCHIP_PINS_ENTRIES 30 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 -#define RK_FUNC_GPIO 0 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) { @@ -147,6 +147,28 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) if (bank->recalced_mask & BIT(pin)) rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + if (IS_ENABLED(CONFIG_ROCKCHIP_RK3588)) { + if (bank->bank_num == 0) { + if (pin >= RK_PB4 && pin <= RK_PD7) { + u32 reg0 = 0; + + reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ + ret = regmap_read(regmap, reg0, &val); + if (ret) + return ret; + + ret = ((val >> bit) & mask); + if (ret != 8) + return ret; + + reg = reg + 0x8000; /* BUS_IOC_BASE */ + regmap = priv->regmap_base; + } + } else if (bank->bank_num > 0) { + reg += 0x8000; /* BUS_IOC_BASE */ + } + } + ret = regmap_read(regmap, reg, &val); if (ret) return ret; From c3fda436addbedbdb9acb425bfbe183b09a043cb Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 6 Jun 2024 13:44:04 +0200 Subject: [PATCH 09/31] rockchip: mkimage: fix mkimage -l for header v1 There are two paths to reach this function, either through mkimage -l or through dumpimage -l. The latter passes a NULL imagename while the former passes an empty string. Therefore, let's make both tools behave the same by handling the empty string the same way as for NULL. Without this, the only way to get some information out of mkimage -l is to provide "-n rk3399" for example, which isn't documented in the usage of the tool. Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- tools/rkcommon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 12c27b34eaa..3e52236b15a 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -470,7 +470,7 @@ int rkcommon_verify_header(unsigned char *buf, int size, * If no 'imagename' is specified via the commandline (e.g. if this is * 'dumpimage -l' w/o any further constraints), we accept any spl_info. */ - if (params->imagename == NULL) + if (params->imagename == NULL || !strlen(params->imagename)) return 0; /* Match the 'imagename' against the 'spl_hdr' found */ From 7d7e5fec15230ea1a6d91526211f7abcf8dfb18e Mon Sep 17 00:00:00 2001 From: Mattijs Korpershoek Date: Tue, 4 Jun 2024 17:15:21 +0200 Subject: [PATCH 10/31] bootstd: Fix a handful of doc typos in bootmeth Fix some trivial typos found by browsing the code. Done with flyspell. Reviewed-by: Quentin Schulz Signed-off-by: Mattijs Korpershoek Reviewed-by: Guillaume La Roque Reviewed-by: Julien Masson --- include/bootmeth.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/include/bootmeth.h b/include/bootmeth.h index 0fc36104ece..9f94f8c06c8 100644 --- a/include/bootmeth.h +++ b/include/bootmeth.h @@ -40,7 +40,7 @@ struct bootmeth_ops { /** * get_state_desc() - get detailed state information * - * Prodecues a textual description of the state of the bootmeth. This + * Produces a textual description of the state of the boot method. This * can include newline characters if it extends to multiple lines. It * must be a nul-terminated string. * @@ -138,7 +138,7 @@ struct bootmeth_ops { * @dev: Bootmethod device to boot * @bflow: Bootflow to boot * Return: does not return on success, since it should boot the - * Operating Systemn. Returns -EFAULT if that fails, -ENOTSUPP if + * operating system. Returns -EFAULT if that fails, -ENOTSUPP if * trying method resulted in finding out that is not actually * supported for this boot and should not be tried again unless * something changes, other -ve on other error @@ -151,7 +151,7 @@ struct bootmeth_ops { /** * bootmeth_get_state_desc() - get detailed state information * - * Prodecues a textual description of the state of the bootmeth. This + * Produces a textual description of the state of the boot method. This * can include newline characters if it extends to multiple lines. It * must be a nul-terminated string. * @@ -244,7 +244,7 @@ int bootmeth_read_file(struct udevice *dev, struct bootflow *bflow, * @dev: Bootmethod device to use * @bflow: Bootflow to read * Return: does not return on success, since it should boot the - * Operating Systemn. Returns -EFAULT if that fails, other -ve on + * operating system. Returns -EFAULT if that fails, other -ve on * other error */ int bootmeth_read_all(struct udevice *dev, struct bootflow *bflow); @@ -255,7 +255,7 @@ int bootmeth_read_all(struct udevice *dev, struct bootflow *bflow); * @dev: Bootmethod device to boot * @bflow: Bootflow to boot * Return: does not return on success, since it should boot the - * Operating Systemn. Returns -EFAULT if that fails, other -ve on + * operating system. Returns -EFAULT if that fails, other -ve on * other error */ int bootmeth_boot(struct udevice *dev, struct bootflow *bflow); @@ -264,7 +264,7 @@ int bootmeth_boot(struct udevice *dev, struct bootflow *bflow); * bootmeth_setup_iter_order() - Set up the ordering of bootmeths to scan * * This sets up the ordering information in @iter, based on the selected - * ordering of the bootmethds in bootstd_priv->bootmeth_order. If there is no + * ordering of the boot methods in bootstd_priv->bootmeth_order. If there is no * ordering there, then all bootmethods are added * * @iter: Iterator to update with the order From f76f4f4be6b8c7b0bba22b83123d4c47077d8463 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Wed, 12 Jun 2024 09:16:37 -0700 Subject: [PATCH 11/31] doc: board: phytec: phycore-am62x: Fix Link to Documentation We moved our documentation to another hoster and therefore the URL changed. Point to the latest documentation instead of release versions to not link out-dated documentation. Signed-off-by: Daniel Schultz Reviewed-by: Wadim Egorov --- doc/board/phytec/phycore-am62x.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst index bc6d5246694..681ac536125 100644 --- a/doc/board/phytec/phycore-am62x.rst +++ b/doc/board/phytec/phycore-am62x.rst @@ -155,4 +155,4 @@ Further Information ------------------- Please see :doc:`../ti/am62x_sk` chapter for further AM62 SoC related documentation -and https://docs.phytec.com/phycore-am62x for vendor documentation. +and https://docs.phytec.com/projects/yocto-phycore-am62x/en/latest/ for vendor documentation. From ca16205b5b162db24461f1f6b01668a47182d02e Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Wed, 12 Jun 2024 09:16:38 -0700 Subject: [PATCH 12/31] doc: board: phytec: phycore-am64x: Fix Link to Documentation We moved our documentation to another hoster and therefore the URL changed. Point to the latest documentation instead of release versions to not link out-dated documentation. Signed-off-by: Daniel Schultz --- doc/board/phytec/phycore-am64x.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/board/phytec/phycore-am64x.rst b/doc/board/phytec/phycore-am64x.rst index a27ad01027b..c99d8f6dd58 100644 --- a/doc/board/phytec/phycore-am64x.rst +++ b/doc/board/phytec/phycore-am64x.rst @@ -156,4 +156,4 @@ Further Information ------------------- Please see :doc:`../ti/am64x_evm` chapter for further AM64 SoC related documentation -and https://docs.phytec.com/phycore-am64x for vendor documentation. +and https://docs.phytec.com/projects/yocto-phycore-am64x/en/latest/ for vendor documentation. From 58e0e8b26a29ee3400f5b1dbdc186397c06e701d Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Wed, 12 Jun 2024 09:16:39 -0700 Subject: [PATCH 13/31] doc: board: phytec: phycore-am64: Fix phyBOARD Name The Carrier-Board for the pyhCORE-AM64x is called phyBOARD-Electra. Signed-off-by: Daniel Schultz --- doc/board/phytec/phycore-am64x.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/board/phytec/phycore-am64x.rst b/doc/board/phytec/phycore-am64x.rst index c99d8f6dd58..ad9f47d9dfd 100644 --- a/doc/board/phytec/phycore-am64x.rst +++ b/doc/board/phytec/phycore-am64x.rst @@ -9,7 +9,7 @@ SoM (System on Module) featuring TI's AM64x SoC. It can be used in combination with different carrier boards. This module can come with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM64x family. -A development Kit, called `phyBOARD-Lyra `_ +A development Kit, called `phyBOARD-Electra `_ is used as a carrier board reference design around the AM64x SoM. Quickstart From 2dc1134b84758a1a72f0733260c621982656d75f Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Fri, 14 Jun 2024 15:09:50 +0300 Subject: [PATCH 14/31] tpm: measure DTB in PCR1 instead of PCR0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PC client spec [0], doesn't describe measurements for DTBs. It does describe what do to for ACPI tables though. There is a description for ACPI in 3.3.4.1 PCR[0] – SRTM, POST BIOS, and Embedded Drivers and they explicitly mention ACPI in there. There's no mention of ACPI in 3.3.4.2 PCR[1] – Host Platform Configuration. However, in Figure 6 -- PCR Mapping of UEFI Components ACPI is shown in PCR1. The general description also mentions PCR0 is for code and PCR1 is for data such as ACPI and SMBIOS. So let's switch over the DTB measurements to PCR1 which seems a better fit. [0] https://trustedcomputinggroup.org/resource/pc-client-specific-platform-firmware-profile-specification Reported-by: Heinrich Schuchardt Signed-off-by: Ilias Apalodimas Reviewed-by: Eddie James --- boot/bootm.c | 2 +- lib/efi_loader/efi_tcg2.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/boot/bootm.c b/boot/bootm.c index 032f5a4a160..9879e1bba4e 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -964,7 +964,7 @@ int bootm_measure(struct bootm_headers *images) goto unmap_initrd; if (IS_ENABLED(CONFIG_MEASURE_DEVICETREE)) { - ret = tcg2_measure_data(dev, &elog, 0, images->ft_len, + ret = tcg2_measure_data(dev, &elog, 1, images->ft_len, (u8 *)images->ft_addr, EV_TABLE_OF_DEVICES, strlen("dts") + 1, diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c index 945aafb847d..d56bd5657c8 100644 --- a/lib/efi_loader/efi_tcg2.c +++ b/lib/efi_loader/efi_tcg2.c @@ -1331,7 +1331,7 @@ efi_status_t efi_tcg2_measure_dtb(void *dtb) sha256_update(&hash_ctx, (u8 *)dtb + fdt_off_mem_rsvmap(dtb), rsvmap_size); sha256_finish(&hash_ctx, blob->data + blob->blob_description_size); - ret = measure_event(dev, 0, EV_POST_CODE, event_size, (u8 *)blob); + ret = measure_event(dev, 1, EV_POST_CODE, event_size, (u8 *)blob); free(blob); return ret; From 3d2a0006ba5a583e4398fa8045ebf1a799807ddf Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Fri, 14 Jun 2024 15:14:03 +0300 Subject: [PATCH 15/31] doc: describe UEFI measured boot We currently only describe the process to enable measured boot using bootm. Describe the UEFI requirements as well which predate bootm. Signed-off-by: Ilias Apalodimas Reviewed-by: Heinrich Schuchardt --- doc/usage/measured_boot.rst | 35 +++++++++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/doc/usage/measured_boot.rst b/doc/usage/measured_boot.rst index 9691904a9d8..05c439e9ac6 100644 --- a/doc/usage/measured_boot.rst +++ b/doc/usage/measured_boot.rst @@ -7,19 +7,46 @@ U-Boot can perform a measured boot, the process of hashing various components of the boot process, extending the results in the TPM and logging the component's measurement in memory for the operating system to consume. +The functionality is available when booting via the EFI subsystem or 'bootm' +command. + +UEFI measured boot +------------------ + +The EFI subsystem implements the `EFI TCG protocol +`_ +and the `TCG PC Client Specific Platform Firmware Profile Specification +`_ +which defines the binaries to be measured and the corresponding PCRs to be used. + +Requirements +~~~~~~~~~~~~ + +* A hardware TPM 2.0 supported by an enabled U-Boot driver +* CONFIG_EFI_TCG2_PROTOCOL=y +* CONFIG_EFI_TCG2_PROTOCOL_EVENTLOG_SIZE=y +* optional CONFIG_EFI_TCG2_PROTOCOL_MEASURE_DTB=y will measure the loaded DTB + in PCR 1 + +Legacy measured boot +-------------------- + +The commands booti, bootm, and bootz can be used for measured boot +using the legacy entry point of the Linux kernel. + By default, U-Boot will measure the operating system (linux) image, the initrd image, and the "bootargs" environment variable. By enabling -CONFIG_MEASURE_DEVICETREE, U-Boot will also measure the devicetree image. +CONFIG_MEASURE_DEVICETREE, U-Boot will also measure the devicetree image in PCR1. The operating system typically would verify that the hashes found in the TPM PCRs match the contents of the event log. This can further be checked against the hash results of previous boots. Requirements ------------- +~~~~~~~~~~~~ -* A hardware TPM 2.0 supported by the U-Boot drivers -* CONFIG_TPM=y +* A hardware TPM 2.0 supported by an enabled U-Boot driver +* CONFIG_TPMv2=y * CONFIG_MEASURED_BOOT=y * Device-tree configuration of the TPM device to specify the memory area for event logging. The TPM device node must either contain a phandle to From 22447c9a3cc289d345fc8a396a71579aaa5b7b6d Mon Sep 17 00:00:00 2001 From: Alexander Dahl Date: Tue, 11 Jun 2024 16:40:31 +0200 Subject: [PATCH 16/31] doc: Fix link reference to general verified boot docs Fixes: ad29e08b79fd ("doc: Bring in FIT signature files") Signed-off-by: Alexander Dahl Reviewed-by: Simon Glass --- doc/usage/fit/signature.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/usage/fit/signature.rst b/doc/usage/fit/signature.rst index 03a71b5192d..b868dcbf9fd 100644 --- a/doc/usage/fit/signature.rst +++ b/doc/usage/fit/signature.rst @@ -15,7 +15,7 @@ that it can be verified using a public key later. Provided that the private key is kept secret and the public key is stored in a non-volatile place, any image can be verified in this way. -See verified-boot.txt for more general information on verified boot. +See :doc:`verified-boot` for more general information on verified boot. Concepts From de88d57a2e08520a6762ab6bb24ebffc6d271026 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 20 Apr 2024 00:03:09 +0200 Subject: [PATCH 17/31] ARM: dts: stm32: Ping IWDG on exit from PSCI suspend code Make sure the OS would not get any spurious IWDG pretimeout IRQ right after the system wakes up. This may happen in case the SoC got woken up by another source than the IWDG pretimeout and the pretimeout IRQ arrived immediately afterward, but too late to be handled by the suspend main loop. In case either of the IWDG is enabled, ping it first and then return to the OS. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard Reviewed-by: Igor Opaniuk --- arch/arm/mach-stm32mp/stm32mp1/psci.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c index 4f2379df45f..e99103910d9 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c @@ -808,6 +808,27 @@ void __secure psci_system_suspend(u32 __always_unused function_id, writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR); clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); + /* + * Make sure the OS would not get any spurious IWDG pretimeout IRQ + * right after the system wakes up. This may happen in case the SoC + * got woken up by another source than the IWDG pretimeout and the + * pretimeout IRQ arrived immediately afterward, but too late to be + * handled by the main loop above. In case either of the IWDG is + * enabled, ping it first and then return to the OS. + */ + + /* Ping IWDG1 and ACK pretimer IRQ */ + if (gic_enabled[4] & BIT(22)) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR); + } + + /* Ping IWDG2 and ACK pretimer IRQ */ + if (gic_enabled[4] & BIT(23)) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR); + } + /* * The system has resumed successfully. Rewrite LR register stored * on stack with 'ep' value, so that on return from this PSCI call, From 6be6a6b4ddd9ebf787fa7bcd0f1e953a5894e3f4 Mon Sep 17 00:00:00 2001 From: Arseniy Krasnov Date: Thu, 30 Nov 2023 14:24:05 +0300 Subject: [PATCH 18/31] mtd: rawnand: macronix: OTP access for MX30LFxG18AC Support for OTP area access on MX30LFxG18AC chip series. Link: https://lore.kernel.org/all/20231130112405.92196-1-avkrasnov@salutedevices.com Signed-off-by: Arseniy Krasnov Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/nand_macronix.c | 170 +++++++++++++++++++++++++++ 1 file changed, 170 insertions(+) diff --git a/drivers/mtd/nand/raw/nand_macronix.c b/drivers/mtd/nand/raw/nand_macronix.c index dc972e59092..4c6ddd92331 100644 --- a/drivers/mtd/nand/raw/nand_macronix.c +++ b/drivers/mtd/nand/raw/nand_macronix.c @@ -16,13 +16,183 @@ * GNU General Public License for more details. */ +#include #include +#define ONFI_FEATURE_ADDR_30LFXG18AC_OTP 0x90 +#define MACRONIX_30LFXG18AC_OTP_START_PAGE 2 +#define MACRONIX_30LFXG18AC_OTP_PAGES 30 +#define MACRONIX_30LFXG18AC_OTP_PAGE_SIZE 2112 +#define MACRONIX_30LFXG18AC_OTP_SIZE_BYTES \ + (MACRONIX_30LFXG18AC_OTP_PAGES * \ + MACRONIX_30LFXG18AC_OTP_PAGE_SIZE) + +#define MACRONIX_30LFXG18AC_OTP_EN BIT(0) + +static int macronix_30lfxg18ac_get_otp_info(struct mtd_info *mtd, size_t len, + size_t *retlen, + struct otp_info *buf) +{ + if (len < sizeof(*buf)) + return -EINVAL; + + /* Always report that OTP is unlocked. Reason is that this + * type of flash chip doesn't provide way to check that OTP + * is locked or not: subfeature parameter is implemented as + * volatile register. Technically OTP region could be locked + * and become readonly, but as there is no way to check it, + * don't allow to lock it ('_lock_user_prot_reg' callback + * always returns -EOPNOTSUPP) and thus we report that OTP + * is unlocked. + */ + buf->locked = 0; + buf->start = 0; + buf->length = MACRONIX_30LFXG18AC_OTP_SIZE_BYTES; + + *retlen = sizeof(*buf); + + return 0; +} + +static int macronix_30lfxg18ac_otp_enable(struct nand_chip *nand) +{ + u8 feature_buf[ONFI_SUBFEATURE_PARAM_LEN] = { 0 }; + struct mtd_info *mtd; + + mtd = nand_to_mtd(nand); + feature_buf[0] = MACRONIX_30LFXG18AC_OTP_EN; + + return nand->onfi_set_features(mtd, nand, ONFI_FEATURE_ADDR_30LFXG18AC_OTP, feature_buf); +} + +static int macronix_30lfxg18ac_otp_disable(struct nand_chip *nand) +{ + u8 feature_buf[ONFI_SUBFEATURE_PARAM_LEN] = { 0 }; + struct mtd_info *mtd; + + mtd = nand_to_mtd(nand); + return nand->onfi_set_features(mtd, nand, ONFI_FEATURE_ADDR_30LFXG18AC_OTP, feature_buf); +} + +static int __macronix_30lfxg18ac_rw_otp(struct mtd_info *mtd, + loff_t offs_in_flash, + size_t len, size_t *retlen, + u_char *buf, bool write) +{ + struct nand_chip *nand; + size_t bytes_handled; + off_t offs_in_page; + u64 page; + int ret; + + nand = mtd_to_nand(mtd); + nand->select_chip(mtd, 0); + + ret = macronix_30lfxg18ac_otp_enable(nand); + if (ret) + goto out_otp; + + page = offs_in_flash; + /* 'page' will be result of division. */ + offs_in_page = do_div(page, MACRONIX_30LFXG18AC_OTP_PAGE_SIZE); + bytes_handled = 0; + + while (bytes_handled < len && + page < MACRONIX_30LFXG18AC_OTP_PAGES) { + size_t bytes_to_handle; + u64 phys_page = page + MACRONIX_30LFXG18AC_OTP_START_PAGE; + + bytes_to_handle = min_t(size_t, len - bytes_handled, + MACRONIX_30LFXG18AC_OTP_PAGE_SIZE - + offs_in_page); + + if (write) + ret = nand_prog_page_op(nand, phys_page, offs_in_page, + &buf[bytes_handled], bytes_to_handle); + else + ret = nand_read_page_op(nand, phys_page, offs_in_page, + &buf[bytes_handled], bytes_to_handle); + if (ret) + goto out_otp; + + bytes_handled += bytes_to_handle; + offs_in_page = 0; + page++; + } + + *retlen = bytes_handled; + +out_otp: + if (ret) + dev_err(mtd->dev, "failed to perform OTP IO: %i\n", ret); + + ret = macronix_30lfxg18ac_otp_disable(nand); + if (ret) + dev_err(mtd->dev, "failed to leave OTP mode after %s\n", + write ? "write" : "read"); + + nand->select_chip(mtd, -1); + + return ret; +} + +static int macronix_30lfxg18ac_write_otp(struct mtd_info *mtd, loff_t to, + size_t len, size_t *rlen, + u_char *buf) +{ + return __macronix_30lfxg18ac_rw_otp(mtd, to, len, rlen, (u_char *)buf, + true); +} + +static int macronix_30lfxg18ac_read_otp(struct mtd_info *mtd, loff_t from, + size_t len, size_t *rlen, + u_char *buf) +{ + return __macronix_30lfxg18ac_rw_otp(mtd, from, len, rlen, buf, false); +} + +static int macronix_30lfxg18ac_lock_otp(struct mtd_info *mtd, loff_t from, + size_t len) +{ + /* See comment in 'macronix_30lfxg18ac_get_otp_info()'. */ + return -EOPNOTSUPP; +} + +static void macronix_nand_setup_otp(struct nand_chip *chip) +{ + static const char * const supported_otp_models[] = { + "MX30LF1G18AC", + "MX30LF2G18AC", + "MX30LF4G18AC", + }; + int i; + + if (!chip->onfi_version || + !(le16_to_cpu(chip->onfi_params.opt_cmd) + & ONFI_OPT_CMD_SET_GET_FEATURES)) + return; + + for (i = 0; i < ARRAY_SIZE(supported_otp_models); i++) { + if (!strcmp(chip->onfi_params.model, supported_otp_models[i])) { + struct mtd_info *mtd; + + mtd = nand_to_mtd(chip); + mtd->_get_user_prot_info = macronix_30lfxg18ac_get_otp_info; + mtd->_read_user_prot_reg = macronix_30lfxg18ac_read_otp; + mtd->_write_user_prot_reg = macronix_30lfxg18ac_write_otp; + mtd->_lock_user_prot_reg = macronix_30lfxg18ac_lock_otp; + return; + } + } +} + static int macronix_nand_init(struct nand_chip *chip) { if (nand_is_slc(chip)) chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + macronix_nand_setup_otp(chip); + return 0; } From 4126a386b33d0a011f93783ade4df9b8754666ca Mon Sep 17 00:00:00 2001 From: John Watts Date: Thu, 11 Apr 2024 15:05:48 +1000 Subject: [PATCH 19/31] ubi: Depend on MTD UBI required MTD to build correctly, add it as a Kconfig dependency. Link: https://lore.kernel.org/all/20240411-mtd-v1-1-fe300f6ab657@jookia.org Signed-off-by: John Watts Reviewed-by: Michael Trimarchi Reviewed-by: Heiko Schocher Signed-off-by: Dario Binacchi --- drivers/mtd/ubi/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index 5783d36c048..fd446d6efb3 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig @@ -9,6 +9,7 @@ config UBI_SILENCE_MSG config MTD_UBI bool "Enable UBI - Unsorted block images" + depends on MTD select RBTREE select MTD_PARTITIONS help From 30938f09548a9ba0a7281db7d31acd7d6c685761 Mon Sep 17 00:00:00 2001 From: Ravi Minnikanti Date: Sat, 27 Apr 2024 09:15:28 -0700 Subject: [PATCH 20/31] mtd: nand: pxa3xx: Incorrect bitflip return on page read Once a page is read with higher bitflips all subsequent reads are returning the same bitflip value even though they have none. max_bitflip variable is not being reset to 0 across page reads. This is causing problems like incorrectly marking erase blocks bad by UBI and causing read failures. Verified the change with both MTD reads and UBI. This change is inline with other NFC drivers. Sample error log where a block is marked bad incorrectly: ubi0: fixable bit-flip detected at PEB 125 ubi0: run torture test for PEB 125 ubi0: fixable bit-flip detected at PEB 125 ubi0 error: torture_peb: read problems on freshly erased PEB 125, must be bad ubi0 error: erase_worker: failed to erase PEB 125, error -5 ubi0: mark PEB 125 as bad Link: https://lore.kernel.org/all/ea0422cd-a8e6-3c36-f551-a0142893301b@marvell.com Signed-off-by: rminnikanti Reviewed-by: Chris Packham Signed-off-by: rminnikanti Acked-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/pxa3xx_nand.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c index 1d9a6d107b1..d2a4faad562 100644 --- a/drivers/mtd/nand/raw/pxa3xx_nand.c +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c @@ -800,6 +800,11 @@ static void prepare_start_command(struct pxa3xx_nand_info *info, int command) info->ecc_err_cnt = 0; info->ndcb3 = 0; info->need_wait = 0; + /* + * Reset max_bitflips to zero. Once command is complete, + * max_bitflips for this READ is returned in ecc.read_page() + */ + info->max_bitflips = 0; switch (command) { case NAND_CMD_READ0: From de5000a31dfdb71411639e35cd822922eba489b3 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 11 Jun 2024 22:04:11 +0100 Subject: [PATCH 21/31] cyclic: Rise default CYCLIC_MAX_CPU_TIME_US to 5000 The default value CYCLIC_MAX_CPU_TIME_US was 1000, which is a little bit too low for slower hardware and sandbox. On my MIPS Boston FPGA board with interaptiv CPU, wdt_cyclic can easily take 3200 us to run. On azure pipeline sandbox_clang, wdt_cyclic some times goes beyond 1300 us. Raise default value to 5000, which is the value already taken by octeon_nic32. This is still sufficent to maintain system responsiveness. Signed-off-by: Jiaxun Yang Signed-off-by: Stefan Roese --- common/Kconfig | 2 +- configs/octeon_nic23_defconfig | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/common/Kconfig b/common/Kconfig index 5e3070e9253..4bb9f08977a 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -628,7 +628,7 @@ if CYCLIC config CYCLIC_MAX_CPU_TIME_US int "Sets the max allowed time for a cyclic function in us" - default 1000 + default 5000 help The max allowed time for a cyclic function in us. If a functions takes longer than this duration this function will get unregistered diff --git a/configs/octeon_nic23_defconfig b/configs/octeon_nic23_defconfig index f7c35536a02..5a8db5a0876 100644 --- a/configs/octeon_nic23_defconfig +++ b/configs/octeon_nic23_defconfig @@ -25,7 +25,6 @@ CONFIG_SYS_PBSIZE=276 CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_SYS_DEVICE_NULLDEV is not set CONFIG_CYCLIC=y -CONFIG_CYCLIC_MAX_CPU_TIME_US=5000 CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y From 095627698a0ee6928feeac57ad88e84deac135be Mon Sep 17 00:00:00 2001 From: Maximilian Brune Date: Tue, 25 Jun 2024 16:39:54 +0200 Subject: [PATCH 22/31] Move SPCR and DBG2 into common code This moves the SPCR and DBG2 table generation into common code, so that they can be used by architectures other than x86. Signed-off-by: Maximilian Brune --- arch/x86/include/asm/acpi_table.h | 11 -- arch/x86/lib/acpi_table.c | 174 ----------------------- include/acpi/acpi_table.h | 34 ++--- lib/acpi/acpi_table.c | 225 +++++++++++++++++++++++++++++- 4 files changed, 241 insertions(+), 203 deletions(-) diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 57e41654ce3..e6175246173 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -45,17 +45,6 @@ int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base, */ int acpi_write_hpet(struct acpi_ctx *ctx); -/** - * acpi_write_dbg2_pci_uart() - Write out a DBG2 table - * - * @ctx: Current ACPI context - * @dev: Debug UART device to describe - * @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS) - * Return: 0 if OK, -ve on error - */ -int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev, - uint access_size); - /** * acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table * diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index a5683132b01..8a4fa6a6264 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -280,140 +280,6 @@ static int acpi_write_tpm2(struct acpi_ctx *ctx, } ACPI_WRITER(5tpm2, "TPM2", acpi_write_tpm2, 0); -int acpi_write_spcr(struct acpi_ctx *ctx, const struct acpi_writer *entry) -{ - struct serial_device_info serial_info = {0}; - ulong serial_address, serial_offset; - struct acpi_table_header *header; - struct acpi_spcr *spcr; - struct udevice *dev; - uint serial_config; - uint serial_width; - int access_size; - int space_id; - int ret = -ENODEV; - - spcr = ctx->current; - header = &spcr->header; - - memset(spcr, '\0', sizeof(struct acpi_spcr)); - - /* Fill out header fields */ - acpi_fill_header(header, "SPCR"); - header->length = sizeof(struct acpi_spcr); - header->revision = 2; - - /* Read the device once, here. It is reused below */ - dev = gd->cur_serial_dev; - if (dev) - ret = serial_getinfo(dev, &serial_info); - if (ret) - serial_info.type = SERIAL_CHIP_UNKNOWN; - - /* Encode chip type */ - switch (serial_info.type) { - case SERIAL_CHIP_16550_COMPATIBLE: - spcr->interface_type = ACPI_DBG2_16550_COMPATIBLE; - break; - case SERIAL_CHIP_UNKNOWN: - default: - spcr->interface_type = ACPI_DBG2_UNKNOWN; - break; - } - - /* Encode address space */ - switch (serial_info.addr_space) { - case SERIAL_ADDRESS_SPACE_MEMORY: - space_id = ACPI_ADDRESS_SPACE_MEMORY; - break; - case SERIAL_ADDRESS_SPACE_IO: - default: - space_id = ACPI_ADDRESS_SPACE_IO; - break; - } - - serial_width = serial_info.reg_width * 8; - serial_offset = serial_info.reg_offset << serial_info.reg_shift; - serial_address = serial_info.addr + serial_offset; - - /* Encode register access size */ - switch (serial_info.reg_shift) { - case 0: - access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - break; - case 1: - access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - break; - case 2: - access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - break; - case 3: - access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS; - break; - default: - access_size = ACPI_ACCESS_SIZE_UNDEFINED; - break; - } - - debug("UART type %u @ %lx\n", spcr->interface_type, serial_address); - - /* Fill GAS */ - spcr->serial_port.space_id = space_id; - spcr->serial_port.bit_width = serial_width; - spcr->serial_port.bit_offset = 0; - spcr->serial_port.access_size = access_size; - spcr->serial_port.addrl = lower_32_bits(serial_address); - spcr->serial_port.addrh = upper_32_bits(serial_address); - - /* Encode baud rate */ - switch (serial_info.baudrate) { - case 9600: - spcr->baud_rate = 3; - break; - case 19200: - spcr->baud_rate = 4; - break; - case 57600: - spcr->baud_rate = 6; - break; - case 115200: - spcr->baud_rate = 7; - break; - default: - spcr->baud_rate = 0; - break; - } - - serial_config = SERIAL_DEFAULT_CONFIG; - if (dev) - ret = serial_getconfig(dev, &serial_config); - - spcr->parity = SERIAL_GET_PARITY(serial_config); - spcr->stop_bits = SERIAL_GET_STOP(serial_config); - - /* No PCI devices for now */ - spcr->pci_device_id = 0xffff; - spcr->pci_vendor_id = 0xffff; - - /* - * SPCR has no clue if the UART base clock speed is different - * to the default one. However, the SPCR 1.04 defines baud rate - * 0 as a preconfigured state of UART and OS is supposed not - * to touch the configuration of the serial device. - */ - if (serial_info.clock != SERIAL_DEFAULT_CLOCK) - spcr->baud_rate = 0; - - /* Fix checksum */ - header->checksum = table_compute_checksum((void *)spcr, header->length); - - acpi_add_table(ctx, spcr); - acpi_inc(ctx, spcr->header.length); - - return 0; -} -ACPI_WRITER(5spcr, "SPCR", acpi_write_spcr, 0); - int acpi_write_gnvs(struct acpi_ctx *ctx, const struct acpi_writer *entry) { ulong addr; @@ -517,46 +383,6 @@ int acpi_write_hpet(struct acpi_ctx *ctx) return 0; } -int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev, - uint access_size) -{ - struct acpi_dbg2_header *dbg2 = ctx->current; - char path[ACPI_PATH_MAX]; - struct acpi_gen_regaddr address; - phys_addr_t addr; - int ret; - - if (!device_active(dev)) { - log_info("Device not enabled\n"); - return -EACCES; - } - /* - * PCI devices don't remember their resource allocation information in - * U-Boot at present. We assume that MMIO is used for the UART and that - * the address space is 32 bytes: ns16550 uses 8 registers of up to - * 32-bits each. This is only for debugging so it is not a big deal. - */ - addr = dm_pci_read_bar32(dev, 0); - log_debug("UART addr %lx\n", (ulong)addr); - - memset(&address, '\0', sizeof(address)); - address.space_id = ACPI_ADDRESS_SPACE_MEMORY; - address.addrl = (uint32_t)addr; - address.addrh = (uint32_t)((addr >> 32) & 0xffffffff); - address.access_size = access_size; - - ret = acpi_device_path(dev, path, sizeof(path)); - if (ret) - return log_msg_ret("path", ret); - acpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT, - ACPI_DBG2_16550_COMPATIBLE, &address, 0x1000, path); - - acpi_inc_align(ctx, dbg2->header.length); - acpi_add_table(ctx, dbg2); - - return 0; -} - void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs, void *dsdt) { diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index 15fd61a51d7..eb9d24697ca 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -846,23 +846,6 @@ int acpi_get_table_revision(enum acpi_tables table); */ int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags); -/** - * acpi_create_dbg2() - Create a DBG2 table - * - * This table describes how to access the debug UART - * - * @dbg2: Place to put information - * @port_type: Serial port type (see ACPI_DBG2_...) - * @port_subtype: Serial port sub-type (see ACPI_DBG2_...) - * @address: ACPI address of port - * @address_size: Size of address space - * @device_path: Path of device (created using acpi_device_path()) - */ -void acpi_create_dbg2(struct acpi_dbg2_header *dbg2, - int port_type, int port_subtype, - struct acpi_gen_regaddr *address, uint32_t address_size, - const char *device_path); - /** * acpi_align() - Align the ACPI output pointer to a 16-byte boundary * @@ -943,6 +926,23 @@ void acpi_fill_header(struct acpi_table_header *header, char *signature); */ int acpi_fill_csrt(struct acpi_ctx *ctx); +/** + * acpi_write_dbg2_pci_uart() - Write out a DBG2 table + * + * @ctx: Current ACPI context + * @dev: Debug UART device to describe + * @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS) + * Return: 0 if OK, -ve on error + */ +int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev, + uint access_size); + +void acpi_pl011_write_dbg2_uart(struct acpi_ctx *ctx, + uint64_t base, const char *name); + +void acpi_16550_mmio32_write_dbg2_uart(struct acpi_ctx *ctx, + uint64_t base, const char *name); + /** * acpi_get_rsdp_addr() - get ACPI RSDP table address * diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index c16ead6a6ec..b406b5cb5da 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -10,8 +10,10 @@ #include #include #include +#include #include #include +#include #include #include @@ -199,7 +201,7 @@ int acpi_add_table(struct acpi_ctx *ctx, void *table) return 0; } -void acpi_create_dbg2(struct acpi_dbg2_header *dbg2, +static void acpi_create_dbg2(struct acpi_dbg2_header *dbg2, int port_type, int port_subtype, struct acpi_gen_regaddr *address, u32 address_size, const char *device_path) @@ -262,3 +264,224 @@ void acpi_create_dbg2(struct acpi_dbg2_header *dbg2, header->length = current - (uintptr_t)dbg2; header->checksum = table_compute_checksum(dbg2, header->length); } + +/** + * acpi_create_dbg2() - Create a DBG2 table + * + * This table describes how to access the debug UART + * + * @dbg2: Place to put information + * @port_type: Serial port type (see ACPI_DBG2_...) + * @port_subtype: Serial port sub-type (see ACPI_DBG2_...) + * @address: ACPI address of port + * @address_size: Size of address space + * @device_path: Path of device (created using acpi_device_path()) + */ +static void acpi_write_dbg2_uart(struct acpi_ctx *ctx, + int space_id, int subtype, uint64_t base, uint32_t size, + int access_size, const char *name) +{ + struct acpi_dbg2_header *dbg2 = (struct acpi_dbg2_header *)ctx->current; + struct acpi_gen_regaddr address; + + memset(&address, 0, sizeof(address)); + + address.space_id = space_id; + address.addrl = (uint32_t)base; + address.addrh = (uint32_t)((base >> 32) & 0xffffffff); + address.access_size = access_size; + + acpi_create_dbg2(dbg2, + ACPI_DBG2_SERIAL_PORT, + subtype, + &address, size, + name); + + if (dbg2->header.length) { + acpi_inc_align(ctx, dbg2->header.length); + acpi_add_table(ctx, dbg2); + } +} + +int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev, + uint access_size) +{ + char path[ACPI_PATH_MAX]; + phys_addr_t addr; + int ret; + + if (!device_active(dev)) { + log_info("Device not enabled\n"); + return -EACCES; + } + /* + * PCI devices don't remember their resource allocation information in + * U-Boot at present. We assume that MMIO is used for the UART and that + * the address space is 32 bytes: ns16550 uses 8 registers of up to + * 32-bits each. This is only for debugging so it is not a big deal. + */ + addr = dm_pci_read_bar32(dev, 0); + log_debug("UART addr %lx\n", (ulong)addr); + + ret = acpi_device_path(dev, path, sizeof(path)); + if (ret) + return log_msg_ret("path", ret); + + acpi_write_dbg2_uart(ctx, ACPI_ADDRESS_SPACE_MEMORY, ACPI_DBG2_16550_COMPATIBLE, + addr, 0x1000, access_size, path); + + return 0; +} + +void acpi_pl011_write_dbg2_uart(struct acpi_ctx *ctx, + uint64_t base, const char *name) +{ + acpi_write_dbg2_uart(ctx, ACPI_ADDRESS_SPACE_MEMORY, + ACPI_DBG2_ARM_PL011, base, 0x1000, + ACPI_ACCESS_SIZE_DWORD_ACCESS, name); +} + +void acpi_16550_mmio32_write_dbg2_uart(struct acpi_ctx *ctx, + uint64_t base, const char *name) +{ + acpi_write_dbg2_uart(ctx, ACPI_ADDRESS_SPACE_MEMORY, + ACPI_DBG2_16550_COMPATIBLE, base, 0x100, + ACPI_ACCESS_SIZE_DWORD_ACCESS, name); +} + +int acpi_write_spcr(struct acpi_ctx *ctx, const struct acpi_writer *entry) +{ + struct serial_device_info serial_info = {0}; + ulong serial_address, serial_offset; + struct acpi_table_header *header; + struct acpi_spcr *spcr; + struct udevice *dev; + uint serial_config; + uint serial_width; + int access_size; + int space_id; + int ret = -ENODEV; + + spcr = ctx->current; + header = &spcr->header; + + memset(spcr, '\0', sizeof(struct acpi_spcr)); + + /* Fill out header fields */ + acpi_fill_header(header, "SPCR"); + header->length = sizeof(struct acpi_spcr); + header->revision = 2; + + /* Read the device once, here. It is reused below */ + dev = gd->cur_serial_dev; + if (dev) + ret = serial_getinfo(dev, &serial_info); + if (ret) + serial_info.type = SERIAL_CHIP_UNKNOWN; + + /* Encode chip type */ + switch (serial_info.type) { + case SERIAL_CHIP_16550_COMPATIBLE: + spcr->interface_type = ACPI_DBG2_16550_COMPATIBLE; + break; + case SERIAL_CHIP_PL01X: + spcr->interface_type = ACPI_DBG2_ARM_PL011; + break; + case SERIAL_CHIP_UNKNOWN: + default: + spcr->interface_type = ACPI_DBG2_UNKNOWN; + break; + } + + /* Encode address space */ + switch (serial_info.addr_space) { + case SERIAL_ADDRESS_SPACE_MEMORY: + space_id = ACPI_ADDRESS_SPACE_MEMORY; + break; + case SERIAL_ADDRESS_SPACE_IO: + default: + space_id = ACPI_ADDRESS_SPACE_IO; + break; + } + + serial_width = serial_info.reg_width * 8; + serial_offset = serial_info.reg_offset << serial_info.reg_shift; + serial_address = serial_info.addr + serial_offset; + + /* Encode register access size */ + switch (serial_info.reg_shift) { + case 0: + access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + break; + case 1: + access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + break; + case 2: + access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + break; + case 3: + access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS; + break; + default: + access_size = ACPI_ACCESS_SIZE_UNDEFINED; + break; + } + + debug("UART type %u @ %lx\n", spcr->interface_type, serial_address); + + /* Fill GAS */ + spcr->serial_port.space_id = space_id; + spcr->serial_port.bit_width = serial_width; + spcr->serial_port.bit_offset = 0; + spcr->serial_port.access_size = access_size; + spcr->serial_port.addrl = lower_32_bits(serial_address); + spcr->serial_port.addrh = upper_32_bits(serial_address); + + /* Encode baud rate */ + switch (serial_info.baudrate) { + case 9600: + spcr->baud_rate = 3; + break; + case 19200: + spcr->baud_rate = 4; + break; + case 57600: + spcr->baud_rate = 6; + break; + case 115200: + spcr->baud_rate = 7; + break; + default: + spcr->baud_rate = 0; + break; + } + + serial_config = SERIAL_DEFAULT_CONFIG; + if (dev) + ret = serial_getconfig(dev, &serial_config); + + spcr->parity = SERIAL_GET_PARITY(serial_config); + spcr->stop_bits = SERIAL_GET_STOP(serial_config); + + /* No PCI devices for now */ + spcr->pci_device_id = 0xffff; + spcr->pci_vendor_id = 0xffff; + + /* + * SPCR has no clue if the UART base clock speed is different + * to the default one. However, the SPCR 1.04 defines baud rate + * 0 as a preconfigured state of UART and OS is supposed not + * to touch the configuration of the serial device. + */ + if (serial_info.clock != SERIAL_DEFAULT_CLOCK) + spcr->baud_rate = 0; + + /* Fix checksum */ + header->checksum = table_compute_checksum((void *)spcr, header->length); + + acpi_add_table(ctx, spcr); + acpi_inc(ctx, spcr->header.length); + + return 0; +} +ACPI_WRITER(5spcr, "SPCR", acpi_write_spcr, 0); From 06e2161b4abf631aa73c3a65c1eef2f5e811761a Mon Sep 17 00:00:00 2001 From: Maximilian Brune Date: Tue, 25 Jun 2024 17:57:51 +0200 Subject: [PATCH 23/31] Write FADT in common code Let the cpu code fill out the FADT body. Signed-off-by: Patrick Rudolph --- arch/x86/cpu/apollolake/acpi.c | 20 +++----------- arch/x86/cpu/baytrail/acpi.c | 17 +----------- arch/x86/cpu/quark/acpi.c | 18 +------------ arch/x86/cpu/tangier/acpi.c | 25 +---------------- arch/x86/include/asm/acpi_table.h | 12 --------- arch/x86/lib/acpi_table.c | 24 ----------------- include/acpi/acpi_table.h | 9 +++++++ lib/acpi/acpi_table.c | 45 +++++++++++++++++++++++++++++++ 8 files changed, 60 insertions(+), 110 deletions(-) diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c index c610a7f4477..3aed38e2629 100644 --- a/arch/x86/cpu/apollolake/acpi.c +++ b/arch/x86/cpu/apollolake/acpi.c @@ -129,8 +129,10 @@ int arch_madt_sci_irq_polarity(int sci) return MP_IRQ_POLARITY_LOW; } -void fill_fadt(struct acpi_fadt *fadt) +void acpi_fill_fadt(struct acpi_fadt *fadt) { + intel_acpi_fill_fadt(fadt); + fadt->pm_tmr_blk = IOMAP_ACPI_BASE + PM1_TMR; fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; @@ -146,22 +148,6 @@ void fill_fadt(struct acpi_fadt *fadt) fadt->x_pm_tmr_blk.addrl = IOMAP_ACPI_BASE + PM1_TMR; } -static int apl_write_fadt(struct acpi_ctx *ctx, const struct acpi_writer *entry) -{ - struct acpi_table_header *header; - struct acpi_fadt *fadt; - - fadt = ctx->current; - acpi_fadt_common(fadt, ctx->facs, ctx->dsdt); - intel_acpi_fill_fadt(fadt); - fill_fadt(fadt); - header = &fadt->header; - header->checksum = table_compute_checksum(fadt, header->length); - - return acpi_add_fadt(ctx, fadt); -} -ACPI_WRITER(5fadt, "FADT", apl_write_fadt, 0); - int apl_acpi_fill_dmar(struct acpi_ctx *ctx) { struct udevice *dev, *sa_dev; diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index ccc4851b188..4cdc8e43147 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -16,20 +16,13 @@ #include #include -static int baytrail_write_fadt(struct acpi_ctx *ctx, - const struct acpi_writer *entry) +void acpi_fill_fadt(struct acpi_fadt *fadt) { struct acpi_table_header *header; - struct acpi_fadt *fadt; - fadt = ctx->current; header = &fadt->header; u16 pmbase = ACPI_BASE_ADDRESS; - memset(fadt, '\0', sizeof(struct acpi_fadt)); - - acpi_fill_header(header, "FACP"); - header->length = sizeof(struct acpi_fadt); header->revision = 4; fadt->preferred_pm_profile = ACPI_PM_MOBILE; @@ -78,9 +71,6 @@ static int baytrail_write_fadt(struct acpi_ctx *ctx, fadt->reset_reg.addrh = 0; fadt->reset_value = SYS_RST | RST_CPU | FULL_RST; - fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs); - fadt->x_dsdt = map_to_sysmem(ctx->dsdt); - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; @@ -136,12 +126,7 @@ static int baytrail_write_fadt(struct acpi_ctx *ctx, fadt->x_gpe1_blk.access_size = 0; fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = table_compute_checksum(fadt, header->length); - - return acpi_add_fadt(ctx, fadt); } -ACPI_WRITER(5fadt, "FADT", baytrail_write_fadt, 0); int acpi_create_gnvs(struct acpi_global_nvs *gnvs) { diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c index 0e18ceab68d..fd5b106684b 100644 --- a/arch/x86/cpu/quark/acpi.c +++ b/arch/x86/cpu/quark/acpi.c @@ -11,20 +11,12 @@ #include #include -static int quark_write_fadt(struct acpi_ctx *ctx, - const struct acpi_writer *entry) +void acpi_fill_fadt(struct acpi_fadt *fadt) { u16 pmbase = ACPI_PM1_BASE_ADDRESS; struct acpi_table_header *header; - struct acpi_fadt *fadt; - fadt = ctx->current; header = &fadt->header; - - memset(fadt, '\0', sizeof(struct acpi_fadt)); - - acpi_fill_header(header, "FACP"); - header->length = sizeof(struct acpi_fadt); header->revision = 4; fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED; @@ -73,9 +65,6 @@ static int quark_write_fadt(struct acpi_ctx *ctx, fadt->reset_reg.addrh = 0; fadt->reset_value = SYS_RST | RST_CPU | FULL_RST; - fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs); - fadt->x_dsdt = map_to_sysmem(ctx->dsdt); - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; @@ -131,12 +120,7 @@ static int quark_write_fadt(struct acpi_ctx *ctx, fadt->x_gpe1_blk.access_size = 0; fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = table_compute_checksum(fadt, header->length); - - return acpi_add_fadt(ctx, fadt); } -ACPI_WRITER(5fadt, "FADT", quark_write_fadt, 0); int acpi_create_gnvs(struct acpi_global_nvs *gnvs) { diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index 1d37cc9e2b0..e38a5ddd46d 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -17,21 +17,8 @@ #include #include -static int tangier_write_fadt(struct acpi_ctx *ctx, - const struct acpi_writer *entry) +void acpi_fill_fadt(struct acpi_fadt *fadt) { - struct acpi_table_header *header; - struct acpi_fadt *fadt; - - fadt = ctx->current; - header = &fadt->header; - - memset(fadt, '\0', sizeof(struct acpi_fadt)); - - acpi_fill_header(header, "FACP"); - header->length = sizeof(struct acpi_fadt); - header->revision = 6; - fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED; fadt->iapc_boot_arch = ACPI_FADT_VGA_NOT_PRESENT | @@ -41,17 +28,7 @@ static int tangier_write_fadt(struct acpi_ctx *ctx, ACPI_FADT_POWER_BUTTON | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE | ACPI_FADT_HEADLESS | ACPI_FADT_HW_REDUCED_ACPI; - - fadt->minor_revision = 2; - - fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs); - fadt->x_dsdt = map_to_sysmem(ctx->dsdt); - - header->checksum = table_compute_checksum(fadt, header->length); - - return acpi_add_fadt(ctx, fadt); } -ACPI_WRITER(5fadt, "FADT", tangier_write_fadt, 0); u32 acpi_fill_madt(u32 current) { diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index e6175246173..3988898f66e 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -168,18 +168,6 @@ int acpi_create_dmar_ds_ioapic(struct acpi_ctx *ctx, uint enumeration_id, int acpi_create_dmar_ds_msi_hpet(struct acpi_ctx *ctx, uint enumeration_id, pci_dev_t bdf); -/** - * acpi_fadt_common() - Handle common parts of filling out an FADT - * - * This sets up the Fixed ACPI Description Table - * - * @fadt: Pointer to place to put FADT - * @facs: Pointer to the FACS - * @dsdt: Pointer to the DSDT - */ -void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs, - void *dsdt); - /** * intel_acpi_fill_fadt() - Set up the contents of the FADT * diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 8a4fa6a6264..9588b841154 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -383,30 +383,6 @@ int acpi_write_hpet(struct acpi_ctx *ctx) return 0; } -void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs, - void *dsdt) -{ - struct acpi_table_header *header = &fadt->header; - - memset((void *)fadt, '\0', sizeof(struct acpi_fadt)); - - acpi_fill_header(header, "FACP"); - header->length = sizeof(struct acpi_fadt); - header->revision = 4; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, OEM_TABLE_ID, 8); - memcpy(header->creator_id, ASLC_ID, 4); - header->creator_revision = 1; - - fadt->x_firmware_ctrl = map_to_sysmem(facs); - fadt->x_dsdt = map_to_sysmem(dsdt); - - fadt->preferred_pm_profile = ACPI_PM_MOBILE; - - /* Use ACPI 3.0 revision */ - fadt->header.revision = 4; -} - void acpi_create_dmar_drhd(struct acpi_ctx *ctx, uint flags, uint segment, u64 bar) { diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index eb9d24697ca..420bfb6a749 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -926,6 +926,15 @@ void acpi_fill_header(struct acpi_table_header *header, char *signature); */ int acpi_fill_csrt(struct acpi_ctx *ctx); +/** + * acpi_fill_fadt() - Fill out the body of the FADT + * + * Should be implemented in SoC specific code. + * + * @fadt: Pointer to FADT to update + */ +void acpi_fill_fadt(struct acpi_fadt *fadt); + /** * acpi_write_dbg2_pci_uart() - Write out a DBG2 table * diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index b406b5cb5da..6e990abf63b 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -201,6 +201,51 @@ int acpi_add_table(struct acpi_ctx *ctx, void *table) return 0; } +__weak void acpi_fill_fadt(struct acpi_fadt *fadt) +{ +} + +int acpi_write_fadt(struct acpi_ctx *ctx, const struct acpi_writer *entry) +{ + struct acpi_table_header *header; + struct acpi_fadt *fadt; + + fadt = ctx->current; + header = &fadt->header; + + memset((void *)fadt, '\0', sizeof(struct acpi_fadt)); + + acpi_fill_header(header, "FACP"); + header->length = sizeof(struct acpi_fadt); + header->revision = ACPI_FADT_REV_ACPI_6_0; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->creator_id, ASLC_ID, 4); + header->creator_revision = 1; + + fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs); + fadt->x_dsdt = map_to_sysmem(ctx->dsdt); + + if (fadt->x_firmware_ctrl < 0x100000000UL) + fadt->firmware_ctrl = fadt->x_firmware_ctrl; + else + fadt->firmware_ctrl = 0; + + if (fadt->x_dsdt < 0x100000000UL) + fadt->dsdt = fadt->x_dsdt; + else + fadt->dsdt = 0; + + fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED; + + acpi_fill_fadt(fadt); + + header->checksum = table_compute_checksum(fadt, header->length); + + return acpi_add_fadt(ctx, fadt); +} +ACPI_WRITER(5fadt, "FADT", acpi_write_fadt, 0); + static void acpi_create_dbg2(struct acpi_dbg2_header *dbg2, int port_type, int port_subtype, struct acpi_gen_regaddr *address, u32 address_size, From aa1a702f51b99cbee7af15fdb8d66c0da3ede807 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 1 Jul 2024 16:13:00 +0200 Subject: [PATCH 24/31] acpi: Move MADT to common code Write MADT in common code and let the SoC fill out the body by calling acpi_fill_madt() which must be implemented at SoC level. Signed-off-by: Patrick Rudolph --- arch/x86/cpu/intel_common/acpi.c | 5 +++- arch/x86/cpu/tangier/acpi.c | 5 +++- arch/x86/include/asm/acpi_table.h | 1 - arch/x86/lib/acpi_table.c | 38 ++++--------------------------- include/acpi/acpi_table.h | 11 +++++++++ lib/acpi/acpi_table.c | 30 ++++++++++++++++++++++++ 6 files changed, 53 insertions(+), 37 deletions(-) diff --git a/arch/x86/cpu/intel_common/acpi.c b/arch/x86/cpu/intel_common/acpi.c index d94ec208f65..dae8054a048 100644 --- a/arch/x86/cpu/intel_common/acpi.c +++ b/arch/x86/cpu/intel_common/acpi.c @@ -101,8 +101,11 @@ static unsigned long acpi_madt_irq_overrides(unsigned long current) return current; } -u32 acpi_fill_madt(u32 current) +u32 acpi_fill_madt(struct acpi_madt *madt, void *current) { + madt->lapic_addr = LAPIC_DEFAULT_BASE; + madt->flags = ACPI_MADT_PCAT_COMPAT; + /* Local APICs */ current += acpi_create_madt_lapics(current); diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index e38a5ddd46d..f165dd16a1c 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -30,8 +30,11 @@ void acpi_fill_fadt(struct acpi_fadt *fadt) ACPI_FADT_HW_REDUCED_ACPI; } -u32 acpi_fill_madt(u32 current) +u32 acpi_fill_madt(struct acpi_madt *madt, void *current) { + madt->lapic_addr = LAPIC_DEFAULT_BASE; + madt->flags = ACPI_MADT_PCAT_COMPAT; + current += acpi_create_madt_lapics(current); current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current, diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 3988898f66e..4c1a639e440 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -31,7 +31,6 @@ int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride, u8 bus, u8 source, u32 gsirq, u16 flags); int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu, u16 flags, u8 lint); -u32 acpi_fill_madt(u32 current); int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base, u16 seg_nr, u8 start, u8 end); diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 9588b841154..c66de8ae3e6 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -116,8 +116,11 @@ static int acpi_create_madt_irq_overrides(u32 current) return length; } -__weak u32 acpi_fill_madt(u32 current) +__weak u32 acpi_fill_madt(struct acpi_madt *madt, void *current) { + madt->lapic_addr = LAPIC_DEFAULT_BASE; + madt->flags = ACPI_MADT_PCAT_COMPAT; + current += acpi_create_madt_lapics(current); current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current, @@ -128,39 +131,6 @@ __weak u32 acpi_fill_madt(u32 current) return current; } -int acpi_write_madt(struct acpi_ctx *ctx, const struct acpi_writer *entry) -{ - struct acpi_table_header *header; - struct acpi_madt *madt; - u32 current; - - madt = ctx->current; - - memset(madt, '\0', sizeof(struct acpi_madt)); - header = &madt->header; - - /* Fill out header fields */ - acpi_fill_header(header, "APIC"); - header->length = sizeof(struct acpi_madt); - header->revision = ACPI_MADT_REV_ACPI_3_0; - - madt->lapic_addr = LAPIC_DEFAULT_BASE; - madt->flags = ACPI_MADT_PCAT_COMPAT; - - current = (u32)madt + sizeof(struct acpi_madt); - current = acpi_fill_madt(current); - - /* (Re)calculate length and checksum */ - header->length = current - (u32)madt; - - header->checksum = table_compute_checksum((void *)madt, header->length); - acpi_add_table(ctx, madt); - acpi_inc(ctx, madt->header.length); - - return 0; -} -ACPI_WRITER(5x86, NULL, acpi_write_madt, 0); - /** * acpi_create_tcpa() - Create a TCPA table * diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index 420bfb6a749..f04c830991a 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -935,6 +935,17 @@ int acpi_fill_csrt(struct acpi_ctx *ctx); */ void acpi_fill_fadt(struct acpi_fadt *fadt); +/** + * acpi_fill_madt() - Fill out the body of the MADT + * + * Must be implemented in SoC specific code. + * + * @madt: The MADT to update + * @current: Pointer to the MADT body + * @return Pointer to the end of tables, where the next tables can be written + */ +void *acpi_fill_madt(struct acpi_madt *madt, void *current); + /** * acpi_write_dbg2_pci_uart() - Write out a DBG2 table * diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index 6e990abf63b..f3e6b2d33a4 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -246,6 +246,36 @@ int acpi_write_fadt(struct acpi_ctx *ctx, const struct acpi_writer *entry) } ACPI_WRITER(5fadt, "FADT", acpi_write_fadt, 0); +int acpi_write_madt(struct acpi_ctx *ctx, const struct acpi_writer *entry) +{ + struct acpi_table_header *header; + struct acpi_madt *madt; + void *current; + + madt = ctx->current; + + memset(madt, '\0', sizeof(struct acpi_madt)); + header = &madt->header; + + /* Fill out header fields */ + acpi_fill_header(header, "APIC"); + header->length = sizeof(struct acpi_madt); + header->revision = ACPI_MADT_REV_ACPI_3_0; + + current = (void *)madt + sizeof(struct acpi_madt); + current = acpi_fill_madt(madt, current); + + /* (Re)calculate length and checksum */ + header->length = (u64)current - (u64)madt; + + header->checksum = table_compute_checksum((void *)madt, header->length); + acpi_add_table(ctx, madt); + acpi_inc(ctx, madt->header.length); + + return 0; +} +ACPI_WRITER(5madt, NULL, acpi_write_madt, 0); + static void acpi_create_dbg2(struct acpi_dbg2_header *dbg2, int port_type, int port_subtype, struct acpi_gen_regaddr *address, u32 address_size, From 9eb5fe1c8a6a51e3734b01bc05d94144fed7faac Mon Sep 17 00:00:00 2001 From: Maximilian Brune Date: Tue, 25 Jun 2024 16:36:02 +0200 Subject: [PATCH 25/31] Add .getinfo() for PL01 It is needed for the ACPI table generation. Signed-off-by: Maximilian Brune --- drivers/serial/serial_pl01x.c | 28 ++++++++++++++++++++++++++++ include/serial.h | 1 + 2 files changed, 29 insertions(+) diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index f04c21e0826..bfbaf9eab46 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -273,6 +274,32 @@ __weak struct serial_device *default_serial_console(void) return &pl01x_serial_drv; } #else + +static int pl01x_serial_getinfo(struct udevice *dev, + struct serial_device_info *info) +{ + struct pl01x_serial_plat *plat = dev_get_plat(dev); + + /* save code size */ + if (!spl_in_proper()) + return -ENOSYS; + + info->type = SERIAL_CHIP_PL01X; + info->addr_space = SERIAL_ADDRESS_SPACE_MEMORY; + info->addr = plat->base; + info->size = 0x1000; + info->reg_width = 4; + info->reg_shift = 2; + info->reg_offset = 0; +#if defined(CONFIG_PL011_SERIAL) + info->clock = CFG_PL011_CLOCK; +#endif + info->clock = plat->clock; + info->baudrate = CONFIG_BAUDRATE; //TODO get from somewhere + + return 0; +} + int pl01x_serial_setbrg(struct udevice *dev, int baudrate) { struct pl01x_serial_plat *plat = dev_get_plat(dev); @@ -342,6 +369,7 @@ static const struct dm_serial_ops pl01x_serial_ops = { .pending = pl01x_serial_pending, .getc = pl01x_serial_getc, .setbrg = pl01x_serial_setbrg, + .getinfo = pl01x_serial_getinfo, }; #if CONFIG_IS_ENABLED(OF_REAL) diff --git a/include/serial.h b/include/serial.h index d129dc3253c..d7a9a8cfb8b 100644 --- a/include/serial.h +++ b/include/serial.h @@ -124,6 +124,7 @@ enum serial_stop { enum serial_chip_type { SERIAL_CHIP_UNKNOWN = -1, SERIAL_CHIP_16550_COMPATIBLE, + SERIAL_CHIP_PL01X, }; enum adr_space_type { From 8e5200dc46b0940423c4ab3ff842a410a8a82971 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 1 Jul 2024 15:56:12 +0200 Subject: [PATCH 26/31] mach-bcm283x: Write ACPI tables when enabled Signed-off-by: Patrick Rudolph --- arch/arm/include/asm/acpi_table.h | 18 +++ arch/arm/lib/Makefile | 1 + arch/arm/lib/acpi_table.c | 45 ++++++++ arch/arm/mach-bcm283x/Makefile | 1 + arch/arm/mach-bcm283x/acpi.c | 185 ++++++++++++++++++++++++++++++ arch/arm/mach-bcm283x/init.c | 25 ++++ 6 files changed, 275 insertions(+) create mode 100644 arch/arm/lib/acpi_table.c create mode 100644 arch/arm/mach-bcm283x/acpi.c diff --git a/arch/arm/include/asm/acpi_table.h b/arch/arm/include/asm/acpi_table.h index e69de29bb2d..7d48557b96d 100644 --- a/arch/arm/include/asm/acpi_table.h +++ b/arch/arm/include/asm/acpi_table.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __ASM_ACPI_TABLE_H__ +#define __ASM_ACPI_TABLE_H__ + +#ifndef __ACPI__ + +void acpi_write_madt_gicc(struct acpi_madr_gicc *gicc, uint cpu_num, + uint perf_gsiv, ulong phys_base, ulong gicv, + ulong gich, uint vgic_maint_irq, ulong mpidr, + uint efficiency); + +void acpi_write_madt_gicd(struct acpi_madr_gicd *gicd, uint gic_id, + ulong phys_base, uint gic_version); + +#endif /* !__ACPI__ */ + +#endif /* __ASM_ACPI_TABLE_H__ */ diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 67275fba616..a7efed6771d 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -86,6 +86,7 @@ obj-y += psci-dt.o obj-$(CONFIG_DEBUG_LL) += debug.o obj-$(CONFIG_BLOBLIST) += xferlist.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o # For EABI conformant tool chains, provide eabi_compat() ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) diff --git a/arch/arm/lib/acpi_table.c b/arch/arm/lib/acpi_table.c new file mode 100644 index 00000000000..ff2d611ba3f --- /dev/null +++ b/arch/arm/lib/acpi_table.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Based on acpi.c from coreboot + * + * Copyright (C) 2024 9elements GmbH + */ + +#define LOG_CATEGORY LOGC_ACPI + +#include +#include +#include +#include +#include + +void acpi_write_madt_gicc(struct acpi_madr_gicc *gicc, uint cpu_num, + uint perf_gsiv, ulong phys_base, ulong gicv, + ulong gich, uint vgic_maint_irq, ulong mpidr, + uint efficiency) +{ + memset(gicc, '\0', sizeof(struct acpi_madr_gicc)); + gicc->type = ACPI_APIC_GICC; + gicc->length = sizeof(struct acpi_madr_gicc); + gicc->cpu_if_num = cpu_num; + gicc->processor_id = cpu_num; + gicc->flags = ACPI_MADRF_ENABLED; + gicc->perf_gsiv = perf_gsiv; + gicc->phys_base = phys_base; + gicc->gicv = gicv; + gicc->gich = gich; + gicc->vgic_maint_irq = vgic_maint_irq; + gicc->mpidr = mpidr; + gicc->efficiency = efficiency; +} + +void acpi_write_madt_gicd(struct acpi_madr_gicd *gicd, uint gic_id, + ulong phys_base, uint gic_version) +{ + memset(gicd, '\0', sizeof(struct acpi_madr_gicd)); + gicd->type = ACPI_APIC_GICD; + gicd->length = sizeof(struct acpi_madr_gicd); + gicd->gic_id = gic_id; + gicd->phys_base = phys_base; + gicd->gic_version = gic_version; +} diff --git a/arch/arm/mach-bcm283x/Makefile b/arch/arm/mach-bcm283x/Makefile index 7cd068832f3..2e64740ea27 100644 --- a/arch/arm/mach-bcm283x/Makefile +++ b/arch/arm/mach-bcm283x/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_BCM2835) += lowlevel_init.o obj-y += init.o reset.o mbox.o msg.o phys2bus.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o diff --git a/arch/arm/mach-bcm283x/acpi.c b/arch/arm/mach-bcm283x/acpi.c new file mode 100644 index 00000000000..7d95a361ff1 --- /dev/null +++ b/arch/arm/mach-bcm283x/acpi.c @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2024 9elements GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +#include +#include +#include +#include +#include + +void acpi_fill_fadt(struct acpi_fadt *fadt) +{ + fadt->flags = ACPI_FADT_HW_REDUCED_ACPI | ACPI_FADT_LOW_PWR_IDLE_S0; + + if (CONFIG_IS_ENABLED(SEC_FIRMWARE_ARMV8_PSCI) && + sec_firmware_support_psci_version() != PSCI_INVALID_VER) + fadt->arm_boot_arch = ACPI_ARM_PSCI_COMPLIANT; +} + +void *acpi_fill_madt(struct acpi_madt *madt, void *current) +{ + struct acpi_madr_gicc *gicc; + struct acpi_madr_gicd *gicd; + + madt->lapic_addr = 0; + madt->flags = 0; + + if (!CONFIG_IS_ENABLED(BCM2711_64B)) { + return current; + } + + gicc = current; + acpi_write_madt_gicc(gicc++, 0, 0x30, 0xff842000, 0xff846000, 0xff844000, 0x19, 0, 1); + acpi_write_madt_gicc(gicc++, 1, 0x31, 0xff842000, 0xff846000, 0xff844000, 0x19, 1, 1); + acpi_write_madt_gicc(gicc++, 2, 0x32, 0xff842000, 0xff846000, 0xff844000, 0x19, 2, 1); + acpi_write_madt_gicc(gicc++, 3, 0x33, 0xff842000, 0xff846000, 0xff844000, 0x19, 3, 1); + + gicd = (struct acpi_madr_gicd *)gicc; + acpi_write_madt_gicd(gicd++, 0, 0xff841000, 2); + return gicd; +} + +static u32 *add_proc(struct acpi_ctx *ctx, int flags, int parent, int proc_id, + int num_resources) +{ + struct acpi_pptt_proc *proc = ctx->current; + u32 *resource_list; + + proc->hdr.type = ACPI_PPTT_TYPE_PROC; + proc->flags = flags; + proc->parent = parent; + proc->proc_id = proc_id; + proc->num_resources = num_resources; + proc->hdr.length = sizeof(struct acpi_pptt_proc) + + sizeof(u32) * num_resources; + resource_list = ctx->current + sizeof(struct acpi_pptt_proc); + acpi_inc(ctx, proc->hdr.length); + + return resource_list; +} + +static int add_cache(struct acpi_ctx *ctx, int flags, int size, int sets, + int assoc, int attributes, int line_size) +{ + struct acpi_pptt_cache *cache = ctx->current; + int ofs; + + ofs = ctx->current - ctx->tab_start; + cache->hdr.type = ACPI_PPTT_TYPE_CACHE; + cache->hdr.length = sizeof(struct acpi_pptt_cache); + cache->flags = flags; + cache->next_cache_level = 0; + cache->size = size; + cache->sets = sets; + cache->assoc = assoc; + cache->attributes = attributes; + cache->line_size = line_size; + acpi_inc(ctx, cache->hdr.length); + + return ofs; +} + +static int acpi_write_pptt(struct acpi_ctx *ctx, const struct acpi_writer *entry) +{ + struct acpi_table_header *header; + int proc_ofs; + u32 *proc_ptr; + int ofs, ofs0, ofs1, i; + + if (!CONFIG_IS_ENABLED(BCM2711_64B)) { + return 0; + } + + header = ctx->current; + ctx->tab_start = ctx->current; + + memset(header, '\0', sizeof(struct acpi_table_header)); + + acpi_fill_header(header, "PPTT"); + header->revision = 0; + acpi_inc(ctx, sizeof(*header)); + + proc_ofs = ctx->current - ctx->tab_start; + proc_ptr = add_proc(ctx, ACPI_PPTT_PHYSICAL_PACKAGE | + ACPI_PPTT_CHILDREN_IDENTICAL, 0, 0, 1); + + ofs = add_cache(ctx, ACPI_PPTT_ALL_VALID, 0x100000, 0x400, 0x10, + ACPI_PPTT_WRITE_ALLOC | + (ACPI_PPTT_CACHE_TYPE_UNIFIED << + ACPI_PPTT_CACHE_TYPE_SHIFT), 0x40); + *proc_ptr = ofs; + + for (i = 0; i < 4; i++) { + proc_ptr = add_proc(ctx, ACPI_PPTT_CHILDREN_IDENTICAL | + ACPI_PPTT_NODE_IS_LEAF | ACPI_PPTT_PROC_ID_VALID, + proc_ofs, i, 2); + + ofs0 = add_cache(ctx, ACPI_PPTT_ALL_VALID, 0x8000, 0x100, 2, + ACPI_PPTT_WRITE_ALLOC, 0x40); + + ofs1 = add_cache(ctx, ACPI_PPTT_ALL_BUT_WRITE_POL, 0xc000, 0x100, 3, + ACPI_PPTT_CACHE_TYPE_INSTR << + ACPI_PPTT_CACHE_TYPE_SHIFT, 0x40); + proc_ptr[0] = ofs0; + proc_ptr[1] = ofs1; + } + + header->length = ctx->current - ctx->tab_start; + header->checksum = table_compute_checksum(header, header->length); + + acpi_inc(ctx, header->length); + acpi_add_table(ctx, header); + + return 0; +}; +ACPI_WRITER(5pptt, "PPTT", acpi_write_pptt, 0); + + +#define GTDT_FLAG_INT_ACTIVE_LOW BIT(1) +#define RPI_GTDT_GTIMER_FLAGS GTDT_FLAG_INT_ACTIVE_LOW + +/* ARM Architectural Timer Interrupt(GIC PPI) numbers */ +#define PcdArmArchTimerSecIntrNum 29 +#define PcdArmArchTimerIntrNum 30 +#define PcdArmArchTimerHypIntrNum 26 +#define PcdArmArchTimerVirtIntrNum 27 + +static int rpi_write_gtdt(struct acpi_ctx *ctx, const struct acpi_writer *entry) +{ + struct acpi_table_header *header; + struct acpi_gtdt *gtdt; + + gtdt = ctx->current; + header = >dt->header; + + memset(gtdt, '\0', sizeof(struct acpi_gtdt)); + + acpi_fill_header(header, "GTDT"); + header->length = sizeof(struct acpi_gtdt); + header->revision = 3; + + gtdt->cnt_ctrl_base = 0xff80001c; + gtdt->sec_el1_gsiv = PcdArmArchTimerSecIntrNum; + gtdt->sec_el1_flags = RPI_GTDT_GTIMER_FLAGS; + gtdt->el1_gsiv = PcdArmArchTimerIntrNum; + gtdt->el1_flags = RPI_GTDT_GTIMER_FLAGS; + gtdt->virt_el1_gsiv = PcdArmArchTimerVirtIntrNum; + gtdt->virt_el1_flags = RPI_GTDT_GTIMER_FLAGS; + gtdt->el2_gsiv = PcdArmArchTimerHypIntrNum; + gtdt->el2_flags = RPI_GTDT_GTIMER_FLAGS; + gtdt->cnt_read_base = 0xffffffffffffffff; + + header->checksum = table_compute_checksum(header, header->length); + + acpi_add_table(ctx, gtdt); + + acpi_inc(ctx, sizeof(struct acpi_gtdt)); + + return 0; +}; +ACPI_WRITER(5gtdt, "GTDT", rpi_write_gtdt, 0); \ No newline at end of file diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 016bc1eb412..a7dd2876c09 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -7,11 +7,13 @@ */ #include +#include #include #include #include #include #include +#include #define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL #define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x400000UL @@ -241,3 +243,26 @@ void enable_caches(void) dcache_enable(); } #endif + +#ifdef CONFIG_GENERATE_ACPI_TABLE +static int last_stage_init(void) +{ + ulong end; + void *ptr; + + /* Reserve 128K for ACPI tables, aligned to a 4K boundary */ + ptr = memalign(SZ_4K, SZ_128K); + + /* Generate ACPI tables */ + end = write_acpi_tables((uintptr_t)ptr); + if (end < 0) { + log_err("Failed to write tables\n"); + return log_msg_ret("table", end); + } + gd->arch.table_start = (uintptr_t)ptr; + gd->arch.table_end = end; + + return 0; +} +EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init); +#endif \ No newline at end of file From 06c34c6b35f62ceac182c52f900410fca9772939 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 1 Dec 2021 16:03:10 +0000 Subject: [PATCH 27/31] WIP: Add debugging for ACPI emission Turn this on for debugging purposes. Signed-off-by: Simon Glass --- lib/acpi/acpi_writer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/acpi/acpi_writer.c b/lib/acpi/acpi_writer.c index bbb9b54786d..3575f82d9f3 100644 --- a/lib/acpi/acpi_writer.c +++ b/lib/acpi/acpi_writer.c @@ -6,6 +6,7 @@ */ #define LOG_CATEGORY LOGC_ACPI +#define LOG_DEBUG #include #include From e792755c927e9e623820caea30e9efd5b92507f0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 1 Dec 2021 16:03:11 +0000 Subject: [PATCH 28/31] RFC: Allow passing ACPI tables to bootefi At present it seems possible to pass ACPI tables using bootefi but in practice an error is produced about not beling allowed to pass devicetree as well. Add some workarounds for this. Presumably I am missing something and this should already work. Perhaps fdt should be set to 0? Not to be applied. Signed-off-by: Simon Glass --- cmd/bootefi.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/cmd/bootefi.c b/cmd/bootefi.c index c1454ffb948..7469c2a39b8 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -143,10 +143,11 @@ static int do_bootefi(struct cmd_tbl *cmdtp, int flag, int argc, if (argc > 2) { uintptr_t fdt_addr; - fdt_addr = hextoul(argv[2], NULL); - fdt = map_sysmem(fdt_addr, 0); - } else { - fdt = EFI_FDT_USE_INTERNAL; + ret = efi_install_fdt(fdt); + if (ret == EFI_INVALID_PARAMETER) + return CMD_RET_USAGE; + else if (ret != EFI_SUCCESS) + return CMD_RET_FAILURE; } if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR) && From c9815fca8508ee5fa4b7a49bfa614ffbd33dbcc8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 1 Dec 2021 16:03:12 +0000 Subject: [PATCH 29/31] WIP: Add ASL files from tianocore Bring in some ACPI files, some of which are needed to build the ACPI tables for Raspberry Pi. This needs to be sorted out. Signed-off-by: Simon Glass --- board/raspberrypi/rpi/acpitables.h | 189 ++++++ board/raspberrypi/rpi/acpitables.inf | 79 +++ board/raspberrypi/rpi/csrt.aslc | 330 ++++++++++ board/raspberrypi/rpi/dbg2miniuart.aslc | 81 +++ board/raspberrypi/rpi/dbg2pl011.aslc | 81 +++ board/raspberrypi/rpi/dsdt.asl | 279 +++++++++ board/raspberrypi/rpi/emmc.asl | 166 +++++ board/raspberrypi/rpi/fadt.aslc | 96 +++ board/raspberrypi/rpi/gpudevs.asl | 393 ++++++++++++ board/raspberrypi/rpi/gtdt.aslc | 55 ++ board/raspberrypi/rpi/iort.aslc | 100 +++ board/raspberrypi/rpi/madt.aslc | 78 +++ board/raspberrypi/rpi/pci.asl | 168 +++++ board/raspberrypi/rpi/pep.asl | 90 +++ board/raspberrypi/rpi/pep.c | 79 +++ board/raspberrypi/rpi/pep.h | 121 ++++ board/raspberrypi/rpi/pptt.aslc | 191 ++++++ board/raspberrypi/rpi/rhpx.asl | 195 ++++++ board/raspberrypi/rpi/rpi4.dsc | 790 ++++++++++++++++++++++++ board/raspberrypi/rpi/sdhc.asl | 119 ++++ board/raspberrypi/rpi/spcrminiuart.aslc | 91 +++ board/raspberrypi/rpi/spcrpl011.aslc | 91 +++ board/raspberrypi/rpi/ssdtthermal.asl | 77 +++ board/raspberrypi/rpi/uart.asl | 202 ++++++ board/raspberrypi/rpi/xhci.asl | 165 +++++ 25 files changed, 4306 insertions(+) create mode 100644 board/raspberrypi/rpi/acpitables.h create mode 100644 board/raspberrypi/rpi/acpitables.inf create mode 100644 board/raspberrypi/rpi/csrt.aslc create mode 100644 board/raspberrypi/rpi/dbg2miniuart.aslc create mode 100644 board/raspberrypi/rpi/dbg2pl011.aslc create mode 100644 board/raspberrypi/rpi/dsdt.asl create mode 100644 board/raspberrypi/rpi/emmc.asl create mode 100644 board/raspberrypi/rpi/fadt.aslc create mode 100644 board/raspberrypi/rpi/gpudevs.asl create mode 100644 board/raspberrypi/rpi/gtdt.aslc create mode 100644 board/raspberrypi/rpi/iort.aslc create mode 100644 board/raspberrypi/rpi/madt.aslc create mode 100644 board/raspberrypi/rpi/pci.asl create mode 100644 board/raspberrypi/rpi/pep.asl create mode 100644 board/raspberrypi/rpi/pep.c create mode 100644 board/raspberrypi/rpi/pep.h create mode 100644 board/raspberrypi/rpi/pptt.aslc create mode 100644 board/raspberrypi/rpi/rhpx.asl create mode 100644 board/raspberrypi/rpi/rpi4.dsc create mode 100644 board/raspberrypi/rpi/sdhc.asl create mode 100644 board/raspberrypi/rpi/spcrminiuart.aslc create mode 100644 board/raspberrypi/rpi/spcrpl011.aslc create mode 100644 board/raspberrypi/rpi/ssdtthermal.asl create mode 100644 board/raspberrypi/rpi/uart.asl create mode 100644 board/raspberrypi/rpi/xhci.asl diff --git a/board/raspberrypi/rpi/acpitables.h b/board/raspberrypi/rpi/acpitables.h new file mode 100644 index 00000000000..74461350f19 --- /dev/null +++ b/board/raspberrypi/rpi/acpitables.h @@ -0,0 +1,189 @@ +/** @file + * + * RPi defines for constructing ACPI tables + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2019, ARM Ltd. All rights reserved. + * Copyright (c) 2018, Andrei Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __RPI_ACPITABLES_H__ +#define __RPI_ACPITABLES_H__ + +#include + +#ifdef CONFIG_TARGET_RPI_4 +#define RPI_MODEL 4 +#elif CONFIG_TARGET_RPI_3 +#define RPI_MODEL 3 +#else +#error "Unsupported rpi module for ACPI tables" +#endif + +/* These are taken from rpi.dsc */ +#define PcdBcm283xRegistersAddress 0xfe000000 +#define PcdBcmGenetRegistersAddress 0xfd580000 + +#define FixedPcdGet64(x) x + +// The ASL compiler can't perform arithmetic on MEMORY32FIXED () +// parameters so you can't pass a constant like BASE + OFFSET. +// We therefore define a macro that can perform arithmetic base +// address update with an offset. +#define MEMORY32SETBASE(BufName, MemName, VarName, Offset) \ + CreateDwordField (^BufName, ^MemName._BAS, VarName) \ + Add (BCM2836_SOC_REGISTERS, Offset, VarName) + +#define EFI_ACPI_OEM_ID {'R','P','I','F','D','N'} +#if (RPI_MODEL == 3) +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64 ('R','P','I','3',' ',' ',' ',' ') +#elif (RPI_MODEL == 4) +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64 ('R','P','I','4',' ',' ',' ',' ') +#endif +#define EFI_ACPI_OEM_REVISION 0x00000200 +#define EFI_ACPI_CREATOR_ID SIGNATURE_32 ('E','D','K','2') +#define EFI_ACPI_CREATOR_REVISION 0x00000300 + +#define EFI_ACPI_VENDOR_ID SIGNATURE_32 ('R','P','I','F') + +// A macro to initialise the common header part of EFI ACPI tables as defined by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define ACPI_HEADER(Signature, Type, Revision) { \ + Signature, /* u32 Signature */ \ + sizeof (Type), /* u32 Length */ \ + Revision, /* u8 Revision */ \ + 0, /* u8 Checksum */ \ + EFI_ACPI_OEM_ID, /* u8 OemId[6] */ \ + EFI_ACPI_OEM_TABLE_ID, /* u64 OemTableId */ \ + EFI_ACPI_OEM_REVISION, /* u32 OemRevision */ \ + EFI_ACPI_CREATOR_ID, /* u32 CreatorId */ \ + EFI_ACPI_CREATOR_REVISION /* u32 CreatorRevision */ \ + } + +#define EFI_ACPI_CSRT_REVISION 0x00000005 +#define EFI_ACPI_CSRT_DEVICE_ID_DMA 0x00000009 // Fixed id +#define EFI_ACPI_CSRT_RESOURCE_ID_IN_DMA_GRP 0x0 // Count up from 0 + +#define RPI_DMA_CHANNEL_COUNT 10 // All 10 DMA channels are listed, including the reserved ones +#define RPI_DMA_USED_CHANNEL_COUNT 5 // Use 5 DMA channels + +#if (RPI_MODEL == 3) +#define RPI_SYSTEM_TIMER_BASE_ADDRESS 0x4000001c +#elif (RPI_MODEL == 4) +#define RPI_SYSTEM_TIMER_BASE_ADDRESS 0xff80001c +#else +#error "Unknown RPI_DMA_CHANNEL_COUNT model" +#endif + +#define EFI_ACPI_6_3_CSRT_REVISION 0x00000000 + +#if !defined(__ACPI__) + +typedef enum +{ + EFI_ACPI_CSRT_RESOURCE_TYPE_RESERVED, // 0 + EFI_ACPI_CSRT_RESOURCE_TYPE_INTERRUPT, // 1 + EFI_ACPI_CSRT_RESOURCE_TYPE_TIMER, // 2 + EFI_ACPI_CSRT_RESOURCE_TYPE_DMA, // 3 + EFI_ACPI_CSRT_RESOURCE_TYPE_CACHE, // 4 +} +CSRT_RESOURCE_TYPE; + +typedef enum +{ + EFI_ACPI_CSRT_RESOURCE_SUBTYPE_DMA_CHANNEL, // 0 + EFI_ACPI_CSRT_RESOURCE_SUBTYPE_DMA_CONTROLLER // 1 +} +CSRT_DMA_SUBTYPE; + +//------------------------------------------------------------------------ +// CSRT Resource Group header 24 bytes long +//------------------------------------------------------------------------ +typedef struct +{ + u32 Length; // Length + u32 VendorID; // 4 bytes + u32 SubVendorId; // 4 bytes + u16 DeviceId; // 2 bytes + u16 SubdeviceId; // 2 bytes + u16 Revision; // 2 bytes + u16 Reserved; // 2 bytes + u32 SharedInfoLength; // 4 bytes +} EFI_ACPI_6_3_CSRT_RESOURCE_GROUP_HEADER; + +//------------------------------------------------------------------------ +// CSRT Resource Descriptor 12 bytes total +//------------------------------------------------------------------------ +typedef struct +{ + u32 Length; // 4 bytes + u16 ResourceType; // 2 bytes + u16 ResourceSubType; // 2 bytes + u32 UID; // 4 bytes +} EFI_ACPI_6_3_CSRT_RESOURCE_DESCRIPTOR_HEADER; + +#endif /* __ACPI__ */ + + +//------------------------------------------------------------------------ +// Interrupts. These are specific to each platform +//------------------------------------------------------------------------ +#if (RPI_MODEL == 3) +#define BCM2836_V3D_BUS_INTERRUPT 0x2A +#define BCM2836_DMA_INTERRUPT 0x3B +#define BCM2836_SPI1_INTERRUPT 0x3D +#define BCM2836_SPI2_INTERRUPT 0x3D +#define BCM2836_HVS_INTERRUPT 0x41 +#define BCM2836_HDMI0_INTERRUPT 0x48 +#define BCM2836_HDMI1_INTERRUPT 0x49 +#define BCM2836_PV2_INTERRUPT 0x4A +#define BCM2836_PV0_INTERRUPT 0x4D +#define BCM2836_PV1_INTERRUPT 0x4E +#define BCM2836_MBOX_INTERRUPT 0x61 +#define BCM2836_VCHIQ_INTERRUPT 0x62 +#define BCM2386_GPIO_INTERRUPT0 0x51 +#define BCM2386_GPIO_INTERRUPT1 0x52 +#define BCM2386_GPIO_INTERRUPT2 0x53 +#define BCM2386_GPIO_INTERRUPT3 0x54 +#define BCM2836_I2C1_INTERRUPT 0x55 +#define BCM2836_I2C2_INTERRUPT 0x55 +#define BCM2836_SPI0_INTERRUPT 0x56 +#define BCM2836_USB_INTERRUPT 0x29 +#define BCM2836_SDHOST_INTERRUPT 0x58 +#define BCM2836_MMCHS1_INTERRUPT 0x5E +#define BCM2836_MINI_UART_INTERRUPT 0x3D +#define BCM2836_PL011_UART_INTERRUPT 0x59 +#elif (RPI_MODEL == 4) +#define BCM2836_V3D_BUS_INTERRUPT 0x2A +#define BCM2836_DMA_INTERRUPT 0x3B +#define BCM2836_SPI1_INTERRUPT 0x7D +#define BCM2836_SPI2_INTERRUPT 0x7D +#define BCM2836_HVS_INTERRUPT 0x41 +#define BCM2836_HDMI0_INTERRUPT 0x48 +#define BCM2836_HDMI1_INTERRUPT 0x49 +#define BCM2836_PV2_INTERRUPT 0x4A +#define BCM2836_PV0_INTERRUPT 0x4D +#define BCM2836_PV1_INTERRUPT 0x4E +#define BCM2836_MBOX_INTERRUPT 0x41 +#define BCM2836_VCHIQ_INTERRUPT 0x42 +#define BCM2386_GPIO_INTERRUPT0 0x91 +#define BCM2386_GPIO_INTERRUPT1 0x92 +#define BCM2386_GPIO_INTERRUPT2 0x93 +#define BCM2386_GPIO_INTERRUPT3 0x94 +#define BCM2836_I2C1_INTERRUPT 0x95 +#define BCM2836_I2C2_INTERRUPT 0x95 +#define BCM2836_SPI0_INTERRUPT 0x96 +#define BCM2836_USB_INTERRUPT 0x69 +#define BCM2836_SDHOST_INTERRUPT 0x98 +#define BCM2836_MMCHS1_INTERRUPT 0x9E +#define BCM2836_MINI_UART_INTERRUPT 0x7D +#define BCM2836_PL011_UART_INTERRUPT 0x99 +#define GENET_INTERRUPT0 0xBD +#define GENET_INTERRUPT1 0xBE +#endif + +#endif // __ACPITABLES_H__ diff --git a/board/raspberrypi/rpi/acpitables.inf b/board/raspberrypi/rpi/acpitables.inf new file mode 100644 index 00000000000..11aca9be39e --- /dev/null +++ b/board/raspberrypi/rpi/acpitables.inf @@ -0,0 +1,79 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) 2017, Andrey Warkentin +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + AcpiTables.h + Emmc.asl + Madt.aslc + Fadt.aslc + Dbg2MiniUart.aslc + Dbg2Pl011.aslc + Gtdt.aslc + Iort.aslc + Dsdt.asl + Csrt.aslc + SpcrMiniUart.aslc + SpcrPl011.aslc + Pptt.aslc + SsdtThermal.asl + Xhci.asl + Pci.asl + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/RaspberryPi/RaspberryPi.dec + Silicon/Broadcom/Bcm27xx/Bcm27xx.dec + Silicon/Broadcom/Bcm283x/Bcm283x.dec + Silicon/Broadcom/Drivers/Net/BcmNet.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase + gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress + gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gEmbeddedTokenSpaceGuid.PcdInterruptBaseAddress + gRaspberryPiTokenSpaceGuid.PcdGicInterruptInterfaceHBase + gRaspberryPiTokenSpaceGuid.PcdGicInterruptInterfaceVBase + gRaspberryPiTokenSpaceGuid.PcdGicGsivId + gRaspberryPiTokenSpaceGuid.PcdGicPmuIrq0 + gRaspberryPiTokenSpaceGuid.PcdGicPmuIrq1 + gRaspberryPiTokenSpaceGuid.PcdGicPmuIrq2 + gRaspberryPiTokenSpaceGuid.PcdGicPmuIrq3 + +[BuildOptions] + GCC:*_*_*_ASL_FLAGS = -vw3133 -vw3150 diff --git a/board/raspberrypi/rpi/csrt.aslc b/board/raspberrypi/rpi/csrt.aslc new file mode 100644 index 00000000000..b230f95ed07 --- /dev/null +++ b/board/raspberrypi/rpi/csrt.aslc @@ -0,0 +1,330 @@ +/** @file + * + * Core System Resource Table (CSRT) + * + * Copyright (c) 2019, ARM Ltd. All rights reserved. + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include + +#include "AcpiTables.h" + +#define RPI_DMA_MAX_REQ_LINES 32 + +#pragma pack (push, 1) + +//------------------------------------------------------------------------ +// DMA Controller Vendor Data +//------------------------------------------------------------------------ +typedef struct +{ + UINT32 Length; + UINT32 Type; + UINT64 ChannelsBaseAddress; + UINT32 ChannelsBaseSize; + UINT64 ControllerBaseAddress; + UINT32 ControllerBaseSize; + UINT32 ChannelCount; + UINT32 ControllerInterrupt; + UINT32 MinimumRequestLine; + UINT32 MaximumRequestLine; + BOOLEAN CacheCoherent; +} DMA_CONTROLLER_VENDOR_DATA; + +//------------------------------------------------------------------------ +// DMA Controller +//------------------------------------------------------------------------ +typedef struct +{ + EFI_ACPI_6_3_CSRT_RESOURCE_DESCRIPTOR_HEADER DmaControllerHeader; + DMA_CONTROLLER_VENDOR_DATA ControllerVendorData; +} RD_DMA_CONTROLLER; + +//------------------------------------------------------------------------ +// DMA Channel Vendor Data +//------------------------------------------------------------------------ +typedef struct +{ + UINT32 ChannelNumber; + UINT32 ChannelInterrupt; + UINT16 IsReservedChannel; + UINT16 NoSrcNoDestAddrIncr; +} DMA_CHANNEL_VENDOR_DATA; + +//------------------------------------------------------------------------ +// DMA Channel +//------------------------------------------------------------------------ +typedef struct +{ + EFI_ACPI_6_3_CSRT_RESOURCE_DESCRIPTOR_HEADER DmaChannelHeader; + DMA_CHANNEL_VENDOR_DATA ChannelVendorData; +} RD_DMA_CHANNEL; + +//------------------------------------------------------------------------ +// DMA Resource Group +//------------------------------------------------------------------------ + +typedef struct +{ + EFI_ACPI_6_3_CSRT_RESOURCE_GROUP_HEADER ResGroupHeader; + RD_DMA_CONTROLLER DmaController; + RD_DMA_CHANNEL DmaChannels[RPI_DMA_CHANNEL_COUNT]; +} RG_DMA; + +//---------------------------------------------------------------------------- +// CSRT table structure - current revision only includes DMA +//---------------------------------------------------------------------------- +typedef struct +{ +// Standard ACPI Header + EFI_ACPI_DESCRIPTION_HEADER CsrtHeader; + +// DMA Resource Group + RG_DMA DmaResourceGroup; + +} EFI_ACPI_6_3_CSRT_TABLE; + +EFI_ACPI_6_3_CSRT_TABLE Csrt = +{ + //------------------------------------------------------------------------ + // ACPI Table Header + //------------------------------------------------------------------------ + { + EFI_ACPI_6_3_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE, // Signature "CSRT" + sizeof (EFI_ACPI_DESCRIPTION_HEADER) + sizeof (RG_DMA), // Length + EFI_ACPI_6_3_CSRT_REVISION, // Revision + 0x00, // Checksum calculated at runtime. + EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field + EFI_ACPI_OEM_TABLE_ID, // OEM table identification (8 bytes long) + EFI_ACPI_OEM_REVISION, // OEM revision number. + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID. + EFI_ACPI_CREATOR_REVISION // ASL compiler revision number. + }, + + //------------------------------------------------------------------------ + // DMA Resource Group + //------------------------------------------------------------------------ + { + + //------------------------------------------------------------------------ + // DMA Resource Group Header + //------------------------------------------------------------------------ + { + sizeof (RG_DMA), // Resource Group Length + EFI_ACPI_VENDOR_ID, // VendorId + 0, // SubvendorId + EFI_ACPI_CSRT_DEVICE_ID_DMA, // DeviceId 9 + 0, // SubdeviceId + 0, // Revision + 0, // Reserved + 0 // SharedInfoLength + }, + + //------------------------------------------------------------------------------- + // Resource Descriptor - DMA Controller + //------------------------------------------------------------------------------- + { + { + sizeof (RD_DMA_CONTROLLER), // Length of this Resource Descriptor + EFI_ACPI_CSRT_RESOURCE_TYPE_DMA, // Type for this resource 3=DMA + EFI_ACPI_CSRT_RESOURCE_SUBTYPE_DMA_CONTROLLER, // Subtype for this resource 1=DMA Controller + EFI_ACPI_CSRT_RESOURCE_ID_IN_DMA_GRP + 0, // ResourceId - 1st DMA controller + }, + { + sizeof (DMA_CONTROLLER_VENDOR_DATA), // Controller vendor data here + 1, + BCM2836_DMA0_BASE_ADDRESS, // Base address for channels + RPI_DMA_CHANNEL_COUNT * BCM2836_DMA_CHANNEL_LENGTH, // Base size = Number of channels x channel size + BCM2836_DMA_CTRL_BASE_ADDRESS,// Base address for controller + 8, // Base size = two registers + RPI_DMA_USED_CHANNEL_COUNT, + 0, // cannot use controller interrupt + 0, // Minimum Request Line + RPI_DMA_MAX_REQ_LINES - 1, // Maximum Request Line + FALSE, + }, + }, + + //------------------------------------------------------------------------ + // Resource Descriptor(s) - DMA Channels 0 to n-1 + //------------------------------------------------------------------------ + { + + // Channel 0 + { + { + sizeof (RD_DMA_CHANNEL), // Length of this Resource Descriptor + EFI_ACPI_CSRT_RESOURCE_TYPE_DMA, // Type for this resource 3=DMA + EFI_ACPI_CSRT_RESOURCE_SUBTYPE_DMA_CHANNEL, // Subtype for this resource 0=DMA Channel + EFI_ACPI_CSRT_RESOURCE_ID_IN_DMA_GRP + 1, // ResourceId + }, + { + 0, // Channel vendor data here + 0x30, // 16+32 dma_int[0] + 0, + 0 + }, + }, + + // Channel 1 reserved + { + { + sizeof (RD_DMA_CHANNEL), + EFI_ACPI_CSRT_RESOURCE_TYPE_DMA, + EFI_ACPI_CSRT_RESOURCE_SUBTYPE_DMA_CHANNEL, + EFI_ACPI_CSRT_RESOURCE_ID_IN_DMA_GRP + 2, // ResourceId + }, + { + 1, // Channel vendor data here + 0x31, // 17+32 dma_int[1] + 1, + 0 + }, + }, + + // Channel 2 - VC4 use only + { + { + sizeof (RD_DMA_CHANNEL), + EFI_ACPI_CSRT_RESOURCE_TYPE_DMA, + EFI_ACPI_CSRT_RESOURCE_SUBTYPE_DMA_CHANNEL, + EFI_ACPI_CSRT_RESOURCE_ID_IN_DMA_GRP + 3, // ResourceId + }, + { + 2, // Channel vendor data here + 0x32, // 18+32 dma_int[2] + 1, + 0 + }, + }, + + // Channel 3 - VC4 use only + { + { + sizeof (RD_DMA_CHANNEL), + EFI_ACPI_CSRT_RESOURCE_TYPE_DMA, + EFI_ACPI_CSRT_RESOURCE_SUBTYPE_DMA_CHANNEL, + EFI_ACPI_CSRT_RESOURCE_ID_IN_DMA_GRP + 4, + }, + { + 3, // Channel vendor data here + 0x33, // 19+32 dma_int[3] + 1, + 0 + }, + }, + + // channel 4 + { + { + sizeof (RD_DMA_CHANNEL), + EFI_ACPI_CSRT_RESOURCE_TYPE_DMA, + EFI_ACPI_CSRT_RESOURCE_SUBTYPE_DMA_CHANNEL, + EFI_ACPI_CSRT_RESOURCE_ID_IN_DMA_GRP + 5, + }, + { + 4, // Channel vendor data here + 0x34, // 20+32 dma_int[4] + 0, + 1 // SD host controller candidate + }, + }, + + // Channel 5 + { + { + sizeof (RD_DMA_CHANNEL), + EFI_ACPI_CSRT_RESOURCE_TYPE_DMA, + EFI_ACPI_CSRT_RESOURCE_SUBTYPE_DMA_CHANNEL, + EFI_ACPI_CSRT_RESOURCE_ID_IN_DMA_GRP + 6, + }, + { + 5, // Channel vendor data here + 0x35, // 21+32 dma_int[5] + 0, + 0 + }, + }, + + // Channel 6 is reserved + { + { + sizeof (RD_DMA_CHANNEL), + EFI_ACPI_CSRT_RESOURCE_TYPE_DMA, + EFI_ACPI_CSRT_RESOURCE_SUBTYPE_DMA_CHANNEL, + EFI_ACPI_CSRT_RESOURCE_ID_IN_DMA_GRP + 7, + }, + { + 6, // Channel vendor data here + 0x36, // 22+32 dma_int[6] + 1, + 0 + }, + }, + + // Channel 7 is reserved + { + { + sizeof (RD_DMA_CHANNEL), + EFI_ACPI_CSRT_RESOURCE_TYPE_DMA, + EFI_ACPI_CSRT_RESOURCE_SUBTYPE_DMA_CHANNEL, + EFI_ACPI_CSRT_RESOURCE_ID_IN_DMA_GRP + 8, + }, + { + 7, // Channel vendor data here + 0x37, // 23+32 dma_int[7] + 1, + 0 + }, + }, + + // Channel 8 + { + { + sizeof (RD_DMA_CHANNEL), + EFI_ACPI_CSRT_RESOURCE_TYPE_DMA, + EFI_ACPI_CSRT_RESOURCE_SUBTYPE_DMA_CHANNEL, + EFI_ACPI_CSRT_RESOURCE_ID_IN_DMA_GRP + 9, + }, + { + 8, // Channel vendor data here + 0x38, // 24+32 dma_int[8] + 0, + 0 + }, + }, + + // Channel 9 + { + { + sizeof (RD_DMA_CHANNEL), + EFI_ACPI_CSRT_RESOURCE_TYPE_DMA, + EFI_ACPI_CSRT_RESOURCE_SUBTYPE_DMA_CHANNEL, + EFI_ACPI_CSRT_RESOURCE_ID_IN_DMA_GRP + 10, + }, + { + 9, // channel vendor data here + 0x39, // 25+32 dma_int[9] + 0, + 0 + }, + } + + } // End DMA Channels 0 to 14 + + } // End DMA Resource group + +}; + +#pragma pack(pop) + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Csrt; diff --git a/board/raspberrypi/rpi/dbg2miniuart.aslc b/board/raspberrypi/rpi/dbg2miniuart.aslc new file mode 100644 index 00000000000..518d8a33e0c --- /dev/null +++ b/board/raspberrypi/rpi/dbg2miniuart.aslc @@ -0,0 +1,81 @@ +/** @file + * + * Debug Port Table (DBG2) + * + * Copyright (c) 2019, Pete Batard + * Copyright (c) 2012-2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include + +#include "AcpiTables.h" + +#pragma pack(1) + +#define RPI_UART_INTERFACE_TYPE EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_BCM2835_UART +#define RPI_UART_BASE_ADDRESS BCM2836_MINI_UART_BASE_ADDRESS +#define RPI_UART_LENGTH BCM2836_MINI_UART_LENGTH +// +// RPI_UART_STR should match the value used Uart.asl +// +#define RPI_UART_STR { '\\', '_', 'S', 'B', '.', 'G', 'D', 'V', '0', '.', 'U', 'R', 'T', 'M', 0x00 } + +#define DBG2_DEBUG_PORT_DDI(NumReg, SubType, UartBase, UartAddrLen, UartNameStr) { \ + { \ + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, /* UINT8 Revision */ \ + sizeof (DBG2_DEBUG_DEVICE_INFORMATION), /* UINT16 Length */ \ + NumReg, /* UINT8 NumberofGenericAddressRegisters */ \ + RPI_DBG2_NAMESPACESTRING_FIELD_SIZE, /* UINT16 NameSpaceStringLength */ \ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), /* UINT16 NameSpaceStringOffset */ \ + 0, /* UINT16 OemDataLength */ \ + 0, /* UINT16 OemDataOffset */ \ + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, /* UINT16 Port Type */ \ + SubType, /* UINT16 Port Subtype */ \ + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, /* UINT8 Reserved[2] */ \ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), /* UINT16 BaseAddressRegister Offset */ \ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) /* UINT16 AddressSize Offset */ \ + }, \ + ARM_GAS32 (UartBase), /* EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister */ \ + UartAddrLen, /* UINT32 AddressSize */ \ + UartNameStr /* UINT8 NameSpaceString[MAX_DBG2_NAME_LEN] */ \ + } + + +STATIC DBG2_TABLE Dbg2 = { + { + ACPI_HEADER ( + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE, + DBG2_TABLE, + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION + ), + OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo), + RPI_DBG2_NUM_DEBUG_PORTS /* UINT32 NumberDbgDeviceInfo */ + }, + { + /* + * Kernel Debug Port + */ + DBG2_DEBUG_PORT_DDI ( + RPI_DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS, + RPI_UART_INTERFACE_TYPE, + RPI_UART_BASE_ADDRESS, + RPI_UART_LENGTH, + RPI_UART_STR + ), + } +}; + +#pragma pack() + +// +// Reference the table being generated to prevent the optimizer from removing +// the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Dbg2; diff --git a/board/raspberrypi/rpi/dbg2pl011.aslc b/board/raspberrypi/rpi/dbg2pl011.aslc new file mode 100644 index 00000000000..1a87fb8bfa6 --- /dev/null +++ b/board/raspberrypi/rpi/dbg2pl011.aslc @@ -0,0 +1,81 @@ +/** @file + * + * Debug Port Table (DBG2) + * + * Copyright (c) 2019, Pete Batard + * Copyright (c) 2012-2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include + +#include "AcpiTables.h" + +#pragma pack(1) + +#define RPI_UART_INTERFACE_TYPE EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART +#define RPI_UART_BASE_ADDRESS BCM2836_PL011_UART_BASE_ADDRESS +#define RPI_UART_LENGTH BCM2836_PL011_UART_LENGTH +// +// RPI_UART_STR should match the value used Uart.asl +// +#define RPI_UART_STR { '\\', '_', 'S', 'B', '.', 'G', 'D', 'V', '0', '.', 'U', 'R', 'T', '0', 0x00 } + +#define DBG2_DEBUG_PORT_DDI(NumReg, SubType, UartBase, UartAddrLen, UartNameStr) { \ + { \ + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, /* UINT8 Revision */ \ + sizeof (DBG2_DEBUG_DEVICE_INFORMATION), /* UINT16 Length */ \ + NumReg, /* UINT8 NumberofGenericAddressRegisters */ \ + RPI_DBG2_NAMESPACESTRING_FIELD_SIZE, /* UINT16 NameSpaceStringLength */ \ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), /* UINT16 NameSpaceStringOffset */ \ + 0, /* UINT16 OemDataLength */ \ + 0, /* UINT16 OemDataOffset */ \ + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, /* UINT16 Port Type */ \ + SubType, /* UINT16 Port Subtype */ \ + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, /* UINT8 Reserved[2] */ \ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), /* UINT16 BaseAddressRegister Offset */ \ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) /* UINT16 AddressSize Offset */ \ + }, \ + ARM_GAS32 (UartBase), /* EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister */ \ + UartAddrLen, /* UINT32 AddressSize */ \ + UartNameStr /* UINT8 NameSpaceString[MAX_DBG2_NAME_LEN] */ \ + } + + +STATIC DBG2_TABLE Dbg2 = { + { + ACPI_HEADER ( + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE, + DBG2_TABLE, + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION + ), + OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo), + RPI_DBG2_NUM_DEBUG_PORTS /* UINT32 NumberDbgDeviceInfo */ + }, + { + /* + * Kernel Debug Port + */ + DBG2_DEBUG_PORT_DDI ( + RPI_DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS, + RPI_UART_INTERFACE_TYPE, + RPI_UART_BASE_ADDRESS, + RPI_UART_LENGTH, + RPI_UART_STR + ), + } +}; + +#pragma pack() + +// +// Reference the table being generated to prevent the optimizer from removing +// the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Dbg2; diff --git a/board/raspberrypi/rpi/dsdt.asl b/board/raspberrypi/rpi/dsdt.asl new file mode 100644 index 00000000000..1376fe47310 --- /dev/null +++ b/board/raspberrypi/rpi/dsdt.asl @@ -0,0 +1,279 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include +#include +#include + +#include "acpitables.h" + +#define BCM_ALT0 0x4 +#define BCM_ALT1 0x5 +#define BCM_ALT2 0x6 +#define BCM_ALT3 0x7 +#define BCM_ALT4 0x3 +#define BCM_ALT5 0x2 + +// +// The ASL compiler does not support argument arithmetic in functions +// like QWordMemory (). So we need to instantiate dummy qword regions +// that we can then update the Min, Max and Length attributes of. +// The three macros below help accomplish this. +// +// QWORDMEMORYSET specifies a CPU memory range (whose base address is +// BCM2836_SOC_REGISTERS + Offset), and QWORDBUSMEMORYSET specifies +// a VPU memory range (whose base address is provided directly). +// +#define QWORDMEMORYBUF(Index) \ + QWordMemory (ResourceProducer,, \ + MinFixed, MaxFixed, NonCacheable, ReadWrite, \ + 0x0, 0x0, 0x0, 0x0, 0x1,,, RB ## Index) + +#define QWORDMEMORYSET(Index, Offset, Length) \ + CreateQwordField (RBUF, RB ## Index._MIN, MI ## Index) \ + CreateQwordField (RBUF, RB ## Index._MAX, MA ## Index) \ + CreateQwordField (RBUF, RB ## Index._LEN, LE ## Index) \ + Store (Length, LE ## Index) \ + Add (BCM2836_SOC_REGISTERS, Offset, MI ## Index) \ + Add (MI ## Index, LE ## Index - 1, MA ## Index) + +#define QWORDBUSMEMORYSET(Index, Base, Length) \ + CreateQwordField (RBUF, RB ## Index._MIN, MI ## Index) \ + CreateQwordField (RBUF, RB ## Index._MAX, MA ## Index) \ + CreateQwordField (RBUF, RB ## Index._LEN, LE ## Index) \ + Store (Base, MI ## Index) \ + Store (Length, LE ## Index) \ + Add (MI ## Index, LE ## Index - 1, MA ## Index) + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2) +{ + Scope (\_SB_) + { + include ("pep.asl") + + Device (CPU0) + { + Name (_HID, "ACPI0007") + Name (_UID, 0x0) + Method (_STA) + { + Return (0xf) + } + } + + Device (CPU1) + { + Name (_HID, "ACPI0007") + Name (_UID, 0x1) + Method (_STA) + { + Return (0xf) + } + } + + Device (CPU2) + { + Name (_HID, "ACPI0007") + Name (_UID, 0x2) + Method (_STA) + { + Return (0xf) + } + } + + Device (CPU3) + { + Name (_HID, "ACPI0007") + Name (_UID, 0x3) + Method (_STA) + { + Return (0xf) + } + } + + // + // GPU device container describes the DMA translation required + // when a device behind the GPU wants to access Arm memory. + // Only the first GB can be addressed. + // + Device (GDV0) + { + Name (_HID, "ACPI0004") + Name (_UID, 0x1) + Name (_CCA, 0x0) + + Method (_CRS, 0, Serialized) { + // + // Container devices with _DMA must have _CRS, meaning GDV0 + // to provide all resources that GpuDevs.asl consume (except + // interrupts). + // + Name (RBUF, ResourceTemplate () { + QWORDMEMORYBUF(01) + QWORDMEMORYBUF(02) + QWORDMEMORYBUF(03) + // QWORDMEMORYBUF(04) + // QWORDMEMORYBUF(05) + QWORDMEMORYBUF(06) + QWORDMEMORYBUF(07) + QWORDMEMORYBUF(08) + QWORDMEMORYBUF(09) + QWORDMEMORYBUF(10) + QWORDMEMORYBUF(11) + QWORDMEMORYBUF(12) + QWORDMEMORYBUF(13) + QWORDMEMORYBUF(14) + QWORDMEMORYBUF(15) + // QWORDMEMORYBUF(16) + QWORDMEMORYBUF(17) + QWORDMEMORYBUF(18) + QWORDMEMORYBUF(19) + QWORDMEMORYBUF(20) + QWORDMEMORYBUF(21) + QWORDMEMORYBUF(22) + QWORDMEMORYBUF(23) + QWORDMEMORYBUF(24) + QWORDMEMORYBUF(25) + }) + + // USB + QWORDMEMORYSET(01, BCM2836_USB_OFFSET, BCM2836_USB_LENGTH) + + // GPU + QWORDMEMORYSET(02, BCM2836_V3D_BUS_OFFSET, BCM2836_V3D_BUS_LENGTH) + QWORDMEMORYSET(03, BCM2836_HVS_OFFSET, BCM2836_HVS_LENGTH) + // QWORDMEMORYSET(04, BCM2836_PV0_OFFSET, BCM2836_PV0_LENGTH) + // QWORDMEMORYSET(05, BCM2836_PV1_OFFSET, BCM2836_PV1_LENGTH) + QWORDMEMORYSET(06, BCM2836_PV2_OFFSET, BCM2836_PV2_LENGTH) + QWORDMEMORYSET(07, BCM2836_HDMI0_OFFSET, BCM2836_HDMI0_LENGTH) + QWORDMEMORYSET(08, BCM2836_HDMI1_OFFSET, BCM2836_HDMI1_LENGTH) + + // Mailbox + QWORDMEMORYSET(09, BCM2836_MBOX_OFFSET, BCM2836_MBOX_LENGTH) + + // VCHIQ + QWORDMEMORYSET(10, BCM2836_VCHIQ_OFFSET, BCM2836_VCHIQ_LENGTH) + + // GPIO + QWORDMEMORYSET(11, GPIO_OFFSET, GPIO_LENGTH) + + // I2C + QWORDMEMORYSET(12, BCM2836_I2C1_OFFSET, BCM2836_I2C1_LENGTH) + QWORDMEMORYSET(13, BCM2836_I2C2_OFFSET, BCM2836_I2C2_LENGTH) + + // SPI + QWORDMEMORYSET(14, BCM2836_SPI0_OFFSET, BCM2836_SPI0_LENGTH) + QWORDMEMORYSET(15, BCM2836_SPI1_OFFSET, BCM2836_SPI1_LENGTH) + // QWORDMEMORYSET(16, BCM2836_SPI2_OFFSET, BCM2836_SPI2_LENGTH) + + // PWM + QWORDMEMORYSET(17, BCM2836_PWM_DMA_OFFSET, BCM2836_PWM_DMA_LENGTH) + QWORDMEMORYSET(18, BCM2836_PWM_CTRL_OFFSET, BCM2836_PWM_CTRL_LENGTH) + QWORDBUSMEMORYSET(19, BCM2836_PWM_BUS_BASE_ADDRESS, BCM2836_PWM_BUS_LENGTH) + QWORDBUSMEMORYSET(20, BCM2836_PWM_CTRL_UNCACHED_BASE_ADDRESS, BCM2836_PWM_CTRL_UNCACHED_LENGTH) + QWORDMEMORYSET(21, BCM2836_PWM_CLK_OFFSET, BCM2836_PWM_CLK_LENGTH) + + // UART + QWORDMEMORYSET(22, BCM2836_PL011_UART_OFFSET, BCM2836_PL011_UART_LENGTH) + QWORDMEMORYSET(23, BCM2836_MINI_UART_OFFSET, BCM2836_MINI_UART_LENGTH) + + // SDC + QWORDMEMORYSET(24, MMCHS1_OFFSET, MMCHS1_LENGTH) + QWORDMEMORYSET(25, SDHOST_OFFSET, SDHOST_LENGTH) + + Return (RBUF) + } + + Name (_DMA, ResourceTemplate() { + // + // Only the first GB is available. + // Bus 0xC0000000 -> CPU 0x00000000. + // + QWordMemory (ResourceProducer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + 0x00000000C0000000, // MIN + 0x00000000FFFFFFFF, // MAX + 0xFFFFFFFF40000000, // TRA + 0x0000000040000000, // LEN + , + , + ) + }) +#include "gpudevs.asl" + } + + Device (ETH0) + { + Name (_HID, "BCM6E4E") + Name (_CID, "BCM6E4E") + Name (_UID, 0x0) + Name (_CCA, 0x0) + Method (_STA) + { + Return (0xf) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "brcm,max-dma-burst-size", 0x08 }, + Package () { "phy-mode", "rgmii-rxid" }, + } + }) + } + + // Define a simple thermal zone. The idea here is we compute the SOC temp + // via a register we can read, and give it to the OS. This enables basic + // reports from the "sensors" utility, and the OS can then poll and take + // actions if that temp exceeds any of the given thresholds. + Device (EC00) + { + Name (_HID, EISAID ("PNP0C06")) + Name (_CCA, 0x0) + + // all temps in are tenths of K (aka 2732 is the min temps in Linux (aka 0C)) + ThermalZone (TZ00) { + Method (_TMP, 0, Serialized) { + OperationRegion (TEMS, SystemMemory, THERM_SENSOR, 0x8) + Field (TEMS, DWordAcc, NoLock, Preserve) { + TMPS, 32 + } + return (((410040 - ((TMPS & 0x3ff) * 487)) / 100) + 2732); + } + Method (_SCP, 3) { } // receive cooling policy from OS + + Method (_CRT) { Return (3632) } // (90C) Critical temp point (immediate power-off) + Method (_HOT) { Return (3582) } // (85C) HOT state where OS should hibernate + Method (_PSV) { Return (3532) } // (80C) Passive cooling (CPU throttling) trip point + + // SSDT inserts _AC0/_AL0 @60C here, if a FAN is configured + + Name (_TZP, 10) //The OSPM must poll this device every 1 seconds + Name (_PSL, Package () { \_SB_.CPU0, \_SB_.CPU1, \_SB_.CPU2, \_SB_.CPU3 }) + } + } + +#include "uart.asl" +#include "rhpx.asl" +#include "sdhc.asl" + + } +} diff --git a/board/raspberrypi/rpi/emmc.asl b/board/raspberrypi/rpi/emmc.asl new file mode 100644 index 00000000000..900612cbcfa --- /dev/null +++ b/board/raspberrypi/rpi/emmc.asl @@ -0,0 +1,166 @@ +/** @file + * + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include + +#include "acpitables.h" + +DefinitionBlock (__FILE__, "SSDT", 2, "RPIFDN", "RPI4EMMC", 2) +{ + Scope (\_SB_) + { +#if (RPI_MODEL == 4) + Device (GDV1) { + Name (_HID, "ACPI0004") + Name (_UID, 0x2) + Name (_CCA, 0x0) + + Name (RBUF, ResourceTemplate () + { + MEMORY32FIXED (ReadWrite, 0, MMCHS2_LENGTH, RMEM) + }) + Method (_CRS, 0x0, Serialized) + { + MEMORY32SETBASE (RBUF, RMEM, RBAS, MMCHS2_OFFSET) + Return (^RBUF) + } + + // Translated DMA region for BCM2711 silicon revisions older than C0 + Name (DMTR, ResourceTemplate() { + QWordMemory (ResourceProducer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + 0x00000000C0000000, // MIN + 0x00000000FFFFFFFF, // MAX + 0xFFFFFFFF40000000, // TRA + 0x0000000040000000, // LEN + , + , + ) + }) + + // Non translated DMA region for BCM2711 revisions C0 and newer + Name (DMNT, ResourceTemplate() { + QWordMemory (ResourceProducer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + 0x0000000000000000, // MIN + 0x000000FFFFFFFFFF, // MAX + 0x0000000000000000, // TRA + 0x0000010000000000, // LEN + , + , + ) + }) + + Method (_DMA, 0x0, Serialized) + { + OperationRegion (CHPR, SystemMemory, ID_CHIPREV, 0x4) + Field (CHPR, DWordAcc, NoLock, Preserve) { + SOCI, 32 + } + + if ((SOCI & 0xFF) >= 0x20) + { + return (^DMNT); + } + else + { + return (^DMTR); + } + } + + // emmc2 Host Controller. (brcm,bcm2711-emmc2) + Device (SDC3) + { + Name (_HID, "BRCME88C") + Name (_UID, 0x1) + Name (_CCA, 0x0) + Name (_S1D, 0x1) + Name (_S2D, 0x1) + Name (_S3D, 0x1) + Name (_S4D, 0x1) + Name (SDMA, 0x2) + Method (_STA) + { + Return(0xf) + } + Name (RBUF, ResourceTemplate () + { + MEMORY32FIXED (ReadWrite, 0, MMCHS2_LENGTH, RMEM) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_MMCHS1_INTERRUPT } + }) + Method (_CRS, 0x0, Serialized) + { + MEMORY32SETBASE (RBUF, RMEM, RBAS, MMCHS2_OFFSET) + Return (^RBUF) + } + + // Unfortunately this controller doesn't honor the + // standard SDHCI voltage control registers + // (or at least Linux's standard code can't + // lower the voltage) So, UHS mode is disabled with caps + Name (DSD1, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "sdhci-caps-mask", 0x0000000500080000 }, + } + }) + // Along with disabling UHS, here both SDMA and ADMA2 + // are also disabled until the linux _DMA() mask/translate + // works properly. + Name (DSD2, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "sdhci-caps-mask", 0x0000000504480000 }, + } + }) + Method (_DSD, 0x0, Serialized) + { + // Select one of the sdhci-caps-mask definitions + // depending on whether we also want to disable DMA + if (SDMA == 0) + { + return (^DSD2) + } + else + { + return (^DSD1) + } + } + + // + // A child device that represents the + // sd card, which is marked as non-removable. + // + Device (SDMM) + { + Method (_ADR) + { + Return (0) + } + Method (_RMV) // Is removable + { + Return (0) // 0 - fixed + } + } + } //SDC3 + } //GDV1 +#endif + } //\SB +} diff --git a/board/raspberrypi/rpi/fadt.aslc b/board/raspberrypi/rpi/fadt.aslc new file mode 100644 index 00000000000..aae47bcce41 --- /dev/null +++ b/board/raspberrypi/rpi/fadt.aslc @@ -0,0 +1,96 @@ +/** @file + * + * Fixed ACPI Description Table (FADT) + * + * Copyright (c) 2019, Pete Batard + * Copyright (c) 2018, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include + +#include "AcpiTables.h" + +/* + * Windows 10 on the Raspberry Pi 3 requires a specific OEM Id for FADT. + * We replace the one that was defined in "AcpiTables.h", so that it is + * picked by the ACPI_HEADER () macro. + */ +#if (RPI_MODEL == 3) +#undef EFI_ACPI_OEM_ID +#define EFI_ACPI_OEM_ID {'B','C','2','8','3','6'} +#endif + +EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { + ACPI_HEADER ( + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_6_3_PM_PROFILE_APPLIANCE_PC, // UINT8 PreferredPmProfile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + EFI_ACPI_RESERVED_WORD, // UINT16 IaPcBootArch (Reserved on ARM) + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1 + EFI_ACPI_6_3_WBINVD | EFI_ACPI_6_3_SLP_BUTTON | // UINT32 Flags + EFI_ACPI_6_3_HW_REDUCED_ACPI, + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_6_3_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepStatusReg +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/board/raspberrypi/rpi/gpudevs.asl b/board/raspberrypi/rpi/gpudevs.asl new file mode 100644 index 00000000000..e6b4fcc3aad --- /dev/null +++ b/board/raspberrypi/rpi/gpudevs.asl @@ -0,0 +1,393 @@ +/** @file + * + * [DSDT] Devices behind the GPU. + * + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +// DWC OTG Controller +Device (USB0) +{ + Name (_HID, "BCM2848") +#if (RPI_MODEL == 3) + Name (_CID, "DWC_OTG") +#elif (RPI_MODEL == 4) + Name (_CID, "BCM2848") +#endif + Name (_UID, 0x0) + Name (_CCA, 0x0) + Method (_STA) + { + Return (0xf) + } + Name (RBUF, ResourceTemplate () + { + MEMORY32FIXED (ReadWrite, 0, BCM2836_USB_LENGTH, RMEM) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_USB_INTERRUPT } + }) + Method (_CRS, 0x0, Serialized) + { + MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_USB_OFFSET) + Return (^RBUF) + } +} + +// Video Core 4 GPU +Device (GPU0) +{ + Name (_HID, "BCM2850") + Name (_CID, "BCM2850") + Name (_UID, 0x0) + Name (_CCA, 0x0) + Method (_STA) + { + Return (0xf) + } + Name (RBUF, ResourceTemplate () + { + // Memory and interrupt for the GPU + MEMORY32FIXED (ReadWrite, 0, BCM2836_V3D_BUS_LENGTH, RM01) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_V3D_BUS_INTERRUPT } + + // HVS - Hardware Video Scalar + MEMORY32FIXED (ReadWrite, 0, BCM2836_HVS_LENGTH, RM02) + // The HVS interrupt is reserved by the VPU + // Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_HVS_INTERRUPT } + + // PixelValve0 - DSI0 or DPI + // MEMORY32FIXED (ReadWrite, BCM2836_PV0_BASE_ADDRESS, BCM2836_PV0_LENGTH, RM03) + // Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_PV0_INTERRUPT } + + // PixelValve1 - DS1 or SMI + // MEMORY32FIXED (ReadWrite, BCM2836_PV1_BASE_ADDRESS, BCM2836_PV1_LENGTH, RM04) + // Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_PV1_INTERRUPT } + + // PixelValve2 - HDMI output - connected to HVS display FIFO 1 + MEMORY32FIXED (ReadWrite, 0, BCM2836_PV2_LENGTH, RM05) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_PV2_INTERRUPT } + + // HDMI registers + MEMORY32FIXED (ReadWrite, 0, BCM2836_HDMI0_LENGTH, RM06) + MEMORY32FIXED (ReadWrite, 0, BCM2836_HDMI1_LENGTH, RM07) + // hdmi_int[0] + // Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_HDMI0_INTERRUPT } + // hdmi_int[1] + // Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_HDMI1_INTERRUPT } + + // HDMI DDC connection + I2CSerialBus (0x50,, 100000,, "\\_SB.GDV0.I2C2",,,,) // EDID + I2CSerialBus (0x30,, 100000,, "\\_SB.GDV0.I2C2",,,,) // E-DDC Segment Pointer + }) + Method (_CRS, 0x0, Serialized) + { + MEMORY32SETBASE (RBUF, RM01, RB01, BCM2836_V3D_BUS_OFFSET) + MEMORY32SETBASE (RBUF, RM02, RB02, BCM2836_HVS_OFFSET) + MEMORY32SETBASE (RBUF, RM05, RB05, BCM2836_PV2_OFFSET) + MEMORY32SETBASE (RBUF, RM06, RB06, BCM2836_HDMI0_OFFSET) + MEMORY32SETBASE (RBUF, RM07, RB07, BCM2836_HDMI1_OFFSET) + Return (^RBUF) + } + + // GPU Power Management Component Data + // Reference : https://github.com/Microsoft/graphics-driver-samples/wiki/Install-Driver-in-a-Windows-VM + Method (PMCD, 0, Serialized) + { + Name (RBUF, Package () + { + 1, // Version + 1, // Number of graphics power components + Package () // Power components package + { + Package () // GPU component package + { + 0, // Component Index + 0, // DXGK_POWER_COMPONENT_MAPPING.ComponentType (0 = DXGK_POWER_COMPONENT_ENGINE) + 0, // DXGK_POWER_COMPONENT_MAPPING.NodeIndex + + Buffer () // DXGK_POWER_RUNTIME_COMPONENT.ComponentGuid + { // 9B2D1E26-1575-4747-8FC0-B9EB4BAA2D2B + 0x26, 0x1E, 0x2D, 0x9B, 0x75, 0x15, 0x47, 0x47, + 0x8f, 0xc0, 0xb9, 0xeb, 0x4b, 0xaa, 0x2d, 0x2b + }, + + "VC4_Engine_00",// DXGK_POWER_RUNTIME_COMPONENT.ComponentName + 2, // DXGK_POWER_RUNTIME_COMPONENT.StateCount + + Package () // DXGK_POWER_RUNTIME_COMPONENT.States[] package + { + Package () // F0 + { + 0, // DXGK_POWER_RUNTIME_STATE.TransitionLatency + 0, // DXGK_POWER_RUNTIME_STATE.ResidencyRequirement + 1210000, // DXGK_POWER_RUNTIME_STATE.NominalPower (microwatt) + }, + + Package () // F1 - Placeholder + { + 10000, // DXGK_POWER_RUNTIME_STATE.TransitionLatency + 10000, // DXGK_POWER_RUNTIME_STATE.ResidencyRequirement + 4, // DXGK_POWER_RUNTIME_STATE.NominalPower + }, + } + } + } + }) + Return (RBUF) + } +} + +// PiQ Mailbox Driver +Device (RPIQ) +{ + Name (_HID, "BCM2849") + Name (_CID, "BCM2849") + Name (_UID, 0) + Name (_CCA, 0x0) + Method (_STA) + { + Return (0xf) + } + Name (RBUF, ResourceTemplate () + { + MEMORY32FIXED (ReadWrite, 0, BCM2836_MBOX_LENGTH, RMEM) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_MBOX_INTERRUPT } + }) + + Method (_CRS, 0x0, Serialized) + { + MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_MBOX_OFFSET) + Return (^RBUF) + } +} + +// VCHIQ Driver +Device (VCIQ) +{ + Name (_HID, "BCM2835") + Name (_CID, "BCM2835") + Name (_UID, 0) + Name (_CCA, 0x0) + Name (_DEP, Package() { \_SB.GDV0.RPIQ }) + Method (_STA) + { + Return (0xf) + } + Name (RBUF, ResourceTemplate () + { + MEMORY32FIXED (ReadWrite, 0, BCM2836_VCHIQ_LENGTH, RMEM) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_VCHIQ_INTERRUPT } + }) + + Method (_CRS, 0x0, Serialized) + { + MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_VCHIQ_OFFSET) + Return (^RBUF) + } +} + +// VC Shared Memory Driver +Device (VCSM) +{ + Name (_HID, "BCM2856") + Name (_CID, "BCM2856") + Name (_UID, 0) + Name (_CCA, 0x0) + Name (_DEP, Package() { \_SB.GDV0.VCIQ }) + Method (_STA) + { + Return (0xf) + } +} + +// Description: GPIO +Device (GPI0) +{ + Name (_HID, "BCM2845") + Name (_CID, "BCM2845") + Name (_UID, 0x0) + Name (_CCA, 0x0) + Method (_STA) + { + Return(0xf) + } + Name (RBUF, ResourceTemplate () + { + MEMORY32FIXED (ReadWrite, 0, GPIO_LENGTH, RMEM) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) + { + BCM2386_GPIO_INTERRUPT0, BCM2386_GPIO_INTERRUPT1, + BCM2386_GPIO_INTERRUPT2, BCM2386_GPIO_INTERRUPT3 + } + }) + Method (_CRS, 0x0, Serialized) + { + MEMORY32SETBASE (RBUF, RMEM, RBAS, GPIO_OFFSET) + Return (^RBUF) + } +} + +// Description: I2C +Device (I2C1) +{ + Name (_HID, "BCM2841") + Name (_CID, "BCM2841") + Name (_UID, 0x1) + Name (_CCA, 0x0) + Method (_STA) + { + Return(0xf) + } + Name (RBUF, ResourceTemplate () + { + MEMORY32FIXED (ReadWrite, 0, BCM2836_I2C1_LENGTH, RMEM) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_I2C1_INTERRUPT } + PinFunction (Exclusive, PullUp, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 2, 3 } + }) + Method (_CRS, 0x0, Serialized) + { + MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_I2C1_OFFSET) + Return (^RBUF) + } +} + +// I2C2 is the HDMI DDC connection +Device (I2C2) +{ + Name (_HID, "BCM2841") + Name (_CID, "BCM2841") + Name (_UID, 0x2) + Name (_CCA, 0x0) + Method (_STA) + { + Return (0xf) + } + Name (RBUF, ResourceTemplate() + { + MEMORY32FIXED (ReadWrite, 0, BCM2836_I2C2_LENGTH, RMEM) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_I2C2_INTERRUPT } + }) + + Method (_CRS, 0x0, Serialized) + { + MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_I2C2_OFFSET) + Return (^RBUF) + } +} + +// SPI +Device (SPI0) +{ + Name (_HID, "BCM2838") + Name (_CID, "BCM2838") + Name (_UID, 0x0) + Name (_CCA, 0x0) + Method (_STA) + { + Return (0xf) + } + Name (RBUF, ResourceTemplate () + { + MEMORY32FIXED (ReadWrite, 0, BCM2836_SPI0_LENGTH, RMEM) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_SPI0_INTERRUPT } + PinFunction (Exclusive, PullDown, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 9, 10, 11 } // MISO, MOSI, SCLK + PinFunction (Exclusive, PullUp, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 8 } // CE0 + PinFunction (Exclusive, PullUp, BCM_ALT0, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 7 } // CE1 + }) + + Method (_CRS, 0x0, Serialized) + { + MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_SPI0_OFFSET) + Return (^RBUF) + } +} + +Device (SPI1) +{ + Name (_HID, "BCM2839") + Name (_CID, "BCM2839") + Name (_UID, 0x1) + Name (_CCA, 0x0) + Name (_DEP, Package() { \_SB.GDV0.RPIQ }) + Method (_STA) + { + Return (0xf) + } + Name (RBUF, ResourceTemplate () + { + MEMORY32FIXED (ReadWrite, 0, BCM2836_SPI1_LENGTH, RMEM) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared,) { BCM2836_SPI1_INTERRUPT } + PinFunction (Exclusive, PullDown, BCM_ALT4, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 19, 20, 21 } // MISO, MOSI, SCLK + PinFunction (Exclusive, PullDown, BCM_ALT4, "\\_SB.GDV0.GPI0", 0, ResourceConsumer, , ) { 16 } // CE2 + }) + + Method (_CRS, 0x0, Serialized) + { + MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_SPI1_OFFSET) + Return (^RBUF) + } +} + +// SPI2 has no pins on GPIO header +// Device (SPI2) +// { +// Name (_HID, "BCM2839") +// Name (_CID, "BCM2839") +// Name (_UID, 0x2) +// Name (_CCA, 0x0) +// Name (_DEP, Package() { \_SB.GDV0.RPIQ }) +// Method (_STA) +// { +// Return (0xf) // Disabled +// } +// Method (_CRS, 0x0, Serialized) +// { +// Name (RBUF, ResourceTemplate () +// { +// MEMORY32FIXED (ReadWrite, BCM2836_SPI2_BASE_ADDRESS, BCM2836_SPI2_LENGTH, RMEM) +// Interrupt (ResourceConsumer, Level, ActiveHigh, Shared,) { BCM2836_SPI2_INTERRUPT } +// }) +// Return (RBUF) +// } +// } + +// PWM Driver +Device (PWM0) +{ + Name (_HID, "BCM2844") + Name (_CID, "BCM2844") + Name (_UID, 0) + Name (_CCA, 0x0) + Method (_STA) + { + Return (0xf) + } + Name (RBUF, ResourceTemplate () + { + // DMA channel 11 control + MEMORY32FIXED (ReadWrite, 0, BCM2836_PWM_DMA_LENGTH, RM01) + // PWM control + MEMORY32FIXED (ReadWrite, 0, BCM2836_PWM_CTRL_LENGTH, RM02) + // PWM control bus + MEMORY32FIXED (ReadWrite, BCM2836_PWM_BUS_BASE_ADDRESS, BCM2836_PWM_BUS_LENGTH, ) + // PWM control uncached + MEMORY32FIXED (ReadWrite, BCM2836_PWM_CTRL_UNCACHED_BASE_ADDRESS, BCM2836_PWM_CTRL_UNCACHED_LENGTH, ) + // PWM clock control + MEMORY32FIXED (ReadWrite, 0, BCM2836_PWM_CLK_LENGTH, RM03) + // Interrupt DMA channel 11 + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_DMA_INTERRUPT } + // DMA channel 11, DREQ 5 for PWM + FixedDMA (5, 11, Width32Bit, ) + }) + + Method (_CRS, 0x0, Serialized) + { + MEMORY32SETBASE (RBUF, RM01, RB01, BCM2836_PWM_DMA_OFFSET) + MEMORY32SETBASE (RBUF, RM02, RB02, BCM2836_PWM_CTRL_OFFSET) + MEMORY32SETBASE (RBUF, RM03, RB03, BCM2836_PWM_CLK_OFFSET) + Return (^RBUF) + } +} \ No newline at end of file diff --git a/board/raspberrypi/rpi/gtdt.aslc b/board/raspberrypi/rpi/gtdt.aslc new file mode 100644 index 00000000000..13181b5b716 --- /dev/null +++ b/board/raspberrypi/rpi/gtdt.aslc @@ -0,0 +1,55 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include + +#include "AcpiTables.h" + +#define RPI_GTDT_GLOBAL_FLAGS 0 +#define RPI_GTDT_GTIMER_FLAGS EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY + +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; +} EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLES; + +#pragma pack () + +EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { + { + ACPI_HEADER( + EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLES, + EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + RPI_SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV + RPI_GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV + RPI_GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV + RPI_GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV + RPI_GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress + 0, // UINT32 PlatformTimerCount + 0 // UINT32 PlatfromTimerOffset + }, +}; + +// +// Reference the table being generated to prevent the optimizer +// from removing the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Gtdt; diff --git a/board/raspberrypi/rpi/iort.aslc b/board/raspberrypi/rpi/iort.aslc new file mode 100644 index 00000000000..86c16a25596 --- /dev/null +++ b/board/raspberrypi/rpi/iort.aslc @@ -0,0 +1,100 @@ +/** @file + + Copyright (c) 2020, Arm, Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "AcpiTables.h" + +#pragma pack(1) + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE Node; + CONST CHAR8 Name[16]; +} RPI4_NC_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; + RPI4_NC_NODE NamedCompNode; + RPI4_NC_NODE NamedCompNode2; + RPI4_NC_NODE NamedCompNode3; +} RPI4_IO_REMAPPING_STRUCTURE; + +STATIC RPI4_IO_REMAPPING_STRUCTURE Iort = { + { + ACPI_HEADER (EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, + RPI4_IO_REMAPPING_STRUCTURE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION), + 3, // NumNodes + sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset + 0 // Reserved + }, { + // XHCI named component node + { + { + EFI_ACPI_IORT_TYPE_NAMED_COMP, // Type + sizeof (RPI4_NC_NODE), // Length + 0x0, // Revision + 0x0, // Reserved + 0x0, // NumIdMappings + 0x0, // IdReference + }, + 0x0, // Flags + 0x0, // CacheCoherent + 0x0, // AllocationHints + 0x0, // Reserved + 0x0, // MemoryAccessFlags + 31, // AddressSizeLimit + }, { + "\\_SB_.SCB0.XHC0" // ObjectName + } + }, { + // gpu/dwc usb named component node + { + { + EFI_ACPI_IORT_TYPE_NAMED_COMP, // Type + sizeof (RPI4_NC_NODE), // Length + 0x0, // Revision + 0x0, // Reserved + 0x0, // NumIdMappings + 0x0, // IdReference + }, + 0x0, // Flags + 0x0, // CacheCoherent + 0x0, // AllocationHints + 0x0, // Reserved + 0x0, // MemoryAccessFlags + 30, // AddressSizeLimit + }, { + "\\_SB_.GDV0.USB0" // ObjectName + } + }, { + // emmc2 named component node + { + { + EFI_ACPI_IORT_TYPE_NAMED_COMP, // Type + sizeof (RPI4_NC_NODE), // Length + 0x0, // Revision + 0x0, // Reserved + 0x0, // NumIdMappings + 0x0, // IdReference + }, + 0x0, // Flags + 0x0, // CacheCoherent + 0x0, // AllocationHints + 0x0, // Reserved + 0x0, // MemoryAccessFlags + 30, // AddressSizeLimit + }, { + "\\_SB_.GDV1.SDC3" // ObjectName + } + } +}; + +#pragma pack() + +VOID* CONST ReferenceAcpiTable = &Iort; diff --git a/board/raspberrypi/rpi/madt.aslc b/board/raspberrypi/rpi/madt.aslc new file mode 100644 index 00000000000..cfdebab759c --- /dev/null +++ b/board/raspberrypi/rpi/madt.aslc @@ -0,0 +1,78 @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2016 Linaro Ltd. All rights reserved. +* Copyright (c) 2012 - 2015, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include + +#include "AcpiTables.h" + +// +// Multiple APIC Description Table +// +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_3_GIC_STRUCTURE GicInterfaces[4]; +#if (RPI_MODEL != 3) + EFI_ACPI_6_3_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; +#endif +} PI_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +PI_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + { + ACPI_HEADER ( + EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + PI_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // + // MADT specific fields + // + 0, // LocalApicAddress + 0, // Flags + }, + { + EFI_ACPI_6_3_GICC_STRUCTURE_INIT ( + 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, FixedPcdGet32 (PcdGicPmuIrq0), + FixedPcdGet64 (PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInterruptInterfaceVBase), + // + // Use 1 for GICR Base Address below, since Windows 10 on Raspberry Pi 3 does not + // boot otherwise, and this is the value that Microsoft had in their IoT blobs. + // Kept to 1 for GICv2-based Pi 4, since this field only matters for GICv3. + // + FixedPcdGet64 (PcdGicInterruptInterfaceHBase), FixedPcdGet32 (PcdGicGsivId), 0, 1, 0), + EFI_ACPI_6_3_GICC_STRUCTURE_INIT ( + 1, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, FixedPcdGet32 (PcdGicPmuIrq1), + FixedPcdGet64 (PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInterruptInterfaceVBase), + FixedPcdGet64 (PcdGicInterruptInterfaceHBase), FixedPcdGet32 (PcdGicGsivId), 0, 1, 0), + EFI_ACPI_6_3_GICC_STRUCTURE_INIT ( + 2, 2, GET_MPID(0, 2), EFI_ACPI_6_0_GIC_ENABLED, FixedPcdGet32 (PcdGicPmuIrq2), + FixedPcdGet64 (PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInterruptInterfaceVBase), + FixedPcdGet64 (PcdGicInterruptInterfaceHBase), FixedPcdGet32 (PcdGicGsivId), 0, 1, 0), + EFI_ACPI_6_3_GICC_STRUCTURE_INIT ( + 3, 3, GET_MPID(0, 3), EFI_ACPI_6_0_GIC_ENABLED, FixedPcdGet32 (PcdGicPmuIrq3), + FixedPcdGet64 (PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInterruptInterfaceVBase), + FixedPcdGet64 (PcdGicInterruptInterfaceHBase), FixedPcdGet32 (PcdGicGsivId), 0, 1, 0), + }, +#if (RPI_MODEL != 3) + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT (0, FixedPcdGet64 (PcdGicDistributorBase), 0, 2) +#endif +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/board/raspberrypi/rpi/pci.asl b/board/raspberrypi/rpi/pci.asl new file mode 100644 index 00000000000..19eb62a2043 --- /dev/null +++ b/board/raspberrypi/rpi/pci.asl @@ -0,0 +1,168 @@ +/** @file + * + * Copyright (c) 2019 Linaro, Limited. All rights reserved. + * Copyright (c) 2021 Arm + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include + +#include "acpitables.h" + +/* + * The following can be used to remove parenthesis from + * defined macros that the compiler complains about. + */ +#define ISOLATE_ARGS(...) __VA_ARGS__ +#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x + +#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW) +#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN) +#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN) + +DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2) +{ + Scope (\_SB_) + { + Device(PCI0) + { + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge + Name(_SEG, Zero) // PCI Segment Group number + Name(_BBN, Zero) // PCI Base Bus Number + Name(_CCA, 0) // Mark the PCI noncoherent + + // PCIe can only DMA to first 3GB with early SOC's + // But we keep the restriction on the later ones + // To avoid DMA translation problems. + Name (_DMA, ResourceTemplate() { + QWordMemory (ResourceProducer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + 0x0, // MIN + 0xbfffffff, // MAX + 0x0, // TRA + 0xc0000000, // LEN + , + , + ) + }) + + // PCI Routing Table + Name(_PRT, Package() { + Package (4) { 0x0000FFFF, 0, zero, 175 }, + Package (4) { 0x0000FFFF, 1, zero, 176 }, + Package (4) { 0x0000FFFF, 2, zero, 177 }, + Package (4) { 0x0000FFFF, 3, zero, 178 } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "linux-ecam-quirk-id", "bcm2711" }, + } + }) + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + + // bus numbers assigned to this root + WordBusNumber ( + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + // 32-bit mmio window in 64-bit addr + QWordMemory ( + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + NonCacheable, ReadWrite, // cacheable + 0x00000000, // Granularity + 0, // SANITIZED_PCIE_PCI_MMIO_BEGIN + 1, // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE_PCI_MMIO_BEGIN + SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW + 2 // SANITIZED_PCIE_MMIO_LEN + 1 + ,,,MMI1 + ) + + // root port registers, not to be used if SMCCC is utilized + QWordMemory ( + ResourceConsumer, , + MinFixed, MaxFixed, + NonCacheable, ReadWrite, // cacheable + 0x00000000, // Granularity + 0xFD500000, // Root port begin + 0xFD509FFF, // Root port end + 0x00000000, // no translation + 0x0000A000, // size + ,, + ) + }) // end Name(RBUF) + + // Work around ASL's inability to add in a resource definition + // or for that matter compute the min,max,len properly + CreateQwordField (RBUF, MMI1._MIN, MMIB) + CreateQwordField (RBUF, MMI1._MAX, MMIE) + CreateQwordField (RBUF, MMI1._TRA, MMIT) + CreateQwordField (RBUF, MMI1._LEN, MMIL) + Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB) + Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE) + Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT) + Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL) + + Return (RBUF) + } // end Method(_CRS) + + // OS Control Handoff + Name(SUPP, Zero) // PCI _OSC Support Field value + Name(CTRL, Zero) // PCI _OSC Control Field value + + // See [1] 6.2.10, [2] 4.5 + Method(_OSC,4) { + // Note, This code is very similar to the code in the PCIe firmware + // specification which can be used as a reference + // Check for proper UUID + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + // Mask out Native HotPlug + And(CTRL,0x1E,CTRL) + // Always allow native PME, AER (no dependencies) + // Never allow SHPC (no SHPC controller in this system) + And(CTRL,0x1D,CTRL) + + If(LNotEqual(Arg1,One)) { // Unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // Update DWORD3 in the buffer + Store(CTRL,CDW3) + Return(Arg3) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } + } // End _OSC + } // PCI0 + } //end scope sb +} //end definition block diff --git a/board/raspberrypi/rpi/pep.asl b/board/raspberrypi/rpi/pep.asl new file mode 100644 index 00000000000..87469e2e5a9 --- /dev/null +++ b/board/raspberrypi/rpi/pep.asl @@ -0,0 +1,90 @@ +/** @file + * + * Platform Extension Plugin (PEP). + * + * Copyright (c) 2019, ARM Ltd. All rights reserved. + * Copyright (c) 2018, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +Device(PEPD) +{ + // + // PEP virtual device. + // + Name (_HID, "BCM2854") // Note: Since PEP on RPi is a virtual device, + Name (_CID, "BCM2854") // its device id needs to be generated by Microsoft + Name (_UID, 0x0) + Name (_CRS, ResourceTemplate () + { + // No hardware resources for PEP driver are needed. + }) + + // + // Processor info. PEP proprietary method to return + // PEP_PROCESSOR_TABLE_PLAT structure. + // + // See Pep.h and Pep.c. + // + Name (_GPI, Buffer() + { + 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x5F, 0x00, 0x53, + 0x00, 0x42, 0x00, 0x2E, 0x00, 0x43, 0x00, 0x50, 0x00, 0x55, 0x00, 0x30, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + + // + // Coordinated state info. PEP proprietary method to return + // PEP_COORDINATED_STATE_TABLE_PLAT structure. + // + // See Pep.h and Pep.c. + // + Name (_GCI, Buffer() + { + 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 + }) + + // + // Device info. PEP proprietary method to return + // PEP_DEVICE_TABLE_PLAT structure. + // + // See Pep.h and Pep.c. + // + Name (_GDI, Buffer() + { + 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x5F, 0x00, 0x53, + 0x00, 0x42, 0x00, 0x2E, 0x00, 0x49, 0x00, 0x32, 0x00, 0x43, 0x00, 0x30, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) +} diff --git a/board/raspberrypi/rpi/pep.c b/board/raspberrypi/rpi/pep.c new file mode 100644 index 00000000000..50d22e13190 --- /dev/null +++ b/board/raspberrypi/rpi/pep.c @@ -0,0 +1,79 @@ +/** @file + * + * PEP device tables + * + * Copyright (c) 2019, ARM Ltd. All rights reserved. + * Copyright (c) 2018, Andrei Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "Pep.h" + +PEP_PROCESSOR_TABLE_PLAT RpiProcessors = { + 1, // Version + 1, // NumberProcessors + { // ProcessorInfo + { // [0] + L"\\_SB.CPU0", // DevicePath, wchar_t[16] + 0, // FeedbackCounterCount + 0x00000000, // Flags + 0, // NumberIdleStates + 0, // NumberPerfStates + { // IdleInfo + }, + { // perfinfo + } + } + } +}; + +PEP_COORDINATED_STATE_TABLE_PLAT RpiCoordinatedStates = { + 1, // Version + 1, // CoordinatedStateCount + { // CordinatedStates[] + { // [0] + { // DependencyInfo + { // [0] + 1, // ExpectedState + 0, // TargetProcessor + 0x0 | 0x2 | 0x4, // LooseDependency = FALSE, InitialState = TRUE, DependentState = TRUE + } + }, + SOC_STATE_TYPE, // StateType + 0x1, // Flags + 0, // Latency + 0, // BreakEvenDuration + 1, // DependencyCount + 1, // MaximumDependencySize + } + } +}; + +PEP_DEVICE_TABLE_PLAT RpiDevices = { + 1, // Version + 1, // NumberDevices + { // DeviceInfo + { // [1] + L"\\_SB.I2C0", // DevicePath, wchar_t[16] + 0x1 | (1 << 3), // DStateSupportMask (D0 and D3) + 1, // NumberCompoenents + { // DStateRequirement + { // [0] + PowerDeviceD3 // DState + } + }, + { // FStateRequirement + { // [0] + { // FState + { // [0] + 0 + } + } + } + } + } + } +}; diff --git a/board/raspberrypi/rpi/pep.h b/board/raspberrypi/rpi/pep.h new file mode 100644 index 00000000000..c7be3109e6e --- /dev/null +++ b/board/raspberrypi/rpi/pep.h @@ -0,0 +1,121 @@ +/** @file + * + * PEP device defines + * + * Copyright (c) 2019, ARM Ltd. All rights reserved. + * Copyright (c) 2018, Andrei Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +/* + * Note: Not everything is here. At least SOC_STATE_TYPE is missing. + */ + +#ifndef _RPI_PEP_H_INCLUDED_ +#define _RPI_PEP_H_INCLUDED_ + +#include + +#define PEP_MAX_DEPENDENCIES_PER_STATE 16 +#define MAX_PROCESSOR_PATH_LENGTH 16 +#define MAX_DEVICE_PATH_LENGTH 32 +#define MAX_COMPONENT_COUNT 8 +#define P_NUMBER_PROCESSORS 1 +#define P_NUMBER_IDLE_STATES 1 +#define P_NUMBER_PERF_STATES 0 +#define P_NUMBER_DEVICES 1 +#define P_NUMBER_COORDINATED_STATS 1 + +typedef struct _PEP_PROCESSOR_IDLE_STATE_INFO { + UINT32 Ulong; + UINT32 Latency; + UINT32 BreakEvenDuration; +} PEP_PROCESSOR_IDLE_STATE_INFO, *PEP_PROCESSOR_IDLE_STATE_INFO; + +typedef struct _PEP_PROCESSOR_IDLE_INFO_PLAT { + // + // Processor idle states. + // + PEP_PROCESSOR_IDLE_STATE_INFO IdleStates[P_NUMBER_IDLE_STATES]; +} PEP_PROCESSOR_IDLE_INFO_PLAT, *PPEP_PROCESSOR_IDLE_INFO_PLAT; + +typedef struct COORDINATED_DEPENDENCY_INFO { + UINT32 ExpectedState; + UINT32 TargetProcessor; + UINT32 Ulong; +} COORDINATED_DEPENDENCY_INFO, *PCOORDINATED_DEPENDENCY_INFO; + +typedef struct { + COORDINATED_DEPENDENCY_INFO DependencyInfo[PEP_MAX_DEPENDENCIES_PER_STATE]; + UINT32 StateType; + UINT32 Ulong; + UINT32 Latency; + UINT32 BreakEvenDuration; + UINT32 DependencyCount; + UINT32 MaximumDependencySize; +} COORDINATED_STATE_INFO; + +typedef struct { + UINT32 Unused; +} PEP_PROCESSOR_PERF_INFO; + +typedef struct { + UINT32 FState[MAX_COMPONENT_COUNT]; +} COORDINATED_FSTATE_REQUIREMENT; + +typedef struct { + UINT32 DState; +} COORDINATED_DSTATE_REQUIREMENT; + +// +// Top level device table +// *N.B. The exact length of the structure is determined by the NumberIdleStates/NumberPerfStates variables. +// + +typedef struct _PEP_PROCESSOR_INFO_PLAT { + WCHAR DevicePath[MAX_PROCESSOR_PATH_LENGTH]; // Null-terminated ACPI name + ULONG FeedbackCounterCount; + ULONG Flags; + + // + // We are putting the idle/perf state count here (instead + // of the PEP_PROCESSOR_xxx_INFO structure for the ease of parsing. + // + ULONG NumberIdleStates; + ULONG NumberPerfStates; + + PEP_PROCESSOR_IDLE_INFO_PLAT IdleInfo; + PEP_PROCESSOR_PERF_INFO PerfInfo; +} PEP_PROCESSOR_INFO_PLAT, *PPEP_PROCESSOR_INFO_PLAT; + +typedef struct _PEP_PROCESSOR_TABLE_PLAT { + UINT32 Version; + UINT32 NumberProcessors; + PEP_PROCESSOR_INFO_PLAT ProcessorInfo[P_NUMBER_PROCESSORS]; +} PEP_PROCESSOR_TABLE_PLAT; + +typedef struct _PEP_COORDINATED_STATE_TABLE_PLAT { + ULONG Version; + ULONG CoordinatedStateCount; + COORDINATED_STATE_INFO CoordinatedStates[P_NUMBER_COORDINATED_STATS]; +} PEP_COORDINATED_STATE_TABLE_PLAT, *PPEP_COORDINATED_STATE_TABLE_PLAT; + +typedef struct _PEP_DEVICE_INFO_PLAT { + WCHAR DevicePath[MAX_DEVICE_PATH_LENGTH]; // Null-terminated ACPI name + ULONG DStateSupportMask; + ULONG NumberComponents; + + COORDINATED_DSTATE_REQUIREMENT DStateRequirement[P_NUMBER_COORDINATED_STATS]; + COORDINATED_FSTATE_REQUIREMENT FStateRequirement[P_NUMBER_COORDINATED_STATS]; +} PEP_DEVICE_INFO_PLAT, *PPEP_DEVICE_INFO_PLAT; + +typedef struct _PEP_DEVICE_TABLE_PLAT { + ULONG Version; + ULONG NumberDevices; + PEP_DEVICE_INFO_PLAT DeviceInfo[P_NUMBER_DEVICES]; +} PEP_DEVICE_TABLE_PLAT, *PPEP_DEVICE_TABLE_PLAT; + +#endif // _RPI_PEP_H_INCLUDED_ diff --git a/board/raspberrypi/rpi/pptt.aslc b/board/raspberrypi/rpi/pptt.aslc new file mode 100644 index 00000000000..9769a5b25e0 --- /dev/null +++ b/board/raspberrypi/rpi/pptt.aslc @@ -0,0 +1,191 @@ +/** @file + * + * Processor Properties Topology Table (PPTT) + * + * Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include + +#include "AcpiTables.h" + +#define NUM_CORES 4 +#define NUM_CLUSTERS 1 + +#if (RPI_MODEL == 3) +#define CORTEX_L1D_SIZE SIZE_16KB +#define CORTEX_L1D_SETS 64 +#define CORTEX_L1D_ASSC 4 +#define CORTEX_L1I_SIZE SIZE_16KB +#define CORTEX_L1I_SETS 128 +#define CORTEX_L1I_ASSC 2 +#define CORTEX_L2_SIZE SIZE_512KB +#define CORTEX_L2_SETS 512 +#define CORTEX_L2_ASSC 16 +#elif (RPI_MODEL == 4) +#define CORTEX_L1D_SIZE SIZE_32KB +#define CORTEX_L1D_SETS 256 +#define CORTEX_L1D_ASSC 2 +#define CORTEX_L1I_SIZE (3*SIZE_16KB) +#define CORTEX_L1I_SETS 256 +#define CORTEX_L1I_ASSC 3 +#define CORTEX_L2_SIZE SIZE_1MB +#define CORTEX_L2_SETS 1024 +#define CORTEX_L2_ASSC 16 +#endif + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 Offset[2]; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache; +} ACPI_6_3_PPTT_CORE; + +typedef struct { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 Offset[1]; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache; + ACPI_6_3_PPTT_CORE Cores[NUM_CORES]; +} ACPI_6_3_PPTT_CLUSTER; + +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt; + ACPI_6_3_PPTT_CLUSTER Packages[NUM_CLUSTERS]; +} ACPI_6_3_PPTT_STRUCTURE; +#pragma pack() + +#define PPTT_CORE(pid, cid, id) { \ + { \ + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \ + FIELD_OFFSET (ACPI_6_3_PPTT_CORE, DCache), \ + {}, \ + { \ + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* Not PhysicalPackage */ \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */ \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \ + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */ \ + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* identical ignored */ \ + }, \ + FIELD_OFFSET (ACPI_6_3_PPTT_STRUCTURE, \ + Packages[pid]), /* Parent */ \ + 256 * (cid) + (id), /* AcpiProcessorId */ \ + 2, /* NumberOfPrivateResources */ \ + }, { \ + FIELD_OFFSET (ACPI_6_3_PPTT_STRUCTURE, \ + Packages[pid].Cores[id].DCache), \ + FIELD_OFFSET (ACPI_6_3_PPTT_STRUCTURE, \ + Packages[pid].Cores[id].ICache), \ + }, { \ + EFI_ACPI_6_3_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 1, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 1, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + CORTEX_L1D_SIZE, /* Size */ \ + CORTEX_L1D_SETS, /* NumberOfSets */ \ + CORTEX_L1D_ASSC, /* Associativity */ \ + { \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ + }, \ + 64 /* LineSize */ \ + }, { \ + EFI_ACPI_6_3_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 1, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 0, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + CORTEX_L1I_SIZE, /* Size */ \ + CORTEX_L1I_SETS, /* NumberOfSets */ \ + CORTEX_L1I_ASSC, /* Associativity */ \ + { \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, /* AllocationType */ \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \ + 0, /* WritePolicy */ \ + }, \ + 64 /* LineSize */ \ + } \ +} + +#define PPTT_CLUSTER(pid, cid) { \ + { \ + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \ + FIELD_OFFSET (ACPI_6_3_PPTT_CLUSTER, L2Cache), \ + {}, \ + { \ + EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */ \ + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \ + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \ + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* not Leaf */ \ + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* identical cores */ \ + }, \ + 0, /* Parent */ \ + 0, /* AcpiProcessorId */ \ + 1, /* NumberOfPrivateResources */ \ + }, { \ + FIELD_OFFSET (ACPI_6_3_PPTT_STRUCTURE, Packages[pid].L2Cache), \ + }, { \ + EFI_ACPI_6_3_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 1, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 1, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + CORTEX_L2_SIZE, /* Size */ \ + CORTEX_L2_SETS, /* NumberOfSets */ \ + CORTEX_L2_ASSC, /* Associativity */ \ + { \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \ + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ + }, \ + 64 /* LineSize */ \ + }, { \ + PPTT_CORE(pid, cid, 0), \ + PPTT_CORE(pid, cid, 1), \ + PPTT_CORE(pid, cid, 2), \ + PPTT_CORE(pid, cid, 3), \ + } \ +} + +ACPI_6_3_PPTT_STRUCTURE Pptt = { + { + ACPI_HEADER(EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + ACPI_6_3_PPTT_STRUCTURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION), + }, { + PPTT_CLUSTER (0, 0), + } +}; + +VOID * CONST ReferenceAcpiTable = &Pptt; diff --git a/board/raspberrypi/rpi/rhpx.asl b/board/raspberrypi/rpi/rhpx.asl new file mode 100644 index 00000000000..214b55c6564 --- /dev/null +++ b/board/raspberrypi/rpi/rhpx.asl @@ -0,0 +1,195 @@ +/** @file + * + * [DSDT] RHProxy device to enable WinRT API (RHPX) + * + * Copyright (c) 2018, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +Device (RHPX) +{ + Name (_HID, "MSFT8000") + Name (_CID, "MSFT8000") + Name (_UID, 1) + + Name(_CRS, ResourceTemplate () + { + // Index 0 + SPISerialBus ( // SCKL - GPIO 11 - Pin 23 + // MOSI - GPIO 10 - Pin 19 + // MISO - GPIO 9 - Pin 21 + // CE0 - GPIO 8 - Pin 24 + 0, // Device selection (CE0) + PolarityLow, // Device selection polarity + FourWireMode, // WireMode + 8, // DataBit len + ControllerInitiated, // Slave mode + 4000000, // Connection speed + ClockPolarityLow, // Clock polarity + ClockPhaseFirst, // Clock phase + "\\_SB.GDV0.SPI0", // ResourceSource: SPI bus controller name + 0, // ResourceSourceIndex + // Resource usage + // DescriptorName: creates name for offset of resource descriptor + ) // Vendor Data + + // Index 1 + SPISerialBus ( // SCKL - GPIO 11 - Pin 23 + // MOSI - GPIO 10 - Pin 19 + // MISO - GPIO 9 - Pin 21 + // CE1 - GPIO 7 - Pin 26 + 1, // Device selection (CE1) + PolarityLow, // Device selection polarity + FourWireMode, // WireMode + 8, // DataBit len + ControllerInitiated, // Slave mode + 4000000, // Connection speed + ClockPolarityLow, // Clock polarity + ClockPhaseFirst, // Clock phase + "\\_SB.GDV0.SPI0", // ResourceSource: SPI bus controller name + 0, // ResourceSourceIndex + // Resource usage + // DescriptorName: creates name for offset of resource descriptor + ) // Vendor Data + + // Index 2 + I2CSerialBus ( // Pin 3 (GPIO2, SDA1), 5 (GPIO3, SCL1) + 0xFFFF, // SlaveAddress: placeholder + , // SlaveMode: default to ControllerInitiated + 0, // ConnectionSpeed: placeholder + , // Addressing Mode: default to 7 bit + "\\_SB.GDV0.I2C1", // ResourceSource: I2C bus controller name + , + , + , // Descriptor Name: creates name for offset of resource descriptor + ) // Vendor Data + + // Index 3 + SPISerialBus ( // SPI1_SCLK - GPIO21 + // SPI1_MOSI - GPIO20 + // SPI1_MISO - GPIO19 + // SPI1_CE2_N - GPIO16 + 2, // Device selection (CE2) + PolarityLow, // Device selection polarity + FourWireMode, // WireMode + 8, // DataBit len + ControllerInitiated, // Slave mode + 4000000, // Connection speed + ClockPolarityLow, // Clock polarity + ClockPhaseFirst, // Clock phase + "\\_SB.GDV0.SPI1", // ResourceSource: SPI bus controller name + 0, // ResourceSourceIndex + // Resource usage + // DescriptorName: creates name for offset of resource descriptor + ) // Vendor Data + + // GPIO 2 + GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 2 } + GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 2 } + // GPIO 3 + GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 3 } + GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 3 } + // GPIO 4 + GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 4 } + GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 4 } + // GPIO 5 + GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 5 } + GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 5 } + // GPIO 6 + GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 6 } + GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 6 } + // GPIO 7 + GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 7 } + GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 7 } + // GPIO 8 + GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 8 } + GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GDV0.GPI0",) { 8 } + // GPIO 9 + GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 9 } + GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 9 } + // GPIO 10 + GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 10 } + GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 10 } + // GPIO 11 + GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 11 } + GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 11 } + // GPIO 12 + GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 12 } + GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 12 } + // GPIO 13 + GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 13 } + GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 13 } + // NTRAID#MSFT-7141401-2016/04/7-jordanrh - disable UART muxing + // until a proper solution can be created for the dmap conflict + // GPIO 14 - UART TX + // GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 14 } + // GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 14 } + // GPIO 15 - UART RX + // GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 15 } + // GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 15 } + // GPIO 16 + GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 16 } + GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 16 } + // GPIO 17 + GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 17 } + GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 17 } + // GPIO 18 + GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 18 } + GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 18 } + // GPIO 19 + GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 19 } + GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 19 } + // GPIO 20 + GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 20 } + GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 20 } + // GPIO 21 + GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 21 } + GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 21 } + // GPIO 22 + GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 22 } + GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 22 } + // GPIO 23 + GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 23 } + GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 23 } + // GPIO 24 + GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 24 } + GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 24 } + // GPIO 25 + GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 25 } + GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 25 } + // GPIO 26 + GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 26 } + GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 26 } + // GPIO 27 + GpioIO (Shared, PullDown, 0, 0, IoRestrictionNone, "\\_SB.GDV0.GPI0", 0, ResourceConsumer,,) { 27 } + GpioInt (Edge, ActiveBoth, Shared, PullDown, 0, "\\_SB.GDV0.GPI0",) { 27 } + }) + + Name (_DSD, Package() + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + // Reference http://www.raspberrypi.org/documentation/hardware/raspberrypi/spi/README.md + // SPI 0 + Package (2) { "bus-SPI-SPI0", Package() { 0, 1 } }, // Index 0 & 1 + Package (2) { "SPI0-MinClockInHz", 7629 }, // 7629 Hz + Package (2) { "SPI0-MaxClockInHz", 125000000 }, // 125 MHz + Package (2) { "SPI0-SupportedDataBitLengths", Package() { 8 } }, // Data Bit Length + // I2C1 + Package (2) { "bus-I2C-I2C1", Package() { 2 } }, + // GPIO Pin Count and supported drive modes + Package (2) { "GPIO-PinCount", 54 }, + Package (2) { "GPIO-UseDescriptorPinNumbers", 1 }, + Package (2) { "GPIO-SupportedDriveModes", 0xf }, // InputHighImpedance, InputPullUp, InputPullDown, OutputCmos + // SPI 1 + Package (2) { "bus-SPI-SPI1", Package() { 3 }}, // Index 3 + Package (2) { "SPI1-MinClockInHz", 30511 }, // 30.5 kHz + Package (2) { "SPI1-MaxClockInHz", 20000000 }, // 20 MHz + Package (2) { "SPI1-SupportedDataBitLengths", Package() { 8 } }, // Data Bit Length + } + }) +} diff --git a/board/raspberrypi/rpi/rpi4.dsc b/board/raspberrypi/rpi/rpi4.dsc new file mode 100644 index 00000000000..5694cf0973e --- /dev/null +++ b/board/raspberrypi/rpi/rpi4.dsc @@ -0,0 +1,790 @@ +# @file +# +# Copyright (c) 2011 - 2020, ARM Limited. All rights reserved. +# Copyright (c) 2017 - 2018, Andrei Warkentin +# Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved. +# Copyright (c) 2014, Linaro Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = RPi4 + PLATFORM_GUID = a7eca3b4-21b0-4989-8c18-c08f3ae87837 + PLATFORM_VERSION = 1.0 + DSC_SPECIFICATION = 0x0001001A + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/RaspberryPi/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf + + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=VALUE + # + DEFINE SECURE_BOOT_ENABLE = FALSE + DEFINE INCLUDE_TFTP_COMMAND = FALSE + DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x8000004F + +!ifndef TFA_BUILD_ARTIFACTS + # + # Default TF-A binary checked into edk2-non-osi. + # + DEFINE TFA_BUILD_BL31 = Platform/RaspberryPi/$(PLATFORM_NAME)/TrustedFirmware/bl31.bin +!else + # + # Usually we use the checked-in binaries, but for developers working + # on the firmware, being able to use a local TF-A build without extra copy + # operations ends up being very helpful. + # + DEFINE TFA_BUILD_BL31 = $(TFA_BUILD_ARTIFACTS)/bl31.bin +!endif + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +!include MdePkg/MdeLibs.dsc.inc + +[LibraryClasses.common] +!if $(TARGET) == RELEASE + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf + BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf + + # + # Ramdisk Requirements + # + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + + # Allow dynamic PCDs + # + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + + # use the accelerated BaseMemoryLibOptDxe by default, overrides for SEC/PEI below + BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf + + # + # It is not possible to prevent the ARM compiler from inserting calls to intrinsic functions. + # This library provides the instrinsic functions such a compiler may generate calls to. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + # Add support for GCC stack protector + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + + # ARM Architectural Libraries + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf + + # Dual serial port library + PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartClockLib.inf + PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf + SerialPortLib|Platform/RaspberryPi/Library/DualSerialPortLib/DebugDualSerialPortLib.inf + + # Cryptographic libraries + RngLib|MdePkg/Library/DxeRngLib/DxeRngLib.inf + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf + + # + # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window + # in the debugger will show load and unload commands for symbols. You can cut and paste this + # into the command window to load symbols. We should be able to use a script to do this, but + # the version of RVD I have does not support scripts accessing system memory. + # + #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf + #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf + + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf + DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf + + # Flattened Device Tree (FDT) access library + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + + # USB Libraries + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + + # + # Secure Boot dependencies + # +!if $(SECURE_BOOT_ENABLE) == TRUE + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf + SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf + SecureBootVariableProvisionLib|SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisionLib.inf + + # re-use the UserPhysicalPresent() dummy implementation from the ovmf tree + PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf +!endif + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf + GpioLib|Silicon/Broadcom/Bcm283x/Library/GpioLib/GpioLib.inf + + # + # PCI dependencies + # + # PCI root port configuation and description + PciHostBridgeLib|Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLib.inf + # The "segment lib" provides the CAM accessors/etc when they aren't ECAM standard + PciSegmentLib|Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.inf + +[LibraryClasses.common.SEC] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + MemoryInitPeiLib|Platform/RaspberryPi/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf + +[LibraryClasses.common.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf + +[LibraryClasses.common.DXE_DRIVER] + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +!if $(INCLUDE_TFTP_COMMAND) == TRUE + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf +!endif + +[LibraryClasses.common.UEFI_APPLICATION] + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + # Runtime debug messages may crash an OS unless serial output to MMIO mapped UARTs is inhibited + DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + EfiResetSystemLib|Platform/RaspberryPi/Library/ResetLib/ResetLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRuntimeDxe.inf + +!if $(SECURE_BOOT_ENABLE) == TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif + +################################################################################################### +# BuildOptions Section - Define the module specific tool chain flags that should be used as +# the default flags for a module. These flags are appended to any +# standard flags that are defined by the build process. +################################################################################################### + +[BuildOptions] + GCC:*_*_*_CC_FLAGS = -DRPI_MODEL=4 + GCC:*_*_*_PP_FLAGS = -DRPI_MODEL=4 + GCC:*_*_*_ASLPP_FLAGS = -DRPI_MODEL=4 + GCC:*_*_*_ASLCC_FLAGS = -DRPI_MODEL=4 + GCC:*_*_*_VFRPP_FLAGS = -DRPI_MODEL=4 + GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -DNDEBUG + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE + + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport|FALSE + +[PcdsFixedAtBuild.common] + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + + # DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PRINT_ENABLED 0x02 + # DEBUG_CODE_ENABLED 0x04 + # CLEAR_MEMORY_ENABLED 0x08 + # ASSERT_BREAKPOINT_ENABLED 0x10 + # ASSERT_DEADLOOP_ENABLED 0x20 +!if $(TARGET) == RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f +!endif + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free (pool) + # DEBUG_PAGE 0x00000020 // Alloc & Free (page) + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNP Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // LoadFile + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may + # // significantly impact boot performance + # DEBUG_ERROR 0x80000000 // Error + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEVEL) + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + + # + # Optional feature to help prevent EFI memory map fragments + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob + # Values are in EFI Pages (4K). DXE Core will make sure that + # at least this much of each type of memory can be allocated + # from a single memory range. This way you only end up with + # maximum of two fragments for each type in the memory map + # (the memory used, and the free memory that was prereserved + # but not used). + # + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 +!if $(SECURE_BOOT_ENABLE) == TRUE + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|600 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1500 +!else + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|300 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|150 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1000 +!endif + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|12000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + gEmbeddedTokenSpaceGuid.PcdDmaDeviceOffset|0xc0000000 + gEmbeddedTokenSpaceGuid.PcdDmaDeviceLimit|0xffffffff + + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"EDK2-DEV" + +!if $(SECURE_BOOT_ENABLE) == TRUE + # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04 +!endif + + gEfiNetworkPkgTokenSpaceGuid.PcdAllowHttpConnections|TRUE + + # Default platform supported RFC 4646 languages: (American) English + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US" + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmPlatformLib|Platform/RaspberryPi/Library/PlatformLib/PlatformLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + PlatformBootManagerLib|Platform/RaspberryPi/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + +[PcdsFixedAtBuild.common] + gArmPlatformTokenSpaceGuid.PcdCoreCount|4 + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 + + # Size of the region used by UEFI in permanent memory (Reserved 64MB) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000 + # + # 0x00000000 - 0x001F0000 FD (PcdFdBaseAddress, PcdFdSize) + # 0x001F0000 - 0x00200000 DTB (PcdFdtBaseAddress, PcdFdtSize) + # 0x00200000 - ... RAM (PcdSystemMemoryBase, PcdSystemMemorySize) + # + # This matches PcdFvBaseAddress, since everything less is the FD, and + # will be reserved away. + # + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00200000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x3fe00000 + + # + # Device specific addresses + # + gBcm27xxTokenSpaceGuid.PcdBcm27xxRegistersAddress|0xfc000000 + gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress|0xfd580000 + gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress|0xfe000000 + + # PCIe specific addresses + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase|0xfd500000 + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr|0xf8000000 + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen|0x3ffffff + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr|0x600000000 + + # UARTs + gArmPlatformTokenSpaceGuid.PL011UartInteger|0 + gArmPlatformTokenSpaceGuid.PL011UartFractional|0 + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|48000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x27 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 + + # + # ARM General Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0xFF841000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFF842000 + gRaspberryPiTokenSpaceGuid.PcdGicInterruptInterfaceHBase|0xFF844000 + gRaspberryPiTokenSpaceGuid.PcdGicInterruptInterfaceVBase|0xFF846000 + gRaspberryPiTokenSpaceGuid.PcdGicGsivId|0x19 + gRaspberryPiTokenSpaceGuid.PcdGicPmuIrq0|0x30 + gRaspberryPiTokenSpaceGuid.PcdGicPmuIrq1|0x31 + gRaspberryPiTokenSpaceGuid.PcdGicPmuIrq2|0x32 + gRaspberryPiTokenSpaceGuid.PcdGicPmuIrq3|0x33 + + # + # Fixed CPU settings. + # + gRaspberryPiTokenSpaceGuid.PcdCpuLowSpeedMHz|800 + gRaspberryPiTokenSpaceGuid.PcdCpuDefSpeedMHz|1500 + gRaspberryPiTokenSpaceGuid.PcdCpuMaxSpeedMHz|2200 + + ## Default Terminal Type + ## 0-PCANSI, 1-VT100, 2-VT00+, 3-UTF8, 4-TTYTERM + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 } + + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"EDK2" + gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE + +[PcdsPatchableInModule] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|500000000 + +[PcdsDynamicHii.common.DEFAULT] + + # + # Clock overrides. + # + + gRaspberryPiTokenSpaceGuid.PcdCpuClock|L"CpuClock"|gConfigDxeFormSetGuid|0x0|1 + gRaspberryPiTokenSpaceGuid.PcdCustomCpuClock|L"CustomCpuClock"|gConfigDxeFormSetGuid|0x0|gRaspberryPiTokenSpaceGuid.PcdCpuDefSpeedMHz + + # + # SD-related. + # + + gRaspberryPiTokenSpaceGuid.PcdSdIsArasan|L"SdIsArasan"|gConfigDxeFormSetGuid|0x0|0 + gRaspberryPiTokenSpaceGuid.PcdMmcForce1Bit|L"MmcForce1Bit"|gConfigDxeFormSetGuid|0x0|0 + gRaspberryPiTokenSpaceGuid.PcdMmcForceDefaultSpeed|L"MmcForceDefaultSpeed"|gConfigDxeFormSetGuid|0x0|0 + gRaspberryPiTokenSpaceGuid.PcdMmcSdDefaultSpeedMHz|L"MmcSdDefaultSpeedMHz"|gConfigDxeFormSetGuid|0x0|25 + gRaspberryPiTokenSpaceGuid.PcdMmcSdHighSpeedMHz|L"MmcSdHighSpeedMHz"|gConfigDxeFormSetGuid|0x0|50 + gRaspberryPiTokenSpaceGuid.PcdMmcDisableMulti|L"MmcDisableMulti"|gConfigDxeFormSetGuid|0x0|0 + gRaspberryPiTokenSpaceGuid.PcdMmcEnableDma|L"MmcEnableDma"|gConfigDxeFormSetGuid|0x0|1 + + # + # Debug-related. + # + + gRaspberryPiTokenSpaceGuid.PcdDebugEnableJTAG|L"DebugEnableJTAG"|gConfigDxeFormSetGuid|0x0|0 + + # + # Display-related. + # + + # + # Just enable native resolution by default. + # + gRaspberryPiTokenSpaceGuid.PcdDisplayEnableScaledVModes|L"DisplayEnableScaledVModes"|gConfigDxeFormSetGuid|0x0|0x20 + gRaspberryPiTokenSpaceGuid.PcdDisplayEnableSShot|L"DisplayEnableSShot"|gConfigDxeFormSetGuid|0x0|1 + + # + # Supporting > 3GB of memory. + # + gRaspberryPiTokenSpaceGuid.PcdRamMoreThan3GB|L"RamMoreThan3GB"|gConfigDxeFormSetGuid|0x0|0 + gRaspberryPiTokenSpaceGuid.PcdRamLimitTo3GB|L"RamLimitTo3GB"|gConfigDxeFormSetGuid|0x0|1 + + # + # Device Tree and ACPI selection. + # + # 0 - SYSTEM_TABLE_MODE_ACPI (default) + # 1 - SYSTEM_TABLE_MODE_BOTH + # 2 - SYSTEM_TABLE_MODE_DT + # + gRaspberryPiTokenSpaceGuid.PcdSystemTableMode|L"SystemTableMode"|gConfigDxeFormSetGuid|0x0|0 + + # + # Enable a fan in the ACPI thermal zone on GPIO pin # + # + # 0 - DISABLED + # 19 - Enabled on pin 19 + # + gRaspberryPiTokenSpaceGuid.PcdFanOnGpio|L"FanOnGpio"|gConfigDxeFormSetGuid|0x0|0 + gRaspberryPiTokenSpaceGuid.PcdFanTemp|L"FanTemp"|gConfigDxeFormSetGuid|0x0|60 + + # + # Reset-related. + # + + gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspberryPiTokenSpaceGuid|0x0|0 + + # Select XHCI/PCIe mode + # + # 0 - XHCI Enabled (default on !cm4) + # 1 - PCIe Enabled + # 2 - PCIe Enabled (default on cm4) + # + gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0x0|0 + + # + # Common UEFI ones. + # + + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 + # + # This is silly, but by pointing SetupConXXX and ConXXX PCDs to + # the same variables, I can use the graphical configuration to + # change the mode used by ConSplitter. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|L"Columns"|gRaspberryPiTokenSpaceGuid|0x0|80 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|L"Columns"|gRaspberryPiTokenSpaceGuid|0x0|80 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|L"Rows"|gRaspberryPiTokenSpaceGuid|0x0|25 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|L"Rows"|gRaspberryPiTokenSpaceGuid|0x0|25 + gEfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy|L"BootDiscoveryPolicy"|gBootDiscoveryPolicyMgrFormsetGuid|0 + +[PcdsDynamicDefault.common] + # + # Set video resolution for boot options and for text setup. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0 + + # + # UART in use + # This value will be synchronized with the setting in config.txt + # 0 - PL011_UART_IN_USE + # 1 - MINI_UART_IN_USE + # + gRaspberryPiTokenSpaceGuid.PcdUartInUse|0 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + # + # PEI Phase modules + # + ArmPlatformPkg/PrePi/PeiUniCore.inf { + + SerialPortLib|Platform/RaspberryPi/Library/DualSerialPortLib/DualSerialPortLib.inf + } + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + Platform/RaspberryPi/Drivers/VarBlockServiceDxe/VarBlockServiceDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + } +!if $(SECURE_BOOT_ENABLE) == TRUE + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf + } + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf + SecurityPkg/EnrollFromDefaultKeysApp/EnrollFromDefaultKeysApp.inf + SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf +!else + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!endif + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf { + + RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf + } + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf { + + SerialPortLib|Platform/RaspberryPi/Library/DualSerialPortLib/DualSerialPortDxeLib.inf + } + Platform/RaspberryPi/Drivers/DisplayDxe/DisplayDxe.inf + EmbeddedPkg/Drivers/ConsolePrefDxe/ConsolePrefDxe.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + Platform/RaspberryPi/Drivers/RpiFirmwareDxe/RpiFirmwareDxe.inf + Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.inf + Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + MdeModulePkg/Universal/EbcDxe/EbcDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + + # + # ACPI Support + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf + Platform/RaspberryPi/AcpiTables/AcpiTables.inf + + # + # SMBIOS Support + # + Platform/RaspberryPi/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + + # + # RAM Disk Support + # + MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + + # + # Bds + # + MdeModulePkg/Universal/BootManagerPolicyDxe/BootManagerPolicyDxe.inf + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + Platform/RaspberryPi/Drivers/LogoDxe/LogoDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLib.inf + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|Platform/RaspberryPi/Library/PlatformUiAppLib/PlatformUiAppLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf + } + + # + # SCSI Bus and Disk Driver + # + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + + # + # USB Support + # + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + Platform/RaspberryPi/Drivers/DwUsbHostDxe/DwUsbHostDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # SD/MMC support + # + # Platform/RaspberryPi/Drivers/SdHostDxe/SdHostDxe.inf + Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.inf + Platform/RaspberryPi/Drivers/MmcDxe/MmcDxe.inf + + # + # Networking stack + # +!include NetworkPkg/Network.dsc.inc + Silicon/Broadcom/Drivers/Net/BcmGenetDxe/BcmGenetDxe.inf { + + gEmbeddedTokenSpaceGuid.PcdDmaDeviceOffset|0x00000000 + gEmbeddedTokenSpaceGuid.PcdDmaDeviceLimit|0xffffffffff + } + + # + # RNG + # + Silicon/Broadcom/Bcm283x/Drivers/Bcm2838RngDxe/Bcm2838RngDxe.inf + + # + # PCI Support + # + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + EmbeddedPkg/Drivers/NonCoherentIoMmuDxe/NonCoherentIoMmuDxe.inf { + + gEmbeddedTokenSpaceGuid.PcdDmaDeviceOffset|0x00000000 + gEmbeddedTokenSpaceGuid.PcdDmaDeviceLimit|0xbfffffff + } + + # + # NVMe boot devices + # + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + gEfiShellPkgTokenSpaceGuid.PcdShellFileOperationSize|0x200000 + } +!if $(INCLUDE_TFTP_COMMAND) == TRUE + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + } +!endif diff --git a/board/raspberrypi/rpi/sdhc.asl b/board/raspberrypi/rpi/sdhc.asl new file mode 100644 index 00000000000..4e1f280a03e --- /dev/null +++ b/board/raspberrypi/rpi/sdhc.asl @@ -0,0 +1,119 @@ +/** @file + * + * [DSDT] SD controller/card definition (SDHC) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include + +#include "acpitables.h" + +// +// Note: UEFI can use either SDHost or Arasan. We expose both to the OS. +// + +// ArasanSD 3.0 SD Host Controller. (brcm,bcm2835-sdhci) +Device (SDC1) +{ + Name (_HID, "BCM2847") + Name (_CID, "BCM2847") + Name (_UID, 0x0) + Name (_CCA, 0x0) + Name (_S1D, 0x1) + Name (_S2D, 0x1) + Name (_S3D, 0x1) + Name (_S4D, 0x1) + Method (_STA) + { + Return(0xf) + } + Name (RBUF, ResourceTemplate () + { + MEMORY32FIXED (ReadWrite, 0, MMCHS1_LENGTH, RMEM) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_MMCHS1_INTERRUPT } + }) + Method (_CRS, 0x0, Serialized) + { + MEMORY32SETBASE (RBUF, RMEM, RBAS, MMCHS1_OFFSET) + Return (^RBUF) + } + + // The standard CAPs registers on this controller + // appear to be 0, lets set some minimal defaults + // Since this cap doesn't indicate DMA capability + // we don't need a _DMA() + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "sdhci-caps", 0x0120fa81 }, + } + }) + + // + // A child device that represents the + // sd card, which is marked as non-removable. + // + Device (SDMM) + { + Method (_ADR) + { + Return (0) + } + Method (_RMV) // Is removable + { + Return (0) // 0 - fixed + } + } +} + +#if (RPI_MODEL < 4) +// Broadcom SDHost 2.0 SD Host Controller +Device (SDC2) +{ + Name (_HID, "BCM2855") + Name (_CID, "BCM2855") + Name (_UID, 0x0) + Name (_CCA, 0x0) + Name (_S1D, 0x1) + Name (_S2D, 0x1) + Name (_S3D, 0x1) + Name (_S4D, 0x1) + Method (_STA) + { + Return (0xf) + } + Name (RBUF, ResourceTemplate () + { + MEMORY32FIXED (ReadWrite, 0, SDHOST_LENGTH, RMEM) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_SDHOST_INTERRUPT } + }) + Method (_CRS, 0x0, Serialized) + { + MEMORY32SETBASE (RBUF, RMEM, RBAS, SDHOST_OFFSET) + Return (^RBUF) + } + + // + // A child device that represents the + // sd card, which is marked as non-removable. + // + Device (SDMM) + { + Method (_ADR) + { + Return (0) + } + Method (_RMV) // Is removable + { + Return (0) // 0 - fixed + } + } +} +#endif // !RPI4 diff --git a/board/raspberrypi/rpi/spcrminiuart.aslc b/board/raspberrypi/rpi/spcrminiuart.aslc new file mode 100644 index 00000000000..4823cab2681 --- /dev/null +++ b/board/raspberrypi/rpi/spcrminiuart.aslc @@ -0,0 +1,91 @@ +/** @file +* SPCR Table +* +* Copyright (c) 2019 Pete Batard +* Copyright (c) 2014-2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include + +#include "AcpiTables.h" + +#define RPI_UART_FLOW_CONTROL_NONE 0 + +#define RPI_UART_INTERFACE_TYPE EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_BCM2835_UART +#define RPI_UART_BASE_ADDRESS BCM2836_MINI_UART_BASE_ADDRESS +#define RPI_UART_INTERRUPT BCM2836_MINI_UART_INTERRUPT + +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { + ACPI_HEADER ( + EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION + ), + // UINT8 InterfaceType; + RPI_UART_INTERFACE_TYPE, + // UINT8 Reserved1[3]; + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddress; + ARM_GAS32 (RPI_UART_BASE_ADDRESS), + // UINT8 InterruptType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, + // UINT8 Irq; + 0, // Not used on ARM + // UINT32 GlobalSystemInterrupt; + RPI_UART_INTERRUPT, + // UINT8 BaudRate; +#if (FixedPcdGet64 (PcdUartDefaultBaudRate) == 9600) + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_9600, +#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 19200) + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_19200, +#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 57600) + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_57600, +#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 115200) + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, +#else +#error Unsupported SPCR Baud Rate +#endif + // UINT8 Parity; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, + // UINT8 StopBits; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, + // UINT8 FlowControl; + RPI_UART_FLOW_CONTROL_NONE, + // UINT8 TerminalType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT_UTF8, + // UINT8 Reserved2; + EFI_ACPI_RESERVED_BYTE, + // UINT16 PciDeviceId; + 0xFFFF, + // UINT16 PciVendorId; + 0xFFFF, + // UINT8 PciBusNumber; + 0x00, + // UINT8 PciDeviceNumber; + 0x00, + // UINT8 PciFunctionNumber; + 0x00, + // UINT32 PciFlags; + 0x00000000, + // UINT8 PciSegment; + 0x00, + // UINT32 Reserved3; + EFI_ACPI_RESERVED_DWORD +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Spcr; diff --git a/board/raspberrypi/rpi/spcrpl011.aslc b/board/raspberrypi/rpi/spcrpl011.aslc new file mode 100644 index 00000000000..5a540adf083 --- /dev/null +++ b/board/raspberrypi/rpi/spcrpl011.aslc @@ -0,0 +1,91 @@ +/** @file +* SPCR Table +* +* Copyright (c) 2019 Pete Batard +* Copyright (c) 2014-2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include + +#include "AcpiTables.h" + +#define RPI_UART_FLOW_CONTROL_NONE 0 + +#define RPI_UART_INTERFACE_TYPE EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART +#define RPI_UART_BASE_ADDRESS BCM2836_PL011_UART_BASE_ADDRESS +#define RPI_UART_INTERRUPT BCM2836_PL011_UART_INTERRUPT + +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { + ACPI_HEADER ( + EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION + ), + // UINT8 InterfaceType; + RPI_UART_INTERFACE_TYPE, + // UINT8 Reserved1[3]; + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddress; + ARM_GAS32 (RPI_UART_BASE_ADDRESS), + // UINT8 InterruptType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, + // UINT8 Irq; + 0, // Not used on ARM + // UINT32 GlobalSystemInterrupt; + RPI_UART_INTERRUPT, + // UINT8 BaudRate; +#if (FixedPcdGet64 (PcdUartDefaultBaudRate) == 9600) + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_9600, +#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 19200) + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_19200, +#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 57600) + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_57600, +#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 115200) + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, +#else +#error Unsupported SPCR Baud Rate +#endif + // UINT8 Parity; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, + // UINT8 StopBits; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, + // UINT8 FlowControl; + RPI_UART_FLOW_CONTROL_NONE, + // UINT8 TerminalType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT_UTF8, + // UINT8 Reserved2; + EFI_ACPI_RESERVED_BYTE, + // UINT16 PciDeviceId; + 0xFFFF, + // UINT16 PciVendorId; + 0xFFFF, + // UINT8 PciBusNumber; + 0x00, + // UINT8 PciDeviceNumber; + 0x00, + // UINT8 PciFunctionNumber; + 0x00, + // UINT32 PciFlags; + 0x00000000, + // UINT8 PciSegment; + 0x00, + // UINT32 Reserved3; + EFI_ACPI_RESERVED_DWORD +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Spcr; diff --git a/board/raspberrypi/rpi/ssdtthermal.asl b/board/raspberrypi/rpi/ssdtthermal.asl new file mode 100644 index 00000000000..5a20ee1d9f7 --- /dev/null +++ b/board/raspberrypi/rpi/ssdtthermal.asl @@ -0,0 +1,77 @@ +/** @file + * + * Secondary System Description Table (SSDT) for active (fan) cooling + * + * Copyright (c) 2020, Arm Ltd. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include + +#include + +DefinitionBlock (__FILE__, "SSDT", 2, "RPIFDN", "RPITHFAN", 2) +{ + External (\_SB_.EC00, DeviceObj) + External (\_SB_.EC00.TZ00, DeviceObj) + + Scope (\_SB_.EC00) + { + // Define a NameOp we will modify during InstallTable + Name (GIOP, 0x2) //08 47 49 4f 50 0a 02 (value must be >1) + Name (FTMP, 0x2) + // Describe a fan + PowerResource (PFAN, 0, 0) { + OperationRegion (GPIO, SystemMemory, GPIO_BASE_ADDRESS, 0x1000) + Field (GPIO, DWordAcc, NoLock, Preserve) { + Offset (0x1C), + GPS0, 32, + GPS1, 32, + RES1, 32, + GPC0, 32, + GPC1, 32, + RES2, 32, + GPL1, 32, + GPL2, 32 + } + // We are hitting a GPIO pin to on/off a fan. + // This assumes that UEFI has programmed the + // direction as OUT. Given the current limitations + // on the GPIO pins, its recommended to use + // the GPIO to switch a larger voltage/current + // for the fan rather than driving it directly. + Method (_STA) { + if (GPL1 & (1 << GIOP)) { + Return (1) // present and enabled + } + Return (0) + } + Method (_ON) { // turn fan on + Store (1 << GIOP, GPS0) + } + Method (_OFF) { // turn fan off + Store (1 << GIOP, GPC0) + } + } + Device (FAN0) { + // Note, not currently an ACPIv4 fan + // the latter adds speed control/detection + // but in the case of linux needs FIF, FPS, FSL, and FST + Name (_HID, EISAID ("PNP0C0B")) + Name (_PR0, Package () { PFAN }) + } + } + + // merge in an active cooling point. + Scope (\_SB_.EC00.TZ00) + { + Method (_AC0) { Return ( (FTMP * 10) + 2732) } // (60C) active cooling trip point, + // if this is lower than PSV then we + // prefer active cooling + Name (_AL0, Package () { \_SB_.EC00.FAN0 }) // the fan used for AC0 above + } +} diff --git a/board/raspberrypi/rpi/uart.asl b/board/raspberrypi/rpi/uart.asl new file mode 100644 index 00000000000..9cca1a5c27d --- /dev/null +++ b/board/raspberrypi/rpi/uart.asl @@ -0,0 +1,202 @@ +/** @file + * + * [DSDT] Serial devices (UART). + * + * Copyright (c) 2021, ARM Limited. All rights reserved. + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include + +#include "acpitables.h" + +// PL011 based UART. +Device (URT0) +{ + Name (_HID, "BCM2837") + Name (_CID, "ARMH0011") + Name (_UID, 0x4) + Name (_CCA, 0x0) + Method (_STA) + { + Return (0xf) + } + Name (RBUF, ResourceTemplate () + { + MEMORY32FIXED (ReadWrite, 0, BCM2836_PL011_UART_LENGTH, RMEM) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { BCM2836_PL011_UART_INTERRUPT } + }) + Method (_CRS, 0x0, Serialized) + { + MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_PL011_UART_OFFSET) + Return (^RBUF) + } + + Name (CLCK, 48000000) + + Name (_DSD, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () + { + Package (2) { "clock-frequency", CLCK }, + } + }) +} + +// +// UART Mini. +// +// This device is referenced in the DBG2 table, which will cause the system to +// not start the driver when the debugger is enabled and to mark the device +// with problem code 53 (CM_PROB_USED_BY_DEBUGGER). +// + +Device (URTM) +{ + Name (_HID, "BCM2836") + Name (_CID, "BCM2836") + Name (_UID, 0x0) + Name (_CCA, 0x0) + Method (_STA) + { + Return (0xf) + } + Name (RBUF, ResourceTemplate () + { + MEMORY32FIXED (ReadWrite, 0, BCM2836_MINI_UART_LENGTH, RMEM) + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) { BCM2836_MINI_UART_INTERRUPT } + + }) + Method (_CRS, 0x0, Serialized) + { + MEMORY32SETBASE (RBUF, RMEM, RBAS, BCM2836_MINI_UART_OFFSET) + Return (^RBUF) + } +} + +// +// Multifunction serial bus device to support Bluetooth function. +// +Device(BTH0) +{ + Name (_HID, "BCM2EA6") + Name (_CID, "BCM2EA6") + + // + // UART In Use will be dynamically updated during boot + // 0x55 0x52 0x49 0x55 0xA 0x2 (Value must > 1) + // + Name (URIU, 0x2) + + Method (_STA) + { + Return (0xf) + } + + // + // Resource for URT0 (PL011) + // + Name (BTPL, ResourceTemplate () + { + UARTSerialBus( + 115200, // InitialBaudRate: in BPS + , // BitsPerByte: default to 8 bits + , // StopBits: Defaults to one bit + 0x00, // LinesInUse: 8 1-bit flags to + // declare enabled control lines. + // Raspberry Pi does not exposed + // HW control signals -> not supported. + // Optional bits: + // - Bit 7 (0x80) Request To Send (RTS) + // - Bit 6 (0x40) Clear To Send (CTS) + // - Bit 5 (0x20) Data Terminal Ready (DTR) + // - Bit 4 (0x10) Data Set Ready (DSR) + // - Bit 3 (0x08) Ring Indicator (RI) + // - Bit 2 (0x04) Data Carrier Detect (DTD) + // - Bit 1 (0x02) Reserved. Must be 0. + // - Bit 0 (0x01) Reserved. Must be 0. + , // IsBigEndian: + // default to LittleEndian. + , // Parity: Defaults to no parity + , // FlowControl: Defaults to + // no flow control. + 16, // ReceiveBufferSize + 16, // TransmitBufferSize + "\\_SB.GDV0.URT0", // ResourceSource: + // UART bus controller name + , // ResourceSourceIndex: assumed to be 0 + , // ResourceUsage: assumed to be + // ResourceConsumer + UAR0, // DescriptorName: creates name + // for offset of resource descriptor + ) // Vendor data + }) + + // + // Resource for URTM (miniUART) + // + Name (BTMN, ResourceTemplate () + { + // + // BT UART: ResourceSource will be dynamically updated to + // either URT0 (PL011) or URTM (miniUART) during boot + // + UARTSerialBus( + 115200, // InitialBaudRate: in BPS + , // BitsPerByte: default to 8 bits + , // StopBits: Defaults to one bit + 0x00, // LinesInUse: 8 1-bit flags to + // declare enabled control lines. + // Raspberry Pi does not exposed + // HW control signals -> not supported. + // Optional bits: + // - Bit 7 (0x80) Request To Send (RTS) + // - Bit 6 (0x40) Clear To Send (CTS) + // - Bit 5 (0x20) Data Terminal Ready (DTR) + // - Bit 4 (0x10) Data Set Ready (DSR) + // - Bit 3 (0x08) Ring Indicator (RI) + // - Bit 2 (0x04) Data Carrier Detect (DTD) + // - Bit 1 (0x02) Reserved. Must be 0. + // - Bit 0 (0x01) Reserved. Must be 0. + , // IsBigEndian: + // default to LittleEndian. + , // Parity: Defaults to no parity + , // FlowControl: Defaults to + // no flow control. + 16, // ReceiveBufferSize + 16, // TransmitBufferSize + "\\_SB.GDV0.URTM", // ResourceSource: + // UART bus controller name + , // ResourceSourceIndex: assumed to be 0 + , // ResourceUsage: assumed to be + // ResourceConsumer + UARM, // DescriptorName: creates name + // for offset of resource descriptor + ) // Vendor data + }) + + Method (_CRS, 0x0, Serialized) + { + if (URIU == 0) + { + // + // PL011 UART is configured for console output + // Return Mini UART for Bluetooth + // + return (^BTMN) + } + else + { + // + // Mini UART is configured for console output + // Return PL011 UART for Bluetooth + // + return (^BTPL) + } + } +} diff --git a/board/raspberrypi/rpi/xhci.asl b/board/raspberrypi/rpi/xhci.asl new file mode 100644 index 00000000000..d6b92da5c09 --- /dev/null +++ b/board/raspberrypi/rpi/xhci.asl @@ -0,0 +1,165 @@ +/** @file + * + * Copyright (c) 2019 Linaro, Limited. All rights reserved. + * Copyright (c) 2019 Andrei Warkentin + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include + +#include "acpitables.h" + +/* + * The following can be used to remove parenthesis from + * defined macros that the compiler complains about. + */ +#define ISOLATE_ARGS(...) __VA_ARGS__ +#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x + +#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW) +#define SANITIZED_PCIE_REG_BASE REMOVE_PARENTHESES(PCIE_REG_BASE) + +/* + * According to UEFI boot log for the VLI device on Pi 4. + */ +#define XHCI_REG_LENGTH 0x1000 + +DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4XHCI", 2) +{ + Scope (\_SB_) + { + + Device (SCB0) { + Name (_HID, "ACPI0004") + Name (_UID, 0x0) + Name (_CCA, 0x0) + + Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings + /* + * Container devices with _DMA must have _CRS, meaning SCB0 + * to provide all resources that XHC0 consumes (except + * interrupts). + */ + Name (RBUF, ResourceTemplate () { + QWordMemory (ResourceProducer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX + 0x0, + 0x1, // LEN + , + , + MMIO + ) + }) + CreateQwordField (RBUF, MMIO._MAX, MMBE) + CreateQwordField (RBUF, MMIO._LEN, MMLE) + Add (MMBE, XHCI_REG_LENGTH - 1, MMBE) + Add (MMLE, XHCI_REG_LENGTH - 1, MMLE) + Return (RBUF) + } + + Name (_DMA, ResourceTemplate() { + /* + * XHC0 is limited to DMA to first 3GB. Note this + * only applies to PCIe, not GENET or other devices + * next to the A72. + */ + QWordMemory (ResourceProducer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + 0x0, // MIN + 0xbfffffff, // MAX + 0x0, // TRA + 0xc0000000, // LEN + , + , + ) + }) + + Device (XHC0) + { + Name (_HID, "PNP0D10") // _HID: Hardware ID + Name (_UID, 0x0) // _UID: Unique ID + Name (_CCA, 0x0) // _CCA: Cache Coherency Attribute + + Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings + Name (RBUF, ResourceTemplate () { + QWordMemory (ResourceConsumer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX + 0x0, + 0x1, // LEN + , + , + MMIO + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { + 175 + } + }) + CreateQwordField (RBUF, MMIO._MAX, MMBE) + CreateQwordField (RBUF, MMIO._LEN, MMLE) + Add (MMBE, XHCI_REG_LENGTH - 1, MMBE) + Add (MMLE, XHCI_REG_LENGTH - 1, MMLE) + Return (RBUF) + } + + Method (_INI, 0, Serialized) { + OperationRegion (PCFG, SystemMemory, SANITIZED_PCIE_REG_BASE + PCIE_EXT_CFG_DATA, 0x1000) + Field (PCFG, AnyAcc, NoLock, Preserve) { + VNID, 16, // Vendor ID + DVID, 16, // Device ID + CMND, 16, // Command register + STAT, 16, // Status register + } + + // Set command register to: + // 1) decode MMIO (set bit 1) + // 2) enable DMA (set bit 2) + // 3) enable interrupts (clear bit 10) + Debug = "xHCI enable" + Store (0x6, CMND) + } + + /* + * Microsoft's USB Device-Specific Methods. See: + * https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/usb-device-specific-method---dsm- + */ + Name (DSMU, ToUUID ("ce2ee385-00e6-48cb-9f05-2edb927c4899")) + + Method (_DSM, 4, Serialized) { + If (LEqual (Arg0, DSMU)) { // USB capabilities UUID + Switch (ToInteger (Arg2)) { + Case (0) { // Function 0: List of supported functions + Return (Buffer () { 0x41 }) // 0x41 - Functions 0 and 6 supported + } + Case (6) { // Function 6: RegisterAccessType + Return (Buffer () { 0x01 }) // 0x01 - Must use 32bit register access + } + Default { } // Unsupported + } + } + return (Buffer () { 0x00 }) // Return 0x00 for anything unsupported + } + } // end XHC0 + } //end SCB0 + } //end scope sb +} //end definition block From 81efa5f368709ff0499cedf420b32eb8e13a3d96 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 1 Dec 2021 16:03:13 +0000 Subject: [PATCH 30/31] WIP: Bring in some header files from tianocore These header files presumably duplicate things already in the U-Boot devicetree. For now, bring them in to get the ASL code to build. This needs to be sorted out. Signed-off-by: Simon Glass --- .../mach-bcm283x/include/mach/acpi/bcm2711.h | 93 ++++++++ .../mach-bcm283x/include/mach/acpi/bcm2836.h | 124 +++++++++++ .../include/mach/acpi/bcm2836_gpio.h | 85 ++++++++ .../include/mach/acpi/bcm2836_gpu.h | 48 +++++ .../include/mach/acpi/bcm2836_pwm.h | 34 +++ .../include/mach/acpi/bcm2836_sdhost.h | 90 ++++++++ .../include/mach/acpi/bcm2836_sdio.h | 203 ++++++++++++++++++ 7 files changed, 677 insertions(+) create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h new file mode 100644 index 00000000000..1bfced2ea8f --- /dev/null +++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h @@ -0,0 +1,93 @@ +/** @file + * + * Copyright (c) 2019, Jeremy Linton + * Copyright (c) 2019, Pete Batard . + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef BCM2711_H__ +#define BCM2711_H__ + +#define BCM2711_SOC_REGISTERS (FixedPcdGet64 (PcdBcm27xxRegistersAddress)) +#define BCM2711_SOC_REGISTER_LENGTH 0x02000000 + +/* Generic PCI addresses */ +#define PCIE_TOP_OF_MEM_WIN (FixedPcdGet64 (PcdBcm27xxPciBusMmioAdr)) +#define PCIE_CPU_MMIO_WINDOW (FixedPcdGet64 (PcdBcm27xxPciCpuMmioAdr)) +#define PCIE_BRIDGE_MMIO_LEN (FixedPcdGet32 (PcdBcm27xxPciBusMmioLen)) + +/* PCI root bridge control registers location */ +#define PCIE_REG_BASE (FixedPcdGet32 (PcdBcm27xxPciRegBase)) +#define PCIE_REG_LIMIT 0x9310 + +/* PCI root bridge control registers */ +#define BRCM_PCIE_CAP_REGS 0x00ac /* Offset to ecam like range for root port */ +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188 +#define BRCM_PCIE_CLASS 0x043c +#define PCIE_MISC_MISC_CTRL 0x4008 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c +#define PCIE_MISC_PCIE_STATUS 0x4068 +#define PCIE_MISC_REVISION 0x406c +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 + +#define PCIE_INTR2_CPU_STATUS 0x4300 +#define PCIE_INTR2_CPU_SET 0x4304 +#define PCIE_INTR2_CPU_CLR 0x4308 +#define PCIE_INTR2_CPU_MASK_STATUS 0x430c +#define PCIE_INTR2_CPU_MASK_SET 0x4310 +#define PCIE_INTR2_CPU_MASK_CLR 0x4314 + +#define PCIE_RGR1_SW_INIT_1 0x9210 +#define PCIE_EXT_CFG_INDEX 0x9000 +/* A small window pointing at the ECAM of the device selected by CFG_INDEX */ +#define PCIE_EXT_CFG_DATA 0x8000 + +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff + +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000 +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f + +#define PCIE_RGR1_SW_INIT_1_INIT_MASK 0x2 +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 + +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 + +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 + +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_MASK_BITS 0xc + + +#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff + +#define BURST_SIZE_128 0 +#define BURST_SIZE_256 1 +#define BURST_SIZE_512 2 + +#define GENET_BASE_ADDRESS FixedPcdGet64 (PcdBcmGenetRegistersAddress) +#define GENET_LENGTH 0x00010000 + +#define THERM_SENSOR 0x7d5d2200 + +#define ID_CHIPREV 0xfc404000 + +#endif /* BCM2711_H__ */ diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h new file mode 100644 index 00000000000..db0fe0262a6 --- /dev/null +++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h @@ -0,0 +1,124 @@ +/** @file + * + * Copyright (c) 2019, ARM Limited. All rights reserved. + * Copyright (c) 2017, Andrei Warkentin + * Copyright (c) 2016, Linaro Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __BCM2836_H__ +#define __BCM2836_H__ + +/* + * Both "core" and SoC perpherals (1M each). + */ +#define BCM2836_SOC_REGISTERS (FixedPcdGet64 (PcdBcm283xRegistersAddress)) +#define BCM2836_SOC_REGISTER_LENGTH 0x02000000 + +/* + * Offset between the CPU's view and the VC's view of system memory. + */ +#define BCM2836_DMA_DEVICE_OFFSET 0xc0000000 + +/* watchdog constants */ +#define BCM2836_WDOG_OFFSET 0x00100000 +#define BCM2836_WDOG_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_WDOG_OFFSET) +#define BCM2836_WDOG_PASSWORD 0x5a000000 +#define BCM2836_WDOG_RSTC_OFFSET 0x0000001c +#define BCM2836_WDOG_WDOG_OFFSET 0x00000024 +#define BCM2836_WDOG_RSTC_WRCFG_MASK 0x00000030 +#define BCM2836_WDOG_RSTC_WRCFG_FULL_RESET 0x00000020 + +/* clock manager constants */ +#define BCM2836_CM_OFFSET 0x00101000 +#define BCM2836_CM_BASE (BCM2836_SOC_REGISTERS + BCM2836_CM_OFFSET) +#define BCM2836_CM_GEN_CLOCK_CONTROL 0x0000 +#define BCM2836_CM_GEN_CLOCK_DIVISOR 0x0004 +#define BCM2836_CM_VPU_CLOCK_CONTROL 0x0008 +#define BCM2836_CM_VPU_CLOCK_DIVISOR 0x000c +#define BCM2836_CM_SYSTEM_CLOCK_CONTROL 0x0010 +#define BCM2836_CM_SYSTEM_CLOCK_DIVISOR 0x0014 +#define BCM2836_CM_H264_CLOCK_CONTROL 0x0028 +#define BCM2836_CM_H264_CLOCK_DIVISOR 0x002c +#define BCM2836_CM_PWM_CLOCK_CONTROL 0x00a0 +#define BCM2836_CM_PWM_CLOCK_DIVISOR 0x00a4 +#define BCM2836_CM_UART_CLOCK_CONTROL 0x00f0 +#define BCM2836_CM_UART_CLOCK_DIVISOR 0x00f4 +#define BCM2836_CM_SDC_CLOCK_CONTROL 0x01a8 +#define BCM2836_CM_SDC_CLOCK_DIVISOR 0x01ac +#define BCM2836_CM_ARM_CLOCK_CONTROL 0x01b0 +#define BCM2836_CM_ARM_CLOCK_DIVISOR 0x01b4 +#define BCM2836_CM_EMMC_CLOCK_CONTROL 0x01c0 +#define BCM2836_CM_EMMC_CLOCK_DIVISOR 0x01c4 + +/* mailbox interface constants */ +#define BCM2836_MBOX_OFFSET 0x0000b880 +#define BCM2836_MBOX_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_MBOX_OFFSET) +#define BCM2836_MBOX_LENGTH 0x00000024 +#define BCM2836_MBOX_READ_OFFSET 0x00000000 +#define BCM2836_MBOX_STATUS_OFFSET 0x00000018 +#define BCM2836_MBOX_CONFIG_OFFSET 0x0000001c +#define BCM2836_MBOX_WRITE_OFFSET 0x00000020 + +#define BCM2836_MBOX_STATUS_FULL 0x1f +#define BCM2836_MBOX_STATUS_EMPTY 0x1e + +#define BCM2836_MBOX_NUM_CHANNELS 16 + +/* interrupt controller constants */ +#define BCM2836_INTC_TIMER_CONTROL_OFFSET 0x00000040 +#define BCM2836_INTC_TIMER_PENDING_OFFSET 0x00000060 + +/* usb constants */ +#define BCM2836_USB_OFFSET 0x00980000 +#define BCM2836_USB_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_USB_OFFSET) +#define BCM2836_USB_LENGTH 0x00010000 + +/* serial based protocol constants */ +#define BCM2836_PL011_UART_OFFSET 0x00201000 +#define BCM2836_PL011_UART_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PL011_UART_OFFSET) +#define BCM2836_PL011_UART_LENGTH 0x00001000 + +#define BCM2836_MINI_UART_OFFSET 0x00215000 +#define BCM2836_MINI_UART_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_MINI_UART_OFFSET) +#define BCM2836_MINI_UART_LENGTH 0x00000070 + +#define BCM2836_I2C0_OFFSET 0x00205000 +#define BCM2836_I2C0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C0_OFFSET) +#define BCM2836_I2C0_LENGTH 0x00000020 + +#define BCM2836_I2C1_OFFSET 0x00804000 +#define BCM2836_I2C1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C1_OFFSET) +#define BCM2836_I2C1_LENGTH 0x00000020 + +#define BCM2836_I2C2_OFFSET 0x00805000 +#define BCM2836_I2C2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C2_OFFSET) +#define BCM2836_I2C2_LENGTH 0x00000020 + +#define BCM2836_SPI0_OFFSET 0x00204000 +#define BCM2836_SPI0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI0_OFFSET) +#define BCM2836_SPI0_LENGTH 0x00000020 + +#define BCM2836_SPI1_OFFSET 0x00215080 +#define BCM2836_SPI1_LENGTH 0x00000040 +#define BCM2836_SPI1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI1_OFFSET) + +#define BCM2836_SPI2_OFFSET 0x002150C0 +#define BCM2836_SPI2_LENGTH 0x00000040 +#define BCM2836_SPI2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI2_OFFSET) + +/* dma constants */ +#define BCM2836_DMA0_OFFSET 0x00007000 +#define BCM2836_DMA0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA0_OFFSET) + +#define BCM2836_DMA15_OFFSET 0x00E05000 +#define BCM2836_DMA15_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA15_OFFSET) + +#define BCM2836_DMA_CTRL_OFFSET 0x00007FE0 +#define BCM2836_DMA_CTRL_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA_CTRL_OFFSET) + +#define BCM2836_DMA_CHANNEL_LENGTH 0x00000100 + +#endif /*__BCM2836_H__ */ diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h new file mode 100644 index 00000000000..a64cecaef3a --- /dev/null +++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h @@ -0,0 +1,85 @@ +/** @file + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018, Andrei Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include + +#ifndef __BCM2836_GPIO_H__ +#define __BCM2836_GPIO_H__ + +#define GPIO_OFFSET 0x00200000 +#define GPIO_BASE_ADDRESS (BCM2836_SOC_REGISTERS + GPIO_OFFSET) +#define GPIO_LENGTH 0x000000B4 + +#define GPIO_GPFSEL0 (GPIO_BASE_ADDRESS + 0x00) +#define GPIO_GPFSEL1 (GPIO_BASE_ADDRESS + 0x04) +#define GPIO_GPFSEL2 (GPIO_BASE_ADDRESS + 0x08) +#define GPIO_GPFSEL3 (GPIO_BASE_ADDRESS + 0x0C) +#define GPIO_GPFSEL4 (GPIO_BASE_ADDRESS + 0x10) +#define GPIO_GPFSEL5 (GPIO_BASE_ADDRESS + 0x14) + +#define GPIO_GPSET0 (GPIO_BASE_ADDRESS + 0x1C) +#define GPIO_GPSET1 (GPIO_BASE_ADDRESS + 0x20) + +#define GPIO_GPCLR0 (GPIO_BASE_ADDRESS + 0x28) +#define GPIO_GPCLR1 (GPIO_BASE_ADDRESS + 0x2C) + +#define GPIO_GPLEV0 (GPIO_BASE_ADDRESS + 0x34) +#define GPIO_GPLEV1 (GPIO_BASE_ADDRESS + 0x38) + +#define GPIO_GPEDS0 (GPIO_BASE_ADDRESS + 0x40) +#define GPIO_GPEDS1 (GPIO_BASE_ADDRESS + 0x44) + +#define GPIO_GPREN0 (GPIO_BASE_ADDRESS + 0x4C) +#define GPIO_GPREN1 (GPIO_BASE_ADDRESS + 0x50) + +#define GPIO_GPFEN0 (GPIO_BASE_ADDRESS + 0x58) +#define GPIO_GPFEN1 (GPIO_BASE_ADDRESS + 0x5C) + +#define GPIO_GPHEN0 (GPIO_BASE_ADDRESS + 0x64) +#define GPIO_GPHEN1 (GPIO_BASE_ADDRESS + 0x68) + +#define GPIO_GPLEN0 (GPIO_BASE_ADDRESS + 0x70) +#define GPIO_GPLEN1 (GPIO_BASE_ADDRESS + 0x74) + +#define GPIO_GPAREN0 (GPIO_BASE_ADDRESS + 0x7C) +#define GPIO_GPAREN1 (GPIO_BASE_ADDRESS + 0x80) + +#define GPIO_GPAFEN0 (GPIO_BASE_ADDRESS + 0x88) +#define GPIO_GPAFEN1 (GPIO_BASE_ADDRESS + 0x8C) + +#define GPIO_GPPUD (GPIO_BASE_ADDRESS + 0x94) +#define GPIO_GPPUDCLK0 (GPIO_BASE_ADDRESS + 0x98) +#define GPIO_GPPUDCLK1 (GPIO_BASE_ADDRESS + 0x9C) + +#define GPIO_GPPUPPDN0 (GPIO_BASE_ADDRESS + 0xE4) +#define GPIO_GPPUPPDN1 (GPIO_BASE_ADDRESS + 0xE8) +#define GPIO_GPPUPPDN2 (GPIO_BASE_ADDRESS + 0xEC) +#define GPIO_GPPUPPDN3 (GPIO_BASE_ADDRESS + 0xF0) + +#define GPIO_FSEL_INPUT 0x0 +#define GPIO_FSEL_OUTPUT 0x1 +#define GPIO_FSEL_ALT0 0x4 +#define GPIO_FSEL_ALT1 0x5 +#define GPIO_FSEL_ALT2 0x6 +#define GPIO_FSEL_ALT3 0x7 +#define GPIO_FSEL_ALT4 0x3 +#define GPIO_FSEL_ALT5 0x2 + +#define GPIO_FSEL_PINS_PER_REGISTER 10 +#define GPIO_FSEL_BITS_PER_PIN 3 +#define GPIO_FSEL_MASK ((1 << GPIO_FSEL_BITS_PER_PIN) - 1) + +#define GPIO_PINS 54 + +#define GPIO_PULL_NONE 0x00 +#define GPIO_PULL_DOWN 0x01 +#define GPIO_PULL_UP 0x02 + +#endif /* __BCM2836_GPIO_H__ */ diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h new file mode 100644 index 00000000000..49be0206d40 --- /dev/null +++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h @@ -0,0 +1,48 @@ +/** @file + * + * Copyright (c) 2020, Pete Batard + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include + +#ifndef __BCM2836_GPU_H__ +#define __BCM2836_GPU_H__ + +/* VideoCore constants */ + +#define BCM2836_VCHIQ_OFFSET 0x0000B840 +#define BCM2836_VCHIQ_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_VCHIQ_OFFSET) +#define BCM2836_VCHIQ_LENGTH 0x00000010 + +#define BCM2836_V3D_BUS_OFFSET 0x00C00000 +#define BCM2836_V3D_BUS_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_V3D_BUS_OFFSET) +#define BCM2836_V3D_BUS_LENGTH 0x00001000 + +#define BCM2836_HVS_OFFSET 0x00400000 +#define BCM2836_HVS_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HVS_OFFSET) +#define BCM2836_HVS_LENGTH 0x00006000 + +#define BCM2836_PV0_OFFSET 0x00206000 +#define BCM2836_PV0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV0_OFFSET) +#define BCM2836_PV0_LENGTH 0x00000100 + +#define BCM2836_PV1_OFFSET 0x00207000 +#define BCM2836_PV1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV1_OFFSET) +#define BCM2836_PV1_LENGTH 0x00000100 + +#define BCM2836_PV2_OFFSET 0x00807000 +#define BCM2836_PV2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV2_OFFSET) +#define BCM2836_PV2_LENGTH 0x00000100 + +#define BCM2836_HDMI0_OFFSET 0x00902000 +#define BCM2836_HDMI0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HDMI0_OFFSET) +#define BCM2836_HDMI0_LENGTH 0x00000600 + +#define BCM2836_HDMI1_OFFSET 0x00808000 +#define BCM2836_HDMI1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HDMI1_OFFSET) +#define BCM2836_HDMI1_LENGTH 0x00000100 + +#endif /* __BCM2836_MISC_H__ */ diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h new file mode 100644 index 00000000000..12050f34b17 --- /dev/null +++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h @@ -0,0 +1,34 @@ +/** @file + * + * Copyright (c) 2020, Pete Batard + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include + +#ifndef __BCM2836_PWM_H__ +#define __BCM2836_PWM_H__ + +/* PWM controller constants */ + +#define BCM2836_PWM_DMA_OFFSET 0x00007B00 +#define BCM2836_PWM_DMA_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PWM_DMA_OFFSET) +#define BCM2836_PWM_DMA_LENGTH 0x00000100 + +#define BCM2836_PWM_CLK_OFFSET 0x001010A0 +#define BCM2836_PWM_CLK_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PWM_CLK_OFFSET) +#define BCM2836_PWM_CLK_LENGTH 0x00000008 + +#define BCM2836_PWM_CTRL_OFFSET 0x0020C000 +#define BCM2836_PWM_CTRL_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PWM_CTRL_OFFSET) +#define BCM2836_PWM_CTRL_LENGTH 0x00000028 + +#define BCM2836_PWM_BUS_BASE_ADDRESS 0x7E20C000 +#define BCM2836_PWM_BUS_LENGTH 0x00000028 + +#define BCM2836_PWM_CTRL_UNCACHED_BASE_ADDRESS 0xFF20C000 +#define BCM2836_PWM_CTRL_UNCACHED_LENGTH 0x00000028 + +#endif /* __BCM2836_PWM_H__ */ diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h new file mode 100644 index 00000000000..1c62d668a48 --- /dev/null +++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h @@ -0,0 +1,90 @@ +/** @file + * + * Copyright (c) 2017, Andrei Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include + +#ifndef __BCM2836_SDHOST_H__ +#define __BCM2836_SDHOST_H__ + +#define SDHOST_OFFSET 0x00202000 +#define SDHOST_BASE_ADDRESS (BCM2836_SOC_REGISTERS + SDHOST_OFFSET) +#define SDHOST_LENGTH 0x00000100 +#define SDHOST_REG(X) (SDHOST_BASE_ADDRESS + (X)) +#define SDHOST_CMD SDHOST_REG(0x0) +#define SDHOST_ARG SDHOST_REG(0x4) +#define SDHOST_TOUT SDHOST_REG(0x8) +#define SDHOST_CDIV SDHOST_REG(0xC) +#define SDHOST_RSP0 SDHOST_REG(0x10) // [31:0] +#define SDHOST_RSP1 SDHOST_REG(0x14) // [63:32] +#define SDHOST_RSP2 SDHOST_REG(0x18) // [95:64] +#define SDHOST_RSP3 SDHOST_REG(0x1C) // [127:96] +#define SDHOST_HSTS SDHOST_REG(0x20) +#define SDHOST_VDD SDHOST_REG(0x30) +#define SDHOST_EDM SDHOST_REG(0x34) +#define SDHOST_HCFG SDHOST_REG(0x38) +#define SDHOST_HBCT SDHOST_REG(0x3C) +#define SDHOST_DATA SDHOST_REG(0x40) +#define SDHOST_HBLC SDHOST_REG(0x50) + +// +// CMD +// +#define SDHOST_CMD_READ_CMD BIT6 +#define SDHOST_CMD_WRITE_CMD BIT7 +#define SDHOST_CMD_RESPONSE_CMD_LONG_RESP BIT9 +#define SDHOST_CMD_RESPONSE_CMD_NO_RESP BIT10 +#define SDHOST_CMD_BUSY_CMD BIT11 +#define SDHOST_CMD_FAIL_FLAG BIT14 +#define SDHOST_CMD_NEW_FLAG BIT15 + +// +// VDD +// +#define SDHOST_VDD_POWER_ON BIT0 + +// +// HSTS +// +#define SDHOST_HSTS_CLEAR 0x7F8 +#define SDHOST_HSTS_BLOCK_IRPT BIT9 +#define SDHOST_HSTS_REW_TIME_OUT BIT7 +#define SDHOST_HSTS_CMD_TIME_OUT BIT6 +#define SDHOST_HSTS_CRC16_ERROR BIT5 +#define SDHOST_HSTS_CRC7_ERROR BIT4 +#define SDHOST_HSTS_FIFO_ERROR BIT3 +#define SDHOST_HSTS_DATA_FLAG BIT0 + +#define SDHOST_HSTS_TIMOUT_ERROR (SDHOST_HSTS_CMD_TIME_OUT | SDHOST_HSTS_REW_TIME_OUT) +#define SDHOST_HSTS_TRANSFER_ERROR (SDHOST_HSTS_FIFO_ERROR | SDHOST_HSTS_CRC7_ERROR | SDHOST_HSTS_CRC16_ERROR) +#define SDHOST_HSTS_ERROR (SDHOST_HSTS_TIMOUT_ERROR | SDHOST_HSTS_TRANSFER_ERROR) + +// +// HCFG +// +#define SDHOST_HCFG_SLOW_CARD BIT3 +#define SDHOST_HCFG_WIDE_EXT_BUS BIT2 +#define SDHOST_HCFG_WIDE_INT_BUS BIT1 +#define SDHOST_HCFG_DATA_IRPT_EN BIT4 +#define SDHOST_HCFG_BLOCK_IRPT_EN BIT8 +#define SDHOST_HCFG_BUSY_IRPT_EN BIT10 + +// +// EDM +// +#define SDHOST_EDM_FIFO_CLEAR BIT21 +#define SDHOST_EDM_WRITE_THRESHOLD_SHIFT 9 +#define SDHOST_EDM_READ_THRESHOLD_SHIFT 14 +#define SDHOST_EDM_THRESHOLD_MASK 0x1F +#define SDHOST_EDM_READ_THRESHOLD(X) ((X) << SDHOST_EDM_READ_THRESHOLD_SHIFT) +#define SDHOST_EDM_WRITE_THRESHOLD(X) ((X) << SDHOST_EDM_WRITE_THRESHOLD_SHIFT) + +#define CMD8_SD_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0) +#define CMD8_MMC_ARG (0) + +#endif /*__BCM2836_SDHOST_H__ */ diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h new file mode 100644 index 00000000000..aba422b9751 --- /dev/null +++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h @@ -0,0 +1,203 @@ +/** @file + * + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include + +#ifndef __BCM2836_SDIO_H__ +#define __BCM2836_SDIO_H__ + +// MMC/SD/SDIO1 register definitions. +#define MMCHS1_OFFSET 0x00300000 +#define MMCHS2_OFFSET 0x00340000 +#define MMCHS1_BASE (BCM2836_SOC_REGISTERS + MMCHS1_OFFSET) +#define MMCHS2_BASE (BCM2836_SOC_REGISTERS + MMCHS2_OFFSET) +#define MMCHS1_LENGTH 0x00000100 +#define MMCHS2_LENGTH 0x00000100 + +#define MMCHS_BLK (mMmcHsBase + 0x4) +#define BLEN_512BYTES (0x200UL << 0) + +#define MMCHS_ARG (mMmcHsBase + 0x8) + +#define MMCHS_CMD (mMmcHsBase + 0xC) +#define BCE_ENABLE BIT1 +#define DDIR_READ BIT4 +#define DDIR_WRITE (0x0UL << 4) +#define MSBS_SGLEBLK (0x0UL << 5) +#define MSBS_MULTBLK BIT5 +#define RSP_TYPE_MASK (0x3UL << 16) +#define RSP_TYPE_136BITS BIT16 +#define RSP_TYPE_48BITS (0x2UL << 16) +#define RSP_TYPE_48BUSY (0x3UL << 16) +#define CCCE_ENABLE BIT19 +#define CICE_ENABLE BIT20 +#define DP_ENABLE BIT21 + +#define CMD_TYPE_NORMAL 0 +#define CMD_TYPE_ABORT 3 +#define TYPE(CMD_TYPE) (((CMD_TYPE) & 0x3) << 22) +#define _INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24) +#define MMC_CMD_NUM(CMD) (((CMD) >> 24) & 0x3F) +#define INDX(CMD_INDX) (TYPE(CMD_TYPE_NORMAL) | _INDX(CMD_INDX)) +#define INDX_ABORT(CMD_INDX) (TYPE(CMD_TYPE_ABORT) | _INDX(CMD_INDX)) + +#define MMCHS_RSP10 (mMmcHsBase + 0x10) +#define MMCHS_RSP32 (mMmcHsBase + 0x14) +#define MMCHS_RSP54 (mMmcHsBase + 0x18) +#define MMCHS_RSP76 (mMmcHsBase + 0x1C) +#define MMCHS_DATA (mMmcHsBase + 0x20) + +#define MMCHS_PRES_STATE (mMmcHsBase + 0x24) +#define CMDI_MASK BIT0 +#define CMDI_ALLOWED (0x0UL << 0) +#define CMDI_NOT_ALLOWED BIT0 +#define DATI_MASK BIT1 +#define DATI_ALLOWED (0x0UL << 1) +#define DATI_NOT_ALLOWED BIT1 +#define WRITE_PROTECT_OFF BIT19 + +#define MMCHS_HCTL (mMmcHsBase + 0x28) +#define DTW_1_BIT (0x0UL << 1) +#define DTW_4_BIT BIT1 +#define SDBP_MASK BIT8 +#define SDBP_OFF (0x0UL << 8) +#define SDBP_ON BIT8 +#define SDVS_MASK (0x7UL << 9) +#define SDVS_1_8_V (0x5UL << 9) +#define SDVS_3_0_V (0x6UL << 9) +#define SDVS_3_3_V (0x7UL << 9) +#define IWE BIT24 + +#define MMCHS_SYSCTL (mMmcHsBase + 0x2C) +#define ICE BIT0 +#define ICS_MASK BIT1 +#define ICS BIT1 +#define CEN BIT2 +#define CLKD_MASK (0x3FFUL << 6) +#define CLKD_80KHZ (0x258UL) //(96*1000/80)/2 +#define CLKD_400KHZ (0xF0UL) +#define CLKD_12500KHZ (0x200UL) +#define DTO_MASK (0xFUL << 16) +#define DTO_VAL (0xEUL << 16) +#define SRA BIT24 +#define SRC_MASK BIT25 +#define SRC BIT25 +#define SRD BIT26 + +#define MMCHS_INT_STAT (mMmcHsBase + 0x30) +#define CC BIT0 +#define TC BIT1 +#define BWR BIT4 +#define BRR BIT5 +#define CARD_INS BIT6 +#define ERRI BIT15 +#define CTO BIT16 +#define DTO BIT20 +#define DCRC BIT21 +#define DEB BIT22 + +#define MMCHS_IE (mMmcHsBase + 0x34) +#define CC_EN BIT0 +#define TC_EN BIT1 +#define BWR_EN BIT4 +#define BRR_EN BIT5 +#define CTO_EN BIT16 +#define CCRC_EN BIT17 +#define CEB_EN BIT18 +#define CIE_EN BIT19 +#define DTO_EN BIT20 +#define DCRC_EN BIT21 +#define DEB_EN BIT22 +#define CERR_EN BIT28 +#define BADA_EN BIT29 +#define ALL_EN 0xFFFFFFFF + +#define MMCHS_ISE (mMmcHsBase + 0x38) +#define CC_SIGEN BIT0 +#define TC_SIGEN BIT1 +#define BWR_SIGEN BIT4 +#define BRR_SIGEN BIT5 +#define CTO_SIGEN BIT16 +#define CCRC_SIGEN BIT17 +#define CEB_SIGEN BIT18 +#define CIE_SIGEN BIT19 +#define DTO_SIGEN BIT20 +#define DCRC_SIGEN BIT21 +#define DEB_SIGEN BIT22 +#define CERR_SIGEN BIT28 +#define BADA_SIGEN BIT29 + +#define MMCHS_AC12 (mMmcHsBase + 0x3C) +#define MMCHS_HC2R (mMmcHsBase + 0x3E) + +#define MMCHS_CAPA (mMmcHsBase + 0x40) +#define VS30 BIT25 +#define VS18 BIT26 + +#define MMCHS_CUR_CAPA (mMmcHsBase + 0x48) +#define MMCHS_REV (mMmcHsBase + 0xFC) + +#define BLOCK_COUNT_SHIFT 16 +#define RCA_SHIFT 16 + +#define CMD_R1 (RSP_TYPE_48BITS | CCCE_ENABLE | CICE_ENABLE) +#define CMD_R1B (RSP_TYPE_48BUSY | CCCE_ENABLE | CICE_ENABLE) +#define CMD_R2 (RSP_TYPE_136BITS | CCCE_ENABLE) +#define CMD_R3 (RSP_TYPE_48BITS) +#define CMD_R6 (RSP_TYPE_48BITS | CCCE_ENABLE | CICE_ENABLE) +#define CMD_R7 (RSP_TYPE_48BITS | CCCE_ENABLE | CICE_ENABLE) + +#define CMD_R1_ADTC (CMD_R1 | DP_ENABLE) +#define CMD_R1_ADTC_READ (CMD_R1_ADTC | DDIR_READ) +#define CMD_R1_ADTC_WRITE (CMD_R1_ADTC | DDIR_WRITE) + +#define CMD0 (INDX(0)) // Go idle +#define CMD1 (INDX(1) | CMD_R3) // MMC: Send Op Cond +#define CMD2 (INDX(2) | CMD_R2) // Send CID +#define CMD3 (INDX(3) | CMD_R6) // Set Relative Addr +#define CMD4 (INDX(4)) // Set DSR +#define CMD5 (INDX(5) | CMD_R1B) // SDIO: Sleep/Awake +#define CMD6 (INDX(6) | CMD_R1_ADTC_READ) // Switch +#define CMD7 (INDX(7) | CMD_R1B) // Select/Deselect +#define CMD8_SD (INDX(8) | CMD_R7) // Send If Cond +#define CMD8_SD_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0) +#define CMD8_MMC (INDX(8) | CMD_R1_ADTC_READ) // Send Ext Csd +#define CMD8_MMC_ARG (0) +#define CMD9 (INDX(9) | CMD_R2) // Send CSD +#define CMD10 (INDX(10) | CMD_R2) // Send CID +#define CMD11 (INDX(11) | CMD_R1) // Voltage Switch +#define CMD12 (INDX_ABORT(12) | CMD_R1B) // Stop Transmission +#define CMD13 (INDX(13) | CMD_R1) // Send Status +#define CMD15 (INDX(15)) // Go inactive state +#define CMD16 (INDX(16) | CMD_R1) // Set Blocklen +#define CMD17 (INDX(17) | CMD_R1_ADTC_READ) // Read Single Block +#define CMD18 (INDX(18) | CMD_R1_ADTC_READ | MSBS_MULTBLK) // Read Multiple Blocks +#define CMD19 (INDX(19) | CMD_R1_ADTC_READ) // SD: Send Tuning Block (64 bytes) +#define CMD20 (INDX(20) | CMD_R1B) // SD: Speed Class Control +#define CMD23 (INDX(23) | CMD_R1) // Set Block Count for CMD18 and CMD25 +#define CMD24 (INDX(24) | CMD_R1_ADTC_WRITE) // Write Block +#define CMD25 (INDX(25) | CMD_R1_ADTC_WRITE | MSBS_MULTBLK) // Write Multiple Blocks +#define CMD55 (INDX(55) | CMD_R1) // App Cmd + +#define ACMD6 (INDX(6) | CMD_R1) // Set Bus Width +#define ACMD22 (INDX(22) | CMD_R1_ADTC_READ) // SEND_NUM_WR_BLOCKS +#define ACMD41 (INDX(41) | CMD_R3) // Send Op Cond +#define ACMD51 (INDX(51) | CMD_R1_ADTC_READ) // Send SCR + +// User-friendly command names +#define CMD_IO_SEND_OP_COND CMD5 +#define CMD_SEND_CSD CMD9 // CSD: Card-Specific Data +#define CMD_STOP_TRANSMISSION CMD12 +#define CMD_SEND_STATUS CMD13 +#define CMD_READ_SINGLE_BLOCK CMD17 +#define CMD_READ_MULTIPLE_BLOCK CMD18 +#define CMD_SET_BLOCK_COUNT CMD23 +#define CMD_WRITE_SINGLE_BLOCK CMD24 +#define CMD_WRITE_MULTIPLE_BLOCK CMD25 + +#endif /* __BCM2836_SDIO_H__ */ From 8e5de81824763342dc4a6ba2b85ace7dc575c5b9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 1 Dec 2021 16:03:14 +0000 Subject: [PATCH 31/31] RFC: rpi: Enable booting with ACPI tables This is only partially implemented and includes RFC patches. So far it boots into grub but is unable to read the OS from the USB stick, presumably because the XHCI SSDT is missing. Signed-off-by: Simon Glass --- board/raspberrypi/rpi/Makefile | 2 + board/raspberrypi/rpi/rpi.c | 158 ++++++++++++++++++++++++++++++++- cmd/bootefi.c | 9 +- configs/rpi_4_defconfig | 17 ++++ 4 files changed, 180 insertions(+), 6 deletions(-) diff --git a/board/raspberrypi/rpi/Makefile b/board/raspberrypi/rpi/Makefile index b1186cdf100..bb1b7cc630f 100644 --- a/board/raspberrypi/rpi/Makefile +++ b/board/raspberrypi/rpi/Makefile @@ -4,3 +4,5 @@ obj-y := rpi.o obj-y += lowlevel_init.o + +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt_generated.o diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 2851ebc9853..543354c6466 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -3,6 +3,11 @@ * (C) Copyright 2012-2016 Stephen Warren */ +#define LOG_CATEGORY LOGC_BOARD + +#define DEBUG +#define LOG_DEBUG + #include #include #include @@ -11,19 +16,31 @@ #include #include #include +#include #include #include +#include +#include +#include +#include +#include #include #include #include #include -#include +#include +#include #include #ifdef CONFIG_ARM64 #include #endif #include #include +#ifdef CONFIG_GENERATE_ACPI_TABLE +#include "acpitables.h" +#endif +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -588,3 +605,142 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } + + +static int rpi_write_dbg2(struct acpi_ctx *ctx, const struct acpi_writer *entry) +{ + u64 addr = 0xfe201000; + char *name = "\\_SB.GDV0.URT0"; + + //TODO mini UART is not 100% compatible to 16550 (some registers are missing) + acpi_16550_mmio32_write_dbg2_uart(ctx, addr, name); + + return 0; +}; +ACPI_WRITER(5dbg2, "DBG2", rpi_write_dbg2, 0); + +#if 0 +/* Need to add a logo first */ +static int rpi_write_bgrt(struct acpi_ctx *ctx, const struct acpi_writer *entry) +{ + struct acpi_table_header *header; + struct acpi_bgrt_header *bgrt; + + bgrt = ctx->current; + header = &dbg2->header; + + memset(bgrt, '\0', sizeof(struct acpi_bgrt)); + + acpi_fill_header(header, "BGRT"); + header->revision = 0; + + acpi_inc(ctx, header->length); + + return 0; +}; +ACPI_WRITER(5bgrt, "BGRT", rpi_write_bgrt, 0); +#endif + +/* DMA Controller Vendor Data */ +struct __packed dma_ctlr_vendor_data { + u32 length; + u32 type; + u64 chan_base; + u32 chan_size; + u64 ctlr_base; + u32 ctlr_size; + u32 chan_count; + u32 ctlr_irq; + u32 min_req_line; + u32 max_req_line; + u8 cache_coherent; +}; + +/* DMA Controller */ +struct __packed rd_dma_ctlr { + struct acpi_csrt_descriptor hdr; + struct dma_ctlr_vendor_data data; +}; + +/* dma chan vendor data */ +struct __packed dma_chan_vendor_data { + u32 chan; + u32 chan_irq; + u16 is_reserved; + u16 addr_incr; +}; + +/* dma chan */ +struct __packed rd_dma_chan { + struct acpi_csrt_descriptor hdr; + struct dma_chan_vendor_data data; +}; + +/* dma resource group */ +struct __packed rg_dma { + struct acpi_csrt_group hdr; + struct rd_dma_ctlr ctlr; + struct rd_dma_chan chan[]; +}; + +#define RPI_DMA_MAX_REQ_LINES 32 + +static void add_cmd_chan(struct rd_dma_chan *dmac, uint uid, uint chan, + uint chan_irq, bool is_reserved, int addr_incr) +{ + memset(dmac, '\0', sizeof(*dmac)); + dmac->hdr.length = sizeof(struct rd_dma_chan); + dmac->hdr.type = EFI_ACPI_CSRT_RESOURCE_TYPE_DMA; + dmac->hdr.subtype = EFI_ACPI_CSRT_RESOURCE_SUBTYPE_DMA_CHANNEL; + dmac->hdr.uid = uid; + + dmac->data.chan = chan; + dmac->data.chan_irq = chan_irq; + dmac->data.is_reserved = is_reserved; + dmac->data.addr_incr = addr_incr; +} + +int acpi_fill_csrt(struct acpi_ctx *ctx) +{ + struct dma_ctlr_vendor_data *data; + struct acpi_csrt_group *hdr; + struct rg_dma *dma; + int i; + + dma = ctx->current; + hdr = &dma->hdr; + memset(hdr, '\0', sizeof(*hdr)); + hdr->length = 0; + hdr->vendor_id = SIGNATURE_32('R', 'P', 'I', 'F'); + hdr->device_id = EFI_ACPI_CSRT_DEVICE_ID_DMA; + + dma->ctlr.hdr.length = sizeof(struct rd_dma_ctlr); + dma->ctlr.hdr.type = EFI_ACPI_CSRT_RESOURCE_TYPE_DMA; + dma->ctlr.hdr.subtype = EFI_ACPI_CSRT_RESOURCE_SUBTYPE_DMA_CONTROLLER; + dma->ctlr.hdr.uid = EFI_ACPI_CSRT_RESOURCE_ID_IN_DMA_GRP; + + data = &dma->ctlr.data; + data->length = sizeof(struct dma_ctlr_vendor_data); + data->type = 1; + data->chan_base = BCM2836_DMA0_BASE_ADDRESS; + data->chan_size = RPI_DMA_CHANNEL_COUNT * BCM2836_DMA_CHANNEL_LENGTH; + data->ctlr_base = BCM2836_DMA_CTRL_BASE_ADDRESS; + data->ctlr_size = 8; + data->chan_count = RPI_DMA_USED_CHANNEL_COUNT; + data->max_req_line = RPI_DMA_MAX_REQ_LINES - 1; + + acpi_inc(ctx, sizeof(struct rg_dma)); + + for (i = 0; i < 10; i++) { + add_cmd_chan(&dma->chan[i], + EFI_ACPI_CSRT_RESOURCE_ID_IN_DMA_GRP + 1 + i, i, + 0x30 + i, + i == 1 || i == 2 || i == 3 || i == 6 || i == 7, + i == 4); + acpi_inc(ctx, sizeof(struct rd_dma_chan)); + } + + hdr->length = (u32)(ctx->current - (void *)dma); + + return 0; +} diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 7469c2a39b8..c1454ffb948 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -143,11 +143,10 @@ static int do_bootefi(struct cmd_tbl *cmdtp, int flag, int argc, if (argc > 2) { uintptr_t fdt_addr; - ret = efi_install_fdt(fdt); - if (ret == EFI_INVALID_PARAMETER) - return CMD_RET_USAGE; - else if (ret != EFI_SUCCESS) - return CMD_RET_FAILURE; + fdt_addr = hextoul(argv[2], NULL); + fdt = map_sysmem(fdt_addr, 0); + } else { + fdt = EFI_FDT_USE_INTERNAL; } if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR) && diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index f5fb322aa8f..a1b1ddca8af 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -18,6 +18,7 @@ CONFIG_PREBOOT="pci enum; usb start;" CONFIG_SYS_PBSIZE=1049 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_DFU=y @@ -65,3 +66,19 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_GENERATE_ACPI_TABLE=y +CONFIG_ACPI=y +CONFIG_CMD_ACPI=y +CONFIG_BOOTM_EFI=y +CONFIG_CMD_BOOTEFI=y +CONFIG_LOG=y +CONFIG_LOG_MAX_LEVEL=9 +CONFIG_LOG_DEFAULT_LEVEL=8 +CONFIG_LOGLEVEL=8 +CONFIG_LOGF_LINE=y +CONFIG_LOGF_FUNC=y +CONFIG_EFI_VARIABLE_NO_STORE=y +#CONFIG_EFI_RT_VOLATILE_STORE=y +CONFIG_HEXDUMP=y